Searched refs:M0 (Results 1 - 25 of 26) sorted by relevance

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/external/mesa3d/src/mesa/sparc/
H A Dsparc_matrix.h35 #define M0 %f16 macro
53 ldd [BASE + ( 0 * 0x4)], M0; \
59 ldd [BASE + ( 0 * 0x4)], M0; \
63 ld [BASE + ( 0 * 0x4)], M0; \
67 ldd [BASE + ( 0 * 0x4)], M0; \
73 ld [BASE + ( 0 * 0x4)], M0; \
78 ld [BASE + ( 0 * 0x4)], M0; \
82 ldd [BASE + ( 0 * 0x4)], M0; \
90 ld [BASE + ( 0 * 0x4)], M0; \
95 ldd [BASE + ( 0 * 0x4)], M0; \
[all...]
H A Dnorm.S60 fmuls %f0, M0, %f3 ! FGM Group
104 fmuls M0, %f15, M0
125 fmuls %f0, M0, %f3 ! FGM Group
199 fmuls %f0, M0, %f3 ! FGM Group
231 fmuls M0, %f15, M0
246 fmuls %f0, M0, %f3 ! FGM Group
291 fmuls M0, %f15, M0
[all...]
H A Dxform.S82 fmuls %f0, M0, %f1 ! FGM Group 1-cycle stall on %f0
86 fmuls %f8, M0, %f9 ! FGM Group f1 available
115 fmuls %f0, M0, %f1 ! FGM Group 1-cycle stall on %f0
197 fmuls %f0, M0, %f1 ! FGM Group
199 fmuls %f8, M0, %f9 ! FGM Group
218 fmuls %f0, M0, %f1
251 fmuls %f0, M0, %f1 ! FGM Group
252 fmuls %f4, M0, %f5 ! FGM Group
268 fmuls %f0, M0, %f1
299 fmuls %f0, M0,
[all...]
/external/mesa3d/src/gallium/drivers/radeon/
H A DSIRegisterInfo.cpp36 case AMDGPU::M0: return 124;
H A DSIISelLowering.cpp153 unsigned M0 = MRI.createVirtualRegister(&AMDGPU::M0RegRegClass); local
161 BuildMI(BB, I, BB.findDebugLoc(I), TII->get(AMDGPU::S_MOV_B32), M0)
168 .addReg(M0);
176 .addReg(M0);
189 unsigned M0 = MRI.createVirtualRegister(&AMDGPU::M0RegRegClass); local
191 BuildMI(BB, I, BB.findDebugLoc(I), TII->get(AMDGPU::S_MOV_B32), M0)
198 .addReg(M0);
H A DSIGenRegisterInfo.pl95 def M0 : SIReg <"M0">;
143 (add (sequence "SGPR%u", 0, $SGPR_MAX_IDX), SREG_LIT_0, M0)
174 def M0Reg : RegisterClass<"AMDGPU", [i32], 32, (add M0)>;
/external/llvm/unittests/Support/
H A DCommandLineTest.cpp53 explicit StackOption(const M0t &M0) : Base(M0) {} argument
57 StackOption(const M0t &M0, const M1t &M1) : Base(M0, M1) {} argument
61 StackOption(const M0t &M0, const M1t &M1, const M2t &M2) : Base(M0, M1, M2) {} argument
65 StackOption(const M0t &M0, const M1t &M1, const M2t &M2, const M3t &M3) argument
66 : Base(M0, M1, M2, M3) {}
/external/llvm/lib/Target/Hexagon/
H A DHexagonExpandPredSpillCode.cpp105 // Emit a "C6 = Rn, C6 is the control register for M0".
114 NewMI->addOperand(MachineOperand::CreateReg(Hexagon::M0,
148 // Emit a "C6 = Rn, C6 is the control register for M0".
158 NewMI->addOperand(MachineOperand::CreateReg(Hexagon::M0,
189 // Emit a "C6 = Rn, C6 is the control register for M0".
198 NewMI->addOperand(MachineOperand::CreateReg(Hexagon::M0,
226 // Emit a "C6 = Rn, C6 is the control register for M0".
234 NewMI->addOperand(MachineOperand::CreateReg(Hexagon::M0,
/external/llvm/unittests/Analysis/
H A DScalarEvolutionTest.cpp64 const SCEVMulExpr *M0 = cast<SCEVMulExpr>(P0); local
68 EXPECT_EQ(cast<SCEVConstant>(M0->getOperand(0))->getValue()->getZExtValue(),
76 EXPECT_EQ(cast<SCEVUnknown>(M0->getOperand(1))->getValue(), V0);
85 EXPECT_EQ(cast<SCEVUnknown>(M0->getOperand(1))->getValue(), V0);
/external/llvm/lib/Target/R600/
H A DSILowerControlFlow.cpp336 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_MOV_B32), AMDGPU::M0)
353 // Move index from VCC into M0
354 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_MOV_B32), AMDGPU::M0)
357 // Compare the just read M0 value to all possible Idx values
359 .addReg(AMDGPU::M0)
402 .addReg(AMDGPU::M0, RegState::Implicit)
424 .addReg(AMDGPU::M0, RegState::Implicit)
H A DSIRegisterInfo.cpp248 bool isM0 = SubReg == AMDGPU::M0;
267 BuildMI(*MBB, MI, DL, TII->get(AMDGPU::S_MOV_B32), AMDGPU::M0)
452 // VCC_LO, VCC_HI, EXEC_LO, EXEC_HI and M0.
H A DSIInsertWaits.cpp111 /// \brief Insert S_NOP between an instruction writing M0 and S_SENDMSG.
420 // There must be "S_NOP 0" between an instruction writing M0 and S_SENDMSG.
427 // Set whether this instruction sets M0
434 if (Op.isReg() && Op.isDef() && Op.getReg() == AMDGPU::M0)
H A DAMDGPUAsmPrinter.cpp278 case AMDGPU::M0:
H A DSIInstrInfo.cpp1246 if (MO.getReg() == AMDGPU::M0 || MO.getReg() == AMDGPU::VCC ||
/external/boringssl/src/crypto/poly1305/
H A Dpoly1305_vec.c289 xmmi M0, M1, M2, M3, M4; local
352 M0 = _mm_and_si128(MMASK, T5);
360 T5 = _mm_mul_epu32(M0, p->R20.v);
361 T6 = _mm_mul_epu32(M0, p->R21.v);
380 T5 = _mm_mul_epu32(M0, p->R22.v);
381 T6 = _mm_mul_epu32(M0, p->R23.v);
400 T5 = _mm_mul_epu32(M0, p->R24.v);
416 M0 = _mm_and_si128(MMASK, T5);
423 T0 = _mm_add_epi64(T0, M0);
478 xmmi M0, M local
[all...]
/external/opencv/cvaux/src/
H A Dcvbgfg_codebook.cpp238 uchar m0, m1, m2, M0, M1, M2; local
256 m0 = model->modMin[0]; M0 = model->modMax[0];
272 int h0 = p0 - M0, h1 = p1 - M1, h2 = p2 - M2;
/external/boringssl/src/crypto/bn/asm/
H A Darmv4-mont.pl270 my ($Bi,$Ni,$M0)=map("d$_",(28..31));
295 vld1.32 {${M0}[0]}, [$n0,:32]
309 vmul.u32 $Ni,$temp,$M0
363 vmul.u32 $Ni,$temp,$M0
488 vmul.u32 $Ni,$temp,$M0
/external/llvm/lib/Target/Hexagon/Disassembler/
H A DHexagonDisassembler.cpp139 Register = Hexagon::M0;
/external/mesa3d/src/gallium/drivers/radeon/MCTargetDesc/
H A DSIMCCodeEmitter.cpp295 case AMDGPU::M0: return 124;
/external/llvm/lib/Transforms/InstCombine/
H A DInstCombineMulDivRem.cpp586 Value *M0 = isNormalFp(cast<Constant>(M1)) ? local
589 if (M0 && M1) {
591 std::swap(M0, M1);
594 ? BinaryOperator::CreateFAdd(M0, M1)
595 : BinaryOperator::CreateFSub(M0, M1);
/external/llvm/lib/Target/R600/AsmParser/
H A DAMDGPUAsmParser.cpp416 .Case("m0", AMDGPU::M0)
911 Inst.addOperand(MCOperand::CreateReg(AMDGPU::M0)); // m0
944 Inst.addOperand(MCOperand::CreateReg(AMDGPU::M0)); // m0
/external/sonivox/jet_tools/JetCreator/
H A Dimg_Redo.py40 \x00\xca\xbcK\xc0\xe2\x14g:~M0\xce^?\xb2\xcd>\x94-\xd3\xae\x00\x92\xa2\xb6\
/external/llvm/lib/Target/R600/InstPrinter/
H A DAMDGPUInstPrinter.cpp142 case AMDGPU::M0:
/external/llvm/lib/CodeGen/SelectionDAG/
H A DDAGCombiner.cpp3514 int M0 = SV0->getMaskElt(i); local
3518 if (M0 < 0 && M1 < 0) {
3519 Mask1.push_back(M0);
3520 Mask2.push_back(M0);
3524 if (M0 < 0 || M1 < 0 ||
3525 (M0 < (int)NumElts && M1 < (int)NumElts) ||
3526 (M0 >= (int)NumElts && M1 >= (int)NumElts)) {
3531 Mask1.push_back(M0 < (int)NumElts ? M0 : M1 + NumElts);
3532 Mask2.push_back(M1 < (int)NumElts ? M1 : M0
[all...]
/external/boringssl/mac-x86_64/crypto/aes/
H A Dbsaes-x86_64.S2497 L$M0:

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