Searched refs:EXT (Results 1 - 25 of 32) sorted by last modified time

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/external/v8/src/mips/
H A Dassembler-mips.cc1944 GenInstrRegister(SPECIAL3, rs, rt, size - 1, pos, EXT);
H A Dconstants-mips.cc272 case EXT:
H A Dconstants-mips.h435 EXT = ((0 << 3) + 0),
H A Dsimulator-mips.cc2112 case EXT: { // Mips32r2 instruction.
2659 case EXT:
/external/v8/src/mips64/
H A Dassembler-mips64.cc2191 GenInstrRegister(SPECIAL3, rs, rt, size - 1, pos, EXT);
H A Dconstants-mips64.cc289 case EXT:
H A Dconstants-mips64.h436 EXT = ((0 << 3) + 0),
H A Dsimulator-mips64.cc2238 case EXT: { // Mips32r2 instruction.
2786 case EXT:
/external/skia/src/gpu/gl/
H A DGrGLAssembleInterface.cpp84 GET_PROC_SUFFIX(BlendColor, EXT);
91 GET_PROC_SUFFIX(BlendEquation, EXT);
138 GET_PROC_SUFFIX(GetQueryObjecti64v, EXT);
139 GET_PROC_SUFFIX(GetQueryObjectui64v, EXT);
157 GET_PROC_SUFFIX(MatrixLoadf, EXT);
158 GET_PROC_SUFFIX(MatrixLoadIdentity, EXT);
177 GET_PROC_SUFFIX(TexStorage2D, EXT);
248 GET_PROC_SUFFIX(GenFramebuffers, EXT);
249 GET_PROC_SUFFIX(GetFramebufferAttachmentParameteriv, EXT);
250 GET_PROC_SUFFIX(GetRenderbufferParameteriv, EXT);
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/external/skia/src/utils/win/
H A DSkWGL_win.cpp269 GET_PROC(SwapInterval, EXT);
/external/mesa3d/src/glsl/
H A Dglsl_parser_extras.cpp264 #define EXT(NAME, VS, GS, FS, GL, ES, SUPPORTED_FLAG) \ macro
276 EXT(ARB_conservative_depth, false, false, true, true, false, ARB_conservative_depth),
277 EXT(ARB_draw_buffers, false, false, true, true, false, dummy_true),
278 EXT(ARB_draw_instanced, true, false, false, true, false, ARB_draw_instanced),
279 EXT(ARB_explicit_attrib_location, true, false, true, true, false, ARB_explicit_attrib_location),
280 EXT(ARB_fragment_coord_conventions, true, false, true, true, false, ARB_fragment_coord_conventions),
281 EXT(ARB_texture_rectangle, true, false, true, true, false, dummy_true),
282 EXT(EXT_texture_array, true, false, true, true, false, EXT_texture_array),
283 EXT(ARB_shader_texture_lod, true, false, true, true, false, ARB_shader_texture_lod),
284 EXT(ARB_shader_stencil_expor
294 #undef EXT macro
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/external/mesa3d/src/mesa/main/
H A Dget.c210 #define EXT(f) \ macro
215 EXT(e), EXTRA_END \
220 EXT(e1), EXT(e2), EXTRA_END \
266 EXT(EXT_secondary_color),
272 EXT(EXT_fog_coord),
278 EXT(EXT_texture_integer),
289 EXT(ARB_texture_buffer_object),
294 EXT(ARB_uniform_buffer_object),
295 EXT(ARB_geometry_shader
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/external/lz4/examples/
H A DMakefile51 EXT =.exe macro
54 EXT = macro
64 $(CC) $(FLAGS) $^ -o $@$(EXT)
67 $(CC) $(FLAGS) $^ -o $@$(EXT)
70 $(CC) $(FLAGS) $^ -o $@$(EXT)
73 $(CC) $(FLAGS) $^ -o $@$(EXT)
76 $(CC) $(FLAGS) $^ -o $@$(EXT)
79 ./printVersion$(EXT)
80 ./doubleBuffer$(EXT) $(TESTFILE)
81 ./ringBuffer$(EXT)
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/external/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp832 case AArch64ISD::EXT: return "AArch64ISD::EXT";
4652 Src.ShuffleVec = DAG.getNode(AArch64ISD::EXT, dl, DestVT, VEXTSrc1,
4719 // check if an EXT instruction can handle the shuffle mask when the
4750 // check if an EXT instruction can handle the shuffle mask when the
4769 // The index of an EXT is the first element if it is not UNDEF.
4770 // Watch out for the beginning UNDEFs. The EXT index should be the expected
5077 return DAG.getNode(AArch64ISD::EXT, dl, VT, OpLHS, OpRHS,
5240 return DAG.getNode(AArch64ISD::EXT, dl, V1.getValueType(), V1, V2,
5245 return DAG.getNode(AArch64ISD::EXT, d
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H A DAArch64ISelLowering.h108 EXT, enumerator in enum:llvm::AArch64ISD::__anon10638
/external/linux-tools-perf/src/tools/lib/traceevent/
H A DMakefile27 EXT = -std=gnu99 macro
149 $(CC) -c $(CFLAGS) $(EXT) -fPIC $< -o $@)
174 $(CC) -c $(CFLAGS) $(EXT) $< -o $(obj)/$@;
/external/libvpx/libvpx/build/make/
H A Drtcd.pl419 --disable-EXT Disable support for EXT extensions
420 --require-EXT Require support for EXT extensions
/external/libhevc/common/arm64/
H A Dihevc_sao_edge_offset_class0.s153 EXT v21.16b, v21.16b , v17.16b,#15 //pu1_cur_row_tmp = vextq_u8(pu1_cur_row_tmp, pu1_cur_row, 15)
169 EXT v28.16b, v28.16b , v26.16b,#15 //II Iteration pu1_cur_row_tmp = vextq_u8(pu1_cur_row_tmp, pu1_cur_row, 15)
177 EXT v21.16b, v17.16b , v21.16b,#1 //pu1_cur_row_tmp = vextq_u8(pu1_cur_row, pu1_cur_row_tmp, 1)
189 EXT v28.16b, v26.16b , v28.16b,#1 //II pu1_cur_row_tmp = vextq_u8(pu1_cur_row, pu1_cur_row_tmp, 1)
293 EXT v21.16b, v21.16b , v17.16b,#15 //pu1_cur_row_tmp = vextq_u8(pu1_cur_row_tmp, pu1_cur_row, 15)
301 EXT v21.16b, v17.16b , v21.16b,#1 //pu1_cur_row_tmp = vextq_u8(pu1_cur_row, pu1_cur_row_tmp, 1)
316 EXT v20.16b, v20.16b , v22.16b,#15 //sign_left = vextq_s8(sign_left, sign_left, 15)
H A Dihevc_sao_edge_offset_class0_chroma.s177 EXT v21.16b, v21.16b , v19.16b,#14 //pu1_cur_row_tmp = vextq_u8(pu1_cur_row_tmp, pu1_cur_row, 14)
192 EXT v28.16b, v28.16b , v30.16b,#14 //II pu1_cur_row_tmp = vextq_u8(pu1_cur_row_tmp, pu1_cur_row, 14)
205 EXT v21.16b, v19.16b , v21.16b,#2 //pu1_cur_row_tmp = vextq_u8(pu1_cur_row, pu1_cur_row_tmp, 2)
216 EXT v28.16b, v30.16b , v28.16b,#2 //II pu1_cur_row_tmp = vextq_u8(pu1_cur_row, pu1_cur_row_tmp, 2)
361 EXT v21.16b, v21.16b , v19.16b,#14 //pu1_cur_row_tmp = vextq_u8(pu1_cur_row_tmp, pu1_cur_row, 15)
376 EXT v28.16b, v28.16b , v30.16b,#14 //II pu1_cur_row_tmp = vextq_u8(pu1_cur_row_tmp, pu1_cur_row, 15)
387 EXT v21.16b, v19.16b , v21.16b,#2 //pu1_cur_row_tmp = vextq_u8(pu1_cur_row, pu1_cur_row_tmp, 1)
402 EXT v28.16b, v30.16b , v28.16b,#2 //II pu1_cur_row_tmp = vextq_u8(pu1_cur_row, pu1_cur_row_tmp, 1)
H A Dihevc_sao_edge_offset_class2.s294 EXT v18.16b, v16.16b , v18.16b,#1 //I pu1_next_row_tmp = vextq_u8(pu1_next_row, pu1_next_row_tmp, 1)
327 EXT v17.16b, v17.16b , v17.16b,#15 //I sign_up = vextq_s8(sign_up, sign_up, 15)
365 EXT v22.16b, v16.16b , v28.16b,#1 //II pu1_next_row_tmp = vextq_u8(pu1_next_row, pu1_next_row_tmp, 1)
374 EXT v18.16b, v30.16b , v18.16b,#1 //III pu1_next_row_tmp = vextq_u8(pu1_next_row, pu1_next_row_tmp, 1)
409 EXT v17.16b, v17.16b , v17.16b,#15 //II sign_up = vextq_s8(sign_up, sign_up, 15)
424 EXT v17.16b, v17.16b , v17.16b,#15 //III sign_up = vextq_s8(sign_up, sign_up, 15)
480 EXT v18.16b, v16.16b , v18.16b,#1 //pu1_next_row_tmp = vextq_u8(pu1_next_row, pu1_next_row_tmp, 1)
501 EXT v17.16b, v17.16b , v17.16b,#15 //sign_up = vextq_s8(sign_up, sign_up, 15)
609 EXT v18.16b, v16.16b , v18.16b,#1 //pu1_next_row_tmp = vextq_u8(pu1_next_row, pu1_next_row_tmp, 1)
644 EXT v1
[all...]
H A Dihevc_sao_edge_offset_class2_chroma.s407 EXT v18.16b, v16.16b , v18.16b,#2 //I pu1_next_row_tmp = vextq_u8(pu1_next_row, pu1_next_row_tmp, 2)
455 EXT v17.16b, v17.16b , v17.16b,#14 //I sign_up = vextq_s8(sign_up, sign_up, 14)
506 EXT v28.16b, v16.16b , v28.16b,#2 //II pu1_next_row_tmp = vextq_u8(pu1_next_row, pu1_next_row_tmp, 2)
519 EXT v18.16b, v30.16b , v18.16b,#2 //III pu1_next_row_tmp = vextq_u8(pu1_next_row, pu1_next_row_tmp, 2)
571 EXT v17.16b, v17.16b , v17.16b,#14 //II sign_up = vextq_s8(sign_up, sign_up, 14)
614 EXT v17.16b, v17.16b , v17.16b,#14 //III sign_up = vextq_s8(sign_up, sign_up, 14)
676 EXT v18.16b, v16.16b , v18.16b,#2 //pu1_next_row_tmp = vextq_u8(pu1_next_row, pu1_next_row_tmp, 2)
832 EXT v18.16b, v16.16b , v18.16b,#2 //pu1_next_row_tmp = vextq_u8(pu1_next_row, pu1_next_row_tmp, 2)
883 EXT v17.16b, v17.16b , v17.16b,#14 //sign_up = vextq_s8(sign_up, sign_up, 14)
990 EXT v1
[all...]
H A Dihevc_sao_edge_offset_class3.s308 EXT v18.16b, v18.16b , v16.16b,#15 //I pu1_next_row_tmp = vextq_u8(pu1_next_row_tmp, pu1_next_row, 15)
335 EXT v17.16b, v17.16b , v17.16b,#1 //I sign_up = vextq_s8(sign_up, sign_up, 1)
385 EXT v18.16b, v18.16b , v16.16b,#15 //II pu1_next_row_tmp = vextq_u8(pu1_next_row_tmp, pu1_next_row, 15)
423 EXT v18.16b, v18.16b , v30.16b,#15 //III pu1_next_row_tmp = vextq_u8(pu1_next_row_tmp, pu1_next_row, 15)
427 EXT v17.16b, v17.16b , v17.16b,#1 //II sign_up = vextq_s8(sign_up, sign_up, 1)
450 EXT v17.16b, v17.16b , v17.16b,#1 //III sign_up = vextq_s8(sign_up, sign_up, 1)
513 EXT v18.16b, v18.16b , v16.16b,#15 //pu1_next_row_tmp = vextq_u8(pu1_next_row_tmp, pu1_next_row, 15)
647 EXT v18.16b, v18.16b , v16.16b,#15 //pu1_next_row_tmp = vextq_u8(pu1_next_row_tmp, pu1_next_row, 15)
682 EXT v17.16b, v17.16b , v17.16b,#1 //sign_up = vextq_s8(sign_up, sign_up, 1)
787 EXT v1
[all...]
H A Dihevc_sao_edge_offset_class3_chroma.s396 EXT v18.16b, v18.16b , v16.16b,#14 //I pu1_next_row_tmp = vextq_u8(pu1_next_row_tmp, pu1_next_row, 14)
440 EXT v17.16b, v17.16b , v17.16b,#2 //I sign_up = vextq_s8(sign_up, sign_up, 2)
500 EXT v28.16b, v28.16b , v16.16b,#14 //II pu1_next_row_tmp = vextq_u8(pu1_next_row_tmp, pu1_next_row, 14)
544 EXT v18.16b, v18.16b , v30.16b,#14 //III pu1_next_row_tmp = vextq_u8(pu1_next_row_tmp, pu1_next_row, 14)
564 EXT v17.16b, v17.16b , v17.16b,#2 //II sign_up = vextq_s8(sign_up, sign_up, 2)
596 EXT v17.16b, v17.16b , v17.16b,#2 //III sign_up = vextq_s8(sign_up, sign_up, 2)
675 EXT v18.16b, v18.16b , v16.16b,#14 //pu1_next_row_tmp = vextq_u8(pu1_next_row_tmp, pu1_next_row, 14)
838 EXT v18.16b, v18.16b , v16.16b,#14 //pu1_next_row_tmp = vextq_u8(pu1_next_row_tmp, pu1_next_row, 14)
890 EXT v17.16b, v17.16b , v17.16b,#2 //sign_up = vextq_s8(sign_up, sign_up, 2)
1022 EXT v1
[all...]
/external/icu/icu4j/main/classes/charset/src/com/ibm/icu/charset/
H A DCharsetISCII.java31 private static final short EXT = 0xf0; /* Extension code */ field in class:CharsetISCII
808 * ii) EXT : Extention code is used to declare switching to Sanskrit and for obscure,
877 } else if (data.contextCharToUnicode == EXT) {
903 /* only 0xA1 - 0xEE are legal after EXT char */
931 case EXT: /* falls through */
1132 if (data.contextCharToUnicode == ATR || data.contextCharToUnicode == EXT || data.contextCharToUnicode == ISCII_INV) {
/external/icu/icu4c/source/common/
H A Ducnvisci.c15 * 24/7/2001 Ram Added support for EXT character handling
38 #define EXT 0xF0 /* Extension code */ macro
1161 * ii) EXT : Extention code is used to declare switching to Sanskrit and for obscure,
1235 } else if (*contextCharToUnicode==EXT) {
1261 /* only 0xA1 - 0xEE are legal after EXT char */
1287 case EXT: /*falls through*/
1495 if (*contextCharToUnicode==ATR || *contextCharToUnicode==EXT || *contextCharToUnicode==ISCII_INV) {

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