/art/compiler/utils/mips/ |
H A D | assembler_mips.h | 58 void Add(Register rd, Register rs, Register rt); 59 void Addu(Register rd, Register rs, Register rt); 60 void Addi(Register rt, Register rs, uint16_t imm16); 61 void Addiu(Register rt, Register r [all...] |
H A D | assembler_mips.cc | 42 void MipsAssembler::EmitR(int opcode, Register rs, Register rt, Register rd, int shamt, int funct) { 55 void MipsAssembler::EmitI(int opcode, Register rs, Register rt, uint16_t imm) { 93 void MipsAssembler::EmitBranch(Register rt, Register rs, Label* label, bool equal) { 163 void MipsAssembler::Add(Register rd, Register rs, Register r [all...] |
/art/compiler/utils/arm/ |
H A D | assembler_thumb2.h | 64 void and_(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) OVERRIDE; 66 void eor(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) OVERRIDE; 68 void sub(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) OVERRIDE; 69 void subs(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) OVERRIDE; 71 void rsb(Register rd, Register r [all...] |
H A D | assembler_arm32.h | 42 void and_(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) OVERRIDE; 44 void eor(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) OVERRIDE; 46 void sub(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) OVERRIDE; 47 void subs(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) OVERRIDE; 49 void rsb(Register rd, Register r [all...] |
H A D | assembler_arm.h | 44 // Data-processing operands - Register 45 explicit ShifterOperand(Register rm) : type_(kRegister), rm_(rm), rs_(kNoRegister), 54 ShifterOperand(Register rm, Shift shift, uint32_t shift_imm = 0) : type_(kRegister), rm_(rm), 60 ShifterOperand(Register rm, Shift shift, Register rs) : type_(kRegister), rm_(rm), 99 Register GetRegister() const { 103 Register GetSecondRegister() const { 115 Register rm_; 116 Register rs_; 185 Address(Register r [all...] |
H A D | assembler_arm32.cc | 51 bool Arm32Assembler::ShifterOperandCanHold(Register rd ATTRIBUTE_UNUSED, 52 Register rn ATTRIBUTE_UNUSED, 59 void Arm32Assembler::and_(Register rd, Register rn, const ShifterOperand& so, 65 void Arm32Assembler::eor(Register rd, Register rn, const ShifterOperand& so, 71 void Arm32Assembler::sub(Register rd, Register rn, const ShifterOperand& so, 76 void Arm32Assembler::rsb(Register rd, Register r [all...] |
H A D | assembler_thumb2.cc | 28 bool Thumb2Assembler::ShifterOperandCanHold(Register rd ATTRIBUTE_UNUSED, 29 Register rn ATTRIBUTE_UNUSED, 54 void Thumb2Assembler::and_(Register rd, Register rn, const ShifterOperand& so, 60 void Thumb2Assembler::eor(Register rd, Register rn, const ShifterOperand& so, 66 void Thumb2Assembler::sub(Register rd, Register rn, const ShifterOperand& so, 72 void Thumb2Assembler::rsb(Register rd, Register r [all...] |
H A D | assembler_thumb2_test.cc | 25 arm::Register, arm::SRegister, 48 new arm::Register(arm::R0), 49 new arm::Register(arm::R1), 50 new arm::Register(arm::R2), 51 new arm::Register(arm::R3), 52 new arm::Register(arm::R4), 53 new arm::Register(arm::R5), 54 new arm::Register(arm::R6), 55 new arm::Register(arm::R7), 56 new arm::Register(ar [all...] |
/art/compiler/utils/x86/ |
H A D | assembler_x86_test.cc | 33 class AssemblerX86Test : public AssemblerTest<x86::X86Assembler, x86::Register, 52 new x86::Register(x86::EAX), 53 new x86::Register(x86::EBX), 54 new x86::Register(x86::ECX), 55 new x86::Register(x86::EDX), 56 new x86::Register(x86::EBP), 57 new x86::Register(x86::ESP), 58 new x86::Register(x86::ESI), 59 new x86::Register(x86::EDI) 84 std::vector<x86::Register*> GetRegister [all...] |
H A D | assembler_x86.h | 54 Register rm() const { 55 return static_cast<Register>(encoding_at(0) & 7); 62 Register index() const { 63 return static_cast<Register>((encoding_at(1) >> 3) & 7); 66 Register base() const { 67 return static_cast<Register>(encoding_at(1) & 7); 82 bool IsRegister(Register reg) const { 84 && ((encoding_[0] & 0x07) == reg); // Register codes match. 91 void SetModRM(int mod_in, Register rm_in) { 97 void SetSIB(ScaleFactor scale_in, Register index_i [all...] |
H A D | assembler_x86.cc | 35 void X86Assembler::call(Register reg) { 68 void X86Assembler::pushl(Register reg) { 93 void X86Assembler::popl(Register reg) { 106 void X86Assembler::movl(Register dst, const Immediate& imm) { 113 void X86Assembler::movl(Register dst, Register src) { 120 void X86Assembler::movl(Register dst, const Address& src) { 127 void X86Assembler::movl(const Address& dst, Register src) { 148 void X86Assembler::bswapl(Register dst) { 154 void X86Assembler::movzxb(Register ds [all...] |
/art/runtime/arch/x86/ |
H A D | registers_x86.h | 29 enum Register { enum in namespace:art::x86 42 std::ostream& operator<<(std::ostream& os, const Register& rhs);
|
H A D | registers_x86.cc | 27 std::ostream& operator<<(std::ostream& os, const Register& rhs) { 31 os << "Register[" << static_cast<int>(rhs) << "]";
|
/art/compiler/optimizing/ |
H A D | intrinsics_arm.cc | 53 Register trg_reg_lo = trg.AsRegisterPairLow<Register>(); 54 Register trg_reg_hi = trg.AsRegisterPairHigh<Register>(); 55 Register res_reg_lo = R0; 56 Register res_reg_hi = R1; 69 Register trg_reg = trg.AsRegister<Register>(); 70 Register res_reg = R0; 160 __ vmovrrd(output.AsRegisterPairLow<Register>(), [all...] |
H A D | code_generator_arm.cc | 46 static constexpr Register kCoreSavedRegisterForBaseline = R5; 47 static constexpr Register kCoreCalleeSaves[] = 350 stream << ArmManagedRegister::FromCoreRegister(Register(reg)); 358 __ StoreToOffset(kStoreWord, static_cast<Register>(reg_id), SP, stack_index); 363 __ LoadFromOffset(kLoadWord, static_cast<Register>(reg_id), SP, stack_index); 517 static dwarf::Reg DWARFReg(Register reg) { 717 __ Mov(destination.AsRegister<Register>(), source.AsRegister<Register>()); 719 __ vmovrs(destination.AsRegister<Register>(), source.AsFpuRegister<SRegister>()); 721 __ LoadFromOffset(kLoadWord, destination.AsRegister<Register>(), S [all...] |
H A D | code_generator_arm.h | 37 static constexpr Register kParameterCoreRegisters[] = { R1, R2, R3 }; 43 static constexpr Register kArtMethodRegister = R0; 45 static constexpr Register kRuntimeParameterCoreRegisters[] = { R0, R1, R2, R3 }; 52 class InvokeRuntimeCallingConvention : public CallingConvention<Register, SRegister> { 71 class InvokeDexCallingConvention : public CallingConvention<Register, SRegister> { 112 void Exchange(Register reg, int mem); 177 void GenerateClassInitializationCheck(SlowPathCodeARM* slow_path, Register class_reg); 181 void GenerateWideAtomicStore(Register addr, uint32_t offset, 182 Register value_lo, Register value_h [all...] |
H A D | code_generator_x86.cc | 40 static constexpr Register kCoreCalleeSaves[] = { EBP, ESI, EDI }; 44 static constexpr int kFakeReturnRegister = Register(8); 80 explicit DivRemMinusOneSlowPathX86(Register reg, bool is_div) : reg_(reg), is_div_(is_div) {} 93 Register reg_; 343 stream << X86ManagedRegister::FromCpuRegister(Register(reg)); 351 __ movl(Address(ESP, stack_index), static_cast<Register>(reg_id)); 356 __ movl(static_cast<Register>(reg_id), Address(ESP, stack_index)); 411 Register reg = static_cast<Register>( 469 static dwarf::Reg DWARFReg(Register re [all...] |
H A D | intrinsics_x86.cc | 77 Register target_reg = target.AsRegister<Register>(); 84 Register target_reg_lo = target.AsRegisterPairLow<Register>(); 85 Register target_reg_hi = target.AsRegisterPairHigh<Register>(); 200 __ movd(output.AsRegisterPairLow<Register>(), temp); 202 __ movd(output.AsRegisterPairHigh<Register>(), temp); 204 __ movd(output.AsRegister<Register>(), input.AsFpuRegister<XmmRegister>()); 215 __ movd(temp1, input.AsRegisterPairLow<Register>()); [all...] |
H A D | code_generator_x86.h | 36 static constexpr Register kParameterCoreRegisters[] = { ECX, EDX, EBX }; 42 static constexpr Register kRuntimeParameterCoreRegisters[] = { EAX, ECX, EDX, EBX }; 49 class InvokeRuntimeCallingConvention : public CallingConvention<Register, XmmRegister> { 62 class InvokeDexCallingConvention : public CallingConvention<Register, XmmRegister> { 106 void Exchange(Register reg, int mem); 160 void GenerateClassInitializationCheck(SlowPathCodeX86* slow_path, Register class_reg); 168 void GenerateShlLong(const Location& loc, Register shifter); 169 void GenerateShrLong(const Location& loc, Register shifter); 170 void GenerateUShrLong(const Location& loc, Register shifter); 262 void GenerateStaticOrDirectCall(HInvokeStaticOrDirect* invoke, Register tem [all...] |
H A D | common_arm64.h | 54 static inline vixl::Register XRegisterFrom(Location location) { 56 return vixl::Register::XRegFromCode(VIXLRegCodeFromART(location.reg())); 59 static inline vixl::Register WRegisterFrom(Location location) { 61 return vixl::Register::WRegFromCode(VIXLRegCodeFromART(location.reg())); 64 static inline vixl::Register RegisterFrom(Location location, Primitive::Type type) { 69 static inline vixl::Register OutputRegister(HInstruction* instr) { 73 static inline vixl::Register InputRegisterAt(HInstruction* instr, int input_index) { 148 static inline vixl::MemOperand HeapOperand(const vixl::Register& base, size_t offset = 0) { 154 static inline vixl::MemOperand HeapOperand(const vixl::Register& base, Offset offset) { 162 static inline Location LocationFrom(const vixl::Register [all...] |
/art/runtime/arch/x86_64/ |
H A D | registers_x86_64.h | 29 enum Register { enum in namespace:art::x86_64 50 std::ostream& operator<<(std::ostream& os, const Register& rhs);
|
H A D | registers_x86_64.cc | 28 std::ostream& operator<<(std::ostream& os, const Register& rhs) { 32 os << "Register[" << static_cast<int>(rhs) << "]"; 41 os << "Register[" << static_cast<int>(rhs) << "]";
|
/art/compiler/utils/x86_64/ |
H A D | constants_x86_64.h | 32 explicit CpuRegister(Register r) : reg_(r) {} 33 explicit CpuRegister(int r) : reg_(Register(r)) {} 34 Register AsRegister() const { 44 const Register reg_;
|
/art/runtime/arch/arm/ |
H A D | registers_arm.cc | 28 std::ostream& operator<<(std::ostream& os, const Register& rhs) { 32 os << "Register[" << static_cast<int>(rhs) << "]";
|
/art/runtime/arch/mips/ |
H A D | registers_mips.cc | 30 std::ostream& operator<<(std::ostream& os, const Register& rhs) { 34 os << "Register[" << static_cast<int>(rhs) << "]";
|