/external/llvm/include/llvm/MC/ |
H A D | MCInstrItineraries.h | 186 /// itinerary class UseClass, operand index UseIdx. 188 unsigned UseClass, unsigned UseIdx) const { 198 if ((FirstUseIdx + UseIdx) >= LastUseIdx) 202 Forwardings[FirstUseIdx + UseIdx]; 209 unsigned UseClass, unsigned UseIdx) const { 217 int UseCycle = getOperandCycle(UseClass, UseIdx); 223 hasPipelineForwarding(DefClass, DefIdx, UseClass, UseIdx))
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H A D | MCSubtargetInfo.h | 120 int getReadAdvanceCycles(const MCSchedClassDesc *SC, unsigned UseIdx, argument 127 if (I->UseIdx < UseIdx) 129 if (I->UseIdx > UseIdx)
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H A D | MCSchedule.h | 84 /// MCReadAdvanceEntries are sorted first by operand index (UseIdx), then by 87 unsigned UseIdx; member in struct:llvm::MCReadAdvanceEntry 92 return UseIdx == Other.UseIdx && WriteResourceID == Other.WriteResourceID
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/external/llvm/lib/CodeGen/ |
H A D | TargetSchedule.cpp | 144 unsigned UseIdx = 0; local 148 ++UseIdx; 150 return UseIdx; 202 unsigned UseIdx = findUseIdx(UseMI, UseOperIdx); local 203 int Advance = STI->getReadAdvanceCycles(UseDesc, UseIdx, WriteID);
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H A D | LiveRangeEdit.cpp | 81 /// OrigIdx are also available with the same value at UseIdx. 84 SlotIndex UseIdx) const { 86 UseIdx = UseIdx.getRegSlot(true); 107 if (SlotIndex::isSameInstr(OrigIdx, UseIdx)) 110 if (OVNI != li.getVNInfoAt(UseIdx)) 117 SlotIndex UseIdx, 140 if (!allUsesAvailableAt(RM.OrigMI, DefIdx, UseIdx)) 116 canRematerializeAt(Remat &RM, SlotIndex UseIdx, bool cheapAsAMove) argument
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H A D | LiveRangeCalc.cpp | 169 SlotIndex UseIdx; local 174 UseIdx = Indexes->getMBBEndIdx(MI->getOperand(OpNo+1).getMBB()); 186 UseIdx = Indexes->getInstructionIndex(MI).getRegSlot(isEarlyClobber); 191 extend(LR, UseIdx, Reg);
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H A D | TargetInstrInfo.cpp | 723 SDNode *UseNode, unsigned UseIdx) const { 734 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx); 812 const MachineInstr *UseMI, unsigned UseIdx) const { 815 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx); 845 /// UseIdx to compute min latency. 849 const MachineInstr *UseMI, unsigned UseIdx) const { 859 OperLatency = getOperandLatency(ItinData, DefMI, DefIdx, UseMI, UseIdx);
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H A D | InlineSpiller.cpp | 867 SlotIndex UseIdx = LIS.getInstructionIndex(MI).getRegSlot(true); 868 VNInfo *ParentVNI = VirtReg.getVNInfoAt(UseIdx.getBaseIndex()); 877 DEBUG(dbgs() << UseIdx << '\t' << *MI); 889 if (!Edit->canRematerializeAt(RM, UseIdx, false)) { 891 DEBUG(dbgs() << "\tcannot remat for " << UseIdx << '\t' << *MI); 899 DEBUG(dbgs() << "\tcannot remat tied reg: " << UseIdx << '\t' << *MI); 930 DEBUG(dbgs() << "\t " << UseIdx << '\t' << *MI << '\n');
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H A D | RegisterCoalescer.cpp | 681 SlotIndex UseIdx = LIS->getInstructionIndex(UseMI); local 682 LiveInterval::iterator US = IntA.FindSegmentContaining(UseIdx); 734 SlotIndex UseIdx = LIS->getInstructionIndex(UseMI).getRegSlot(true); local 735 LiveInterval::iterator US = IntA.FindSegmentContaining(UseIdx); 755 SlotIndex DefIdx = UseIdx.getRegSlot(); 1102 SlotIndex UseIdx = LIS->getInstructionIndex(&MI); local 1110 if (SR.liveAt(UseIdx)) { 1116 isLive = DstLI.liveAt(UseIdx); 1120 DEBUG(dbgs() << "\tnew undef: " << UseIdx << '\t' << MI); 1177 SlotIndex UseIdx local [all...] |
H A D | SplitKit.h | 315 /// defFromParent - Define Reg from ParentVNI at UseIdx using either 319 SlotIndex UseIdx,
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H A D | MachineVerifier.cpp | 1004 SlotIndex UseIdx = LiveInts->getInstructionIndex(MI); local 1009 LiveQueryResult LRQ = LR->Query(UseIdx); 1012 errs() << UseIdx << " is not live in " << PrintRegUnit(*Units, TRI) 1027 LiveQueryResult LRQ = LI.Query(UseIdx); 1030 errs() << UseIdx << " is not live in " << LI << '\n';
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H A D | MachineInstr.cpp | 1222 /// tieOperands - Mark operands at DefIdx and UseIdx as tied to each other. 1234 void MachineInstr::tieOperands(unsigned DefIdx, unsigned UseIdx) { argument 1236 MachineOperand &UseMO = getOperand(UseIdx); 1238 assert(UseMO.isUse() && "UseIdx must be a use operand"); 1252 // UseIdx can be out of range, we'll search for it in findTiedOperandIdx(). 1253 DefMO.TiedTo = std::min(UseIdx + 1, TiedMax);
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H A D | TwoAddressInstructionPass.cpp | 1555 SlotIndex UseIdx = MIIdx.getRegSlot(IsEarlyClobber); local 1556 if (I->end == UseIdx) 1557 LI.removeSegment(LastCopyIdx, UseIdx);
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H A D | SplitKit.cpp | 418 SlotIndex UseIdx, 431 if (Edit->canRematerializeAt(RM, UseIdx, true)) { 416 defFromParent(unsigned RegIdx, VNInfo *ParentVNI, SlotIndex UseIdx, MachineBasicBlock &MBB, MachineBasicBlock::iterator I) argument
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/external/llvm/lib/Target/ARM/ |
H A D | ARMBaseInstrInfo.h | 279 unsigned UseIdx) const override; 282 SDNode *UseNode, unsigned UseIdx) const override; 311 unsigned UseIdx, unsigned UseAlign) const; 315 unsigned UseIdx, unsigned UseAlign) const; 320 unsigned UseIdx, unsigned UseAlign) const; 335 unsigned UseIdx) const override;
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H A D | ARMBaseInstrInfo.cpp | 3200 unsigned UseIdx, unsigned UseAlign) const { 3201 int RegNo = (int)(UseIdx+1) - UseMCID.getNumOperands() + 1; 3203 return ItinData->getOperandCycle(UseClass, UseIdx); 3240 unsigned UseIdx, unsigned UseAlign) const { 3241 int RegNo = (int)(UseIdx+1) - UseMCID.getNumOperands() + 1; 3243 return ItinData->getOperandCycle(UseClass, UseIdx); 3270 unsigned UseIdx, unsigned UseAlign) const { 3274 if (DefIdx < DefMCID.getNumDefs() && UseIdx < UseMCID.getNumOperands()) 3275 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx); 3325 UseCycle = ItinData->getOperandCycle(UseClass, UseIdx); 3197 getVSTMUseCycle(const InstrItineraryData *ItinData, const MCInstrDesc &UseMCID, unsigned UseClass, unsigned UseIdx, unsigned UseAlign) const argument 3237 getSTMUseCycle(const InstrItineraryData *ItinData, const MCInstrDesc &UseMCID, unsigned UseClass, unsigned UseIdx, unsigned UseAlign) const argument 3266 getOperandLatency(const InstrItineraryData *ItinData, const MCInstrDesc &DefMCID, unsigned DefIdx, unsigned DefAlign, const MCInstrDesc &UseMCID, unsigned UseIdx, unsigned UseAlign) const argument 3400 getBundledUseMI(const TargetRegisterInfo *TRI, const MachineInstr *MI, unsigned Reg, unsigned &UseIdx, unsigned &Dist) argument [all...] |
/external/llvm/include/llvm/CodeGen/ |
H A D | LiveRangeEdit.h | 87 /// OrigIdx are also available with the same value at UseIdx. 89 SlotIndex UseIdx) const; 179 /// UseIdx. It is assumed that parent_.getVNINfoAt(UseIdx) == ParentVNI. 182 SlotIndex UseIdx,
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H A D | MachineInstr.h | 980 /// UseIdx. The tie will cause the register allocator to ensure that the two 985 void tieOperands(unsigned DefIdx, unsigned UseIdx);
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/external/llvm/lib/Target/PowerPC/ |
H A D | PPCInstrInfo.h | 101 unsigned UseIdx) const override; 104 SDNode *UseNode, unsigned UseIdx) const override { 106 UseNode, UseIdx);
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H A D | PPCInstrInfo.cpp | 109 unsigned UseIdx) const { 111 UseMI, UseIdx); 1113 unsigned UseIdx; local 1114 for (UseIdx = 0; UseIdx < UseMI->getNumOperands(); ++UseIdx) 1115 if (UseMI->getOperand(UseIdx).isReg() && 1116 UseMI->getOperand(UseIdx).getReg() == Reg) 1119 assert(UseIdx < UseMI->getNumOperands() && "Cannot find Reg in UseMI"); 1120 assert(UseIdx < UseMCI [all...] |
/external/llvm/include/llvm/Target/ |
H A D | TargetInstrInfo.h | 1026 SDNode *UseNode, unsigned UseIdx) const; 1039 unsigned UseIdx) const; 1045 const MachineInstr *UseMI, unsigned UseIdx) 1080 const MachineInstr *UseMI, unsigned UseIdx) const {
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/external/llvm/utils/TableGen/ |
H A D | SubtargetEmitter.cpp | 979 // Entries must be sorted first by UseIdx then by WriteResourceID. 980 for (unsigned UseIdx = 0, EndIdx = Reads.size(); 981 UseIdx != EndIdx; ++UseIdx) { 983 FindReadAdvance(SchedModels.getSchedRead(Reads[UseIdx]), ProcModel); 1005 RAEntry.UseIdx = UseIdx; 1110 OS << "\n// {UseIdx, WriteResourceID, Cycles}\n" 1117 OS << " {" << RAEntry.UseIdx << ", "
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/external/llvm/lib/Target/X86/ |
H A D | X86InstrInfo.h | 427 unsigned UseIdx) const override;
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H A D | X86InstrInfo.cpp | 6216 const MachineInstr *UseMI, unsigned UseIdx) const {
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/external/llvm/lib/CodeGen/SelectionDAG/ |
H A D | InstrEmitter.cpp | 1000 unsigned UseIdx = GroupIdx.back() + 1; 1002 MIB->tieOperands(DefIdx + j, UseIdx + j);
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