gen_common.cc revision bfea9c29e809e04bde4a46591fea64c5a7b922fb
1/* 2 * Copyright (C) 2012 The Android Open Source Project 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17#include "dex/compiler_ir.h" 18#include "dex/compiler_internals.h" 19#include "dex/quick/mir_to_lir-inl.h" 20#include "entrypoints/quick/quick_entrypoints.h" 21#include "mirror/array.h" 22#include "mirror/object-inl.h" 23#include "verifier/method_verifier.h" 24#include <functional> 25 26namespace art { 27 28/* 29 * This source files contains "gen" codegen routines that should 30 * be applicable to most targets. Only mid-level support utilities 31 * and "op" calls may be used here. 32 */ 33 34/* 35 * Generate a kPseudoBarrier marker to indicate the boundary of special 36 * blocks. 37 */ 38void Mir2Lir::GenBarrier() { 39 LIR* barrier = NewLIR0(kPseudoBarrier); 40 /* Mark all resources as being clobbered */ 41 DCHECK(!barrier->flags.use_def_invalid); 42 barrier->u.m.def_mask = ENCODE_ALL; 43} 44 45// TODO: need to do some work to split out targets with 46// condition codes and those without 47LIR* Mir2Lir::GenCheck(ConditionCode c_code, ThrowKind kind) { 48 DCHECK_NE(cu_->instruction_set, kMips); 49 LIR* tgt = RawLIR(0, kPseudoThrowTarget, kind, current_dalvik_offset_); 50 LIR* branch = OpCondBranch(c_code, tgt); 51 // Remember branch target - will process later 52 throw_launchpads_.Insert(tgt); 53 return branch; 54} 55 56LIR* Mir2Lir::GenImmedCheck(ConditionCode c_code, int reg, int imm_val, ThrowKind kind) { 57 LIR* tgt = RawLIR(0, kPseudoThrowTarget, kind, current_dalvik_offset_, reg, imm_val); 58 LIR* branch; 59 if (c_code == kCondAl) { 60 branch = OpUnconditionalBranch(tgt); 61 } else { 62 branch = OpCmpImmBranch(c_code, reg, imm_val, tgt); 63 } 64 // Remember branch target - will process later 65 throw_launchpads_.Insert(tgt); 66 return branch; 67} 68 69 70/* Perform null-check on a register. */ 71LIR* Mir2Lir::GenNullCheck(int m_reg, int opt_flags) { 72 if (Runtime::Current()->ExplicitNullChecks()) { 73 if (!(cu_->disable_opt & (1 << kNullCheckElimination)) && (opt_flags & MIR_IGNORE_NULL_CHECK)) { 74 return NULL; 75 } 76 return GenImmedCheck(kCondEq, m_reg, 0, kThrowNullPointer); 77 } 78 return nullptr; 79} 80 81void Mir2Lir::MarkPossibleNullPointerException(int opt_flags) { 82 if (!Runtime::Current()->ExplicitNullChecks()) { 83 if (!(cu_->disable_opt & (1 << kNullCheckElimination)) && (opt_flags & MIR_IGNORE_NULL_CHECK)) { 84 return; 85 } 86 MarkSafepointPC(last_lir_insn_); 87 } 88} 89 90void Mir2Lir::MarkPossibleStackOverflowException() { 91 if (!Runtime::Current()->ExplicitStackOverflowChecks()) { 92 MarkSafepointPC(last_lir_insn_); 93 } 94} 95 96void Mir2Lir::ForceImplicitNullCheck(int reg, int opt_flags) { 97 if (!Runtime::Current()->ExplicitNullChecks()) { 98 if (!(cu_->disable_opt & (1 << kNullCheckElimination)) && (opt_flags & MIR_IGNORE_NULL_CHECK)) { 99 return; 100 } 101 // Force an implicit null check by performing a memory operation (load) from the given 102 // register with offset 0. This will cause a signal if the register contains 0 (null). 103 int tmp = AllocTemp(); 104 LIR* load = LoadWordDisp(reg, 0, tmp); 105 FreeTemp(tmp); 106 MarkSafepointPC(load); 107 } 108} 109 110/* Perform check on two registers */ 111LIR* Mir2Lir::GenRegRegCheck(ConditionCode c_code, int reg1, int reg2, 112 ThrowKind kind) { 113 LIR* tgt = RawLIR(0, kPseudoThrowTarget, kind, current_dalvik_offset_, reg1, reg2); 114 LIR* branch = OpCmpBranch(c_code, reg1, reg2, tgt); 115 // Remember branch target - will process later 116 throw_launchpads_.Insert(tgt); 117 return branch; 118} 119 120void Mir2Lir::GenCompareAndBranch(Instruction::Code opcode, RegLocation rl_src1, 121 RegLocation rl_src2, LIR* taken, 122 LIR* fall_through) { 123 ConditionCode cond; 124 switch (opcode) { 125 case Instruction::IF_EQ: 126 cond = kCondEq; 127 break; 128 case Instruction::IF_NE: 129 cond = kCondNe; 130 break; 131 case Instruction::IF_LT: 132 cond = kCondLt; 133 break; 134 case Instruction::IF_GE: 135 cond = kCondGe; 136 break; 137 case Instruction::IF_GT: 138 cond = kCondGt; 139 break; 140 case Instruction::IF_LE: 141 cond = kCondLe; 142 break; 143 default: 144 cond = static_cast<ConditionCode>(0); 145 LOG(FATAL) << "Unexpected opcode " << opcode; 146 } 147 148 // Normalize such that if either operand is constant, src2 will be constant 149 if (rl_src1.is_const) { 150 RegLocation rl_temp = rl_src1; 151 rl_src1 = rl_src2; 152 rl_src2 = rl_temp; 153 cond = FlipComparisonOrder(cond); 154 } 155 156 rl_src1 = LoadValue(rl_src1, kCoreReg); 157 // Is this really an immediate comparison? 158 if (rl_src2.is_const) { 159 // If it's already live in a register or not easily materialized, just keep going 160 RegLocation rl_temp = UpdateLoc(rl_src2); 161 if ((rl_temp.location == kLocDalvikFrame) && 162 InexpensiveConstantInt(mir_graph_->ConstantValue(rl_src2))) { 163 // OK - convert this to a compare immediate and branch 164 OpCmpImmBranch(cond, rl_src1.reg.GetReg(), mir_graph_->ConstantValue(rl_src2), taken); 165 return; 166 } 167 } 168 rl_src2 = LoadValue(rl_src2, kCoreReg); 169 OpCmpBranch(cond, rl_src1.reg.GetReg(), rl_src2.reg.GetReg(), taken); 170} 171 172void Mir2Lir::GenCompareZeroAndBranch(Instruction::Code opcode, RegLocation rl_src, LIR* taken, 173 LIR* fall_through) { 174 ConditionCode cond; 175 rl_src = LoadValue(rl_src, kCoreReg); 176 switch (opcode) { 177 case Instruction::IF_EQZ: 178 cond = kCondEq; 179 break; 180 case Instruction::IF_NEZ: 181 cond = kCondNe; 182 break; 183 case Instruction::IF_LTZ: 184 cond = kCondLt; 185 break; 186 case Instruction::IF_GEZ: 187 cond = kCondGe; 188 break; 189 case Instruction::IF_GTZ: 190 cond = kCondGt; 191 break; 192 case Instruction::IF_LEZ: 193 cond = kCondLe; 194 break; 195 default: 196 cond = static_cast<ConditionCode>(0); 197 LOG(FATAL) << "Unexpected opcode " << opcode; 198 } 199 OpCmpImmBranch(cond, rl_src.reg.GetReg(), 0, taken); 200} 201 202void Mir2Lir::GenIntToLong(RegLocation rl_dest, RegLocation rl_src) { 203 RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); 204 if (rl_src.location == kLocPhysReg) { 205 OpRegCopy(rl_result.reg.GetReg(), rl_src.reg.GetReg()); 206 } else { 207 LoadValueDirect(rl_src, rl_result.reg.GetReg()); 208 } 209 OpRegRegImm(kOpAsr, rl_result.reg.GetHighReg(), rl_result.reg.GetReg(), 31); 210 StoreValueWide(rl_dest, rl_result); 211} 212 213void Mir2Lir::GenIntNarrowing(Instruction::Code opcode, RegLocation rl_dest, 214 RegLocation rl_src) { 215 rl_src = LoadValue(rl_src, kCoreReg); 216 RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); 217 OpKind op = kOpInvalid; 218 switch (opcode) { 219 case Instruction::INT_TO_BYTE: 220 op = kOp2Byte; 221 break; 222 case Instruction::INT_TO_SHORT: 223 op = kOp2Short; 224 break; 225 case Instruction::INT_TO_CHAR: 226 op = kOp2Char; 227 break; 228 default: 229 LOG(ERROR) << "Bad int conversion type"; 230 } 231 OpRegReg(op, rl_result.reg.GetReg(), rl_src.reg.GetReg()); 232 StoreValue(rl_dest, rl_result); 233} 234 235/* 236 * Let helper function take care of everything. Will call 237 * Array::AllocFromCode(type_idx, method, count); 238 * Note: AllocFromCode will handle checks for errNegativeArraySize. 239 */ 240void Mir2Lir::GenNewArray(uint32_t type_idx, RegLocation rl_dest, 241 RegLocation rl_src) { 242 FlushAllRegs(); /* Everything to home location */ 243 ThreadOffset func_offset(-1); 244 const DexFile* dex_file = cu_->dex_file; 245 CompilerDriver* driver = cu_->compiler_driver; 246 if (cu_->compiler_driver->CanAccessTypeWithoutChecks(cu_->method_idx, *dex_file, 247 type_idx)) { 248 bool is_type_initialized; // Ignored as an array does not have an initializer. 249 bool use_direct_type_ptr; 250 uintptr_t direct_type_ptr; 251 if (kEmbedClassInCode && 252 driver->CanEmbedTypeInCode(*dex_file, type_idx, 253 &is_type_initialized, &use_direct_type_ptr, &direct_type_ptr)) { 254 // The fast path. 255 if (!use_direct_type_ptr) { 256 LoadClassType(type_idx, kArg0); 257 func_offset = QUICK_ENTRYPOINT_OFFSET(pAllocArrayResolved); 258 CallRuntimeHelperRegMethodRegLocation(func_offset, TargetReg(kArg0), rl_src, true); 259 } else { 260 // Use the direct pointer. 261 func_offset = QUICK_ENTRYPOINT_OFFSET(pAllocArrayResolved); 262 CallRuntimeHelperImmMethodRegLocation(func_offset, direct_type_ptr, rl_src, true); 263 } 264 } else { 265 // The slow path. 266 DCHECK_EQ(func_offset.Int32Value(), -1); 267 func_offset = QUICK_ENTRYPOINT_OFFSET(pAllocArray); 268 CallRuntimeHelperImmMethodRegLocation(func_offset, type_idx, rl_src, true); 269 } 270 DCHECK_NE(func_offset.Int32Value(), -1); 271 } else { 272 func_offset= QUICK_ENTRYPOINT_OFFSET(pAllocArrayWithAccessCheck); 273 CallRuntimeHelperImmMethodRegLocation(func_offset, type_idx, rl_src, true); 274 } 275 RegLocation rl_result = GetReturn(false); 276 StoreValue(rl_dest, rl_result); 277} 278 279/* 280 * Similar to GenNewArray, but with post-allocation initialization. 281 * Verifier guarantees we're dealing with an array class. Current 282 * code throws runtime exception "bad Filled array req" for 'D' and 'J'. 283 * Current code also throws internal unimp if not 'L', '[' or 'I'. 284 */ 285void Mir2Lir::GenFilledNewArray(CallInfo* info) { 286 int elems = info->num_arg_words; 287 int type_idx = info->index; 288 FlushAllRegs(); /* Everything to home location */ 289 ThreadOffset func_offset(-1); 290 if (cu_->compiler_driver->CanAccessTypeWithoutChecks(cu_->method_idx, *cu_->dex_file, 291 type_idx)) { 292 func_offset = QUICK_ENTRYPOINT_OFFSET(pCheckAndAllocArray); 293 } else { 294 func_offset = QUICK_ENTRYPOINT_OFFSET(pCheckAndAllocArrayWithAccessCheck); 295 } 296 CallRuntimeHelperImmMethodImm(func_offset, type_idx, elems, true); 297 FreeTemp(TargetReg(kArg2)); 298 FreeTemp(TargetReg(kArg1)); 299 /* 300 * NOTE: the implicit target for Instruction::FILLED_NEW_ARRAY is the 301 * return region. Because AllocFromCode placed the new array 302 * in kRet0, we'll just lock it into place. When debugger support is 303 * added, it may be necessary to additionally copy all return 304 * values to a home location in thread-local storage 305 */ 306 LockTemp(TargetReg(kRet0)); 307 308 // TODO: use the correct component size, currently all supported types 309 // share array alignment with ints (see comment at head of function) 310 size_t component_size = sizeof(int32_t); 311 312 // Having a range of 0 is legal 313 if (info->is_range && (elems > 0)) { 314 /* 315 * Bit of ugliness here. We're going generate a mem copy loop 316 * on the register range, but it is possible that some regs 317 * in the range have been promoted. This is unlikely, but 318 * before generating the copy, we'll just force a flush 319 * of any regs in the source range that have been promoted to 320 * home location. 321 */ 322 for (int i = 0; i < elems; i++) { 323 RegLocation loc = UpdateLoc(info->args[i]); 324 if (loc.location == kLocPhysReg) { 325 StoreBaseDisp(TargetReg(kSp), SRegOffset(loc.s_reg_low), 326 loc.reg.GetReg(), kWord); 327 } 328 } 329 /* 330 * TUNING note: generated code here could be much improved, but 331 * this is an uncommon operation and isn't especially performance 332 * critical. 333 */ 334 int r_src = AllocTemp(); 335 int r_dst = AllocTemp(); 336 int r_idx = AllocTemp(); 337 int r_val = INVALID_REG; 338 switch (cu_->instruction_set) { 339 case kThumb2: 340 r_val = TargetReg(kLr); 341 break; 342 case kX86: 343 FreeTemp(TargetReg(kRet0)); 344 r_val = AllocTemp(); 345 break; 346 case kMips: 347 r_val = AllocTemp(); 348 break; 349 default: LOG(FATAL) << "Unexpected instruction set: " << cu_->instruction_set; 350 } 351 // Set up source pointer 352 RegLocation rl_first = info->args[0]; 353 OpRegRegImm(kOpAdd, r_src, TargetReg(kSp), SRegOffset(rl_first.s_reg_low)); 354 // Set up the target pointer 355 OpRegRegImm(kOpAdd, r_dst, TargetReg(kRet0), 356 mirror::Array::DataOffset(component_size).Int32Value()); 357 // Set up the loop counter (known to be > 0) 358 LoadConstant(r_idx, elems - 1); 359 // Generate the copy loop. Going backwards for convenience 360 LIR* target = NewLIR0(kPseudoTargetLabel); 361 // Copy next element 362 LoadBaseIndexed(r_src, r_idx, r_val, 2, kWord); 363 StoreBaseIndexed(r_dst, r_idx, r_val, 2, kWord); 364 FreeTemp(r_val); 365 OpDecAndBranch(kCondGe, r_idx, target); 366 if (cu_->instruction_set == kX86) { 367 // Restore the target pointer 368 OpRegRegImm(kOpAdd, TargetReg(kRet0), r_dst, 369 -mirror::Array::DataOffset(component_size).Int32Value()); 370 } 371 } else if (!info->is_range) { 372 // TUNING: interleave 373 for (int i = 0; i < elems; i++) { 374 RegLocation rl_arg = LoadValue(info->args[i], kCoreReg); 375 StoreBaseDisp(TargetReg(kRet0), 376 mirror::Array::DataOffset(component_size).Int32Value() + 377 i * 4, rl_arg.reg.GetReg(), kWord); 378 // If the LoadValue caused a temp to be allocated, free it 379 if (IsTemp(rl_arg.reg.GetReg())) { 380 FreeTemp(rl_arg.reg.GetReg()); 381 } 382 } 383 } 384 if (info->result.location != kLocInvalid) { 385 StoreValue(info->result, GetReturn(false /* not fp */)); 386 } 387} 388 389// 390// Slow path to ensure a class is initialized for sget/sput. 391// 392class StaticFieldSlowPath : public Mir2Lir::LIRSlowPath { 393 public: 394 StaticFieldSlowPath(Mir2Lir* m2l, LIR* unresolved, LIR* uninit, LIR* cont, 395 int storage_index, int r_base) : 396 LIRSlowPath(m2l, m2l->GetCurrentDexPc(), unresolved, cont), uninit_(uninit), storage_index_(storage_index), 397 r_base_(r_base) { 398 } 399 400 void Compile() { 401 LIR* unresolved_target = GenerateTargetLabel(); 402 uninit_->target = unresolved_target; 403 m2l_->CallRuntimeHelperImm(QUICK_ENTRYPOINT_OFFSET(pInitializeStaticStorage), 404 storage_index_, true); 405 // Copy helper's result into r_base, a no-op on all but MIPS. 406 m2l_->OpRegCopy(r_base_, m2l_->TargetReg(kRet0)); 407 408 m2l_->OpUnconditionalBranch(cont_); 409 } 410 411 private: 412 LIR* const uninit_; 413 const int storage_index_; 414 const int r_base_; 415}; 416 417void Mir2Lir::GenSput(MIR* mir, RegLocation rl_src, bool is_long_or_double, 418 bool is_object) { 419 const MirSFieldLoweringInfo& field_info = mir_graph_->GetSFieldLoweringInfo(mir); 420 cu_->compiler_driver->ProcessedStaticField(field_info.FastPut(), field_info.IsReferrersClass()); 421 if (field_info.FastPut() && !SLOW_FIELD_PATH) { 422 DCHECK_GE(field_info.FieldOffset().Int32Value(), 0); 423 int r_base; 424 if (field_info.IsReferrersClass()) { 425 // Fast path, static storage base is this method's class 426 RegLocation rl_method = LoadCurrMethod(); 427 r_base = AllocTemp(); 428 LoadWordDisp(rl_method.reg.GetReg(), 429 mirror::ArtMethod::DeclaringClassOffset().Int32Value(), r_base); 430 if (IsTemp(rl_method.reg.GetReg())) { 431 FreeTemp(rl_method.reg.GetReg()); 432 } 433 } else { 434 // Medium path, static storage base in a different class which requires checks that the other 435 // class is initialized. 436 // TODO: remove initialized check now that we are initializing classes in the compiler driver. 437 DCHECK_NE(field_info.StorageIndex(), DexFile::kDexNoIndex); 438 // May do runtime call so everything to home locations. 439 FlushAllRegs(); 440 // Using fixed register to sync with possible call to runtime support. 441 int r_method = TargetReg(kArg1); 442 LockTemp(r_method); 443 LoadCurrMethodDirect(r_method); 444 r_base = TargetReg(kArg0); 445 LockTemp(r_base); 446 LoadWordDisp(r_method, 447 mirror::ArtMethod::DexCacheResolvedTypesOffset().Int32Value(), 448 r_base); 449 LoadWordDisp(r_base, mirror::Array::DataOffset(sizeof(mirror::Object*)).Int32Value() + 450 sizeof(int32_t*) * field_info.StorageIndex(), r_base); 451 // r_base now points at static storage (Class*) or NULL if the type is not yet resolved. 452 if (!field_info.IsInitialized() && 453 (mir->optimization_flags & MIR_IGNORE_CLINIT_CHECK) == 0) { 454 // Check if r_base is NULL or a not yet initialized class. 455 456 // The slow path is invoked if the r_base is NULL or the class pointed 457 // to by it is not initialized. 458 LIR* unresolved_branch = OpCmpImmBranch(kCondEq, r_base, 0, NULL); 459 int r_tmp = TargetReg(kArg2); 460 LockTemp(r_tmp); 461 LIR* uninit_branch = OpCmpMemImmBranch(kCondLt, r_tmp, r_base, 462 mirror::Class::StatusOffset().Int32Value(), 463 mirror::Class::kStatusInitialized, NULL); 464 LIR* cont = NewLIR0(kPseudoTargetLabel); 465 466 AddSlowPath(new (arena_) StaticFieldSlowPath(this, 467 unresolved_branch, uninit_branch, cont, 468 field_info.StorageIndex(), r_base)); 469 470 FreeTemp(r_tmp); 471 } 472 FreeTemp(r_method); 473 } 474 // rBase now holds static storage base 475 if (is_long_or_double) { 476 rl_src = LoadValueWide(rl_src, kAnyReg); 477 } else { 478 rl_src = LoadValue(rl_src, kAnyReg); 479 } 480 if (field_info.IsVolatile()) { 481 GenMemBarrier(kStoreStore); 482 } 483 if (is_long_or_double) { 484 StoreBaseDispWide(r_base, field_info.FieldOffset().Int32Value(), rl_src.reg.GetReg(), 485 rl_src.reg.GetHighReg()); 486 } else { 487 StoreWordDisp(r_base, field_info.FieldOffset().Int32Value(), rl_src.reg.GetReg()); 488 } 489 if (field_info.IsVolatile()) { 490 GenMemBarrier(kStoreLoad); 491 } 492 if (is_object && !mir_graph_->IsConstantNullRef(rl_src)) { 493 MarkGCCard(rl_src.reg.GetReg(), r_base); 494 } 495 FreeTemp(r_base); 496 } else { 497 FlushAllRegs(); // Everything to home locations 498 ThreadOffset setter_offset = 499 is_long_or_double ? QUICK_ENTRYPOINT_OFFSET(pSet64Static) 500 : (is_object ? QUICK_ENTRYPOINT_OFFSET(pSetObjStatic) 501 : QUICK_ENTRYPOINT_OFFSET(pSet32Static)); 502 CallRuntimeHelperImmRegLocation(setter_offset, field_info.FieldIndex(), rl_src, true); 503 } 504} 505 506void Mir2Lir::GenSget(MIR* mir, RegLocation rl_dest, 507 bool is_long_or_double, bool is_object) { 508 const MirSFieldLoweringInfo& field_info = mir_graph_->GetSFieldLoweringInfo(mir); 509 cu_->compiler_driver->ProcessedStaticField(field_info.FastGet(), field_info.IsReferrersClass()); 510 if (field_info.FastGet() && !SLOW_FIELD_PATH) { 511 DCHECK_GE(field_info.FieldOffset().Int32Value(), 0); 512 int r_base; 513 if (field_info.IsReferrersClass()) { 514 // Fast path, static storage base is this method's class 515 RegLocation rl_method = LoadCurrMethod(); 516 r_base = AllocTemp(); 517 LoadWordDisp(rl_method.reg.GetReg(), 518 mirror::ArtMethod::DeclaringClassOffset().Int32Value(), r_base); 519 } else { 520 // Medium path, static storage base in a different class which requires checks that the other 521 // class is initialized 522 DCHECK_NE(field_info.StorageIndex(), DexFile::kDexNoIndex); 523 // May do runtime call so everything to home locations. 524 FlushAllRegs(); 525 // Using fixed register to sync with possible call to runtime support. 526 int r_method = TargetReg(kArg1); 527 LockTemp(r_method); 528 LoadCurrMethodDirect(r_method); 529 r_base = TargetReg(kArg0); 530 LockTemp(r_base); 531 LoadWordDisp(r_method, 532 mirror::ArtMethod::DexCacheResolvedTypesOffset().Int32Value(), 533 r_base); 534 LoadWordDisp(r_base, mirror::Array::DataOffset(sizeof(mirror::Object*)).Int32Value() + 535 sizeof(int32_t*) * field_info.StorageIndex(), r_base); 536 // r_base now points at static storage (Class*) or NULL if the type is not yet resolved. 537 if (!field_info.IsInitialized() && 538 (mir->optimization_flags & MIR_IGNORE_CLINIT_CHECK) == 0) { 539 // Check if r_base is NULL or a not yet initialized class. 540 541 // The slow path is invoked if the r_base is NULL or the class pointed 542 // to by it is not initialized. 543 LIR* unresolved_branch = OpCmpImmBranch(kCondEq, r_base, 0, NULL); 544 int r_tmp = TargetReg(kArg2); 545 LockTemp(r_tmp); 546 LIR* uninit_branch = OpCmpMemImmBranch(kCondLt, r_tmp, r_base, 547 mirror::Class::StatusOffset().Int32Value(), 548 mirror::Class::kStatusInitialized, NULL); 549 LIR* cont = NewLIR0(kPseudoTargetLabel); 550 551 AddSlowPath(new (arena_) StaticFieldSlowPath(this, 552 unresolved_branch, uninit_branch, cont, 553 field_info.StorageIndex(), r_base)); 554 555 FreeTemp(r_tmp); 556 } 557 FreeTemp(r_method); 558 } 559 // r_base now holds static storage base 560 RegLocation rl_result = EvalLoc(rl_dest, kAnyReg, true); 561 if (field_info.IsVolatile()) { 562 GenMemBarrier(kLoadLoad); 563 } 564 if (is_long_or_double) { 565 LoadBaseDispWide(r_base, field_info.FieldOffset().Int32Value(), rl_result.reg.GetReg(), 566 rl_result.reg.GetHighReg(), INVALID_SREG); 567 } else { 568 LoadWordDisp(r_base, field_info.FieldOffset().Int32Value(), rl_result.reg.GetReg()); 569 } 570 FreeTemp(r_base); 571 if (is_long_or_double) { 572 StoreValueWide(rl_dest, rl_result); 573 } else { 574 StoreValue(rl_dest, rl_result); 575 } 576 } else { 577 FlushAllRegs(); // Everything to home locations 578 ThreadOffset getterOffset = 579 is_long_or_double ? QUICK_ENTRYPOINT_OFFSET(pGet64Static) 580 :(is_object ? QUICK_ENTRYPOINT_OFFSET(pGetObjStatic) 581 : QUICK_ENTRYPOINT_OFFSET(pGet32Static)); 582 CallRuntimeHelperImm(getterOffset, field_info.FieldIndex(), true); 583 if (is_long_or_double) { 584 RegLocation rl_result = GetReturnWide(rl_dest.fp); 585 StoreValueWide(rl_dest, rl_result); 586 } else { 587 RegLocation rl_result = GetReturn(rl_dest.fp); 588 StoreValue(rl_dest, rl_result); 589 } 590 } 591} 592 593// Generate code for all slow paths. 594void Mir2Lir::HandleSlowPaths() { 595 int n = slow_paths_.Size(); 596 for (int i = 0; i < n; ++i) { 597 LIRSlowPath* slowpath = slow_paths_.Get(i); 598 slowpath->Compile(); 599 } 600 slow_paths_.Reset(); 601} 602 603void Mir2Lir::HandleSuspendLaunchPads() { 604 int num_elems = suspend_launchpads_.Size(); 605 ThreadOffset helper_offset = QUICK_ENTRYPOINT_OFFSET(pTestSuspend); 606 for (int i = 0; i < num_elems; i++) { 607 ResetRegPool(); 608 ResetDefTracking(); 609 LIR* lab = suspend_launchpads_.Get(i); 610 LIR* resume_lab = reinterpret_cast<LIR*>(UnwrapPointer(lab->operands[0])); 611 current_dalvik_offset_ = lab->operands[1]; 612 AppendLIR(lab); 613 int r_tgt = CallHelperSetup(helper_offset); 614 CallHelper(r_tgt, helper_offset, true /* MarkSafepointPC */); 615 OpUnconditionalBranch(resume_lab); 616 } 617} 618 619void Mir2Lir::HandleThrowLaunchPads() { 620 int num_elems = throw_launchpads_.Size(); 621 for (int i = 0; i < num_elems; i++) { 622 ResetRegPool(); 623 ResetDefTracking(); 624 LIR* lab = throw_launchpads_.Get(i); 625 current_dalvik_offset_ = lab->operands[1]; 626 AppendLIR(lab); 627 ThreadOffset func_offset(-1); 628 int v1 = lab->operands[2]; 629 int v2 = lab->operands[3]; 630 bool target_x86 = (cu_->instruction_set == kX86); 631 switch (lab->operands[0]) { 632 case kThrowNullPointer: 633 func_offset = QUICK_ENTRYPOINT_OFFSET(pThrowNullPointer); 634 break; 635 case kThrowConstantArrayBounds: // v1 is length reg (for Arm/Mips), v2 constant index 636 // v1 holds the constant array index. Mips/Arm uses v2 for length, x86 reloads. 637 if (target_x86) { 638 OpRegMem(kOpMov, TargetReg(kArg1), v1, mirror::Array::LengthOffset().Int32Value()); 639 } else { 640 OpRegCopy(TargetReg(kArg1), v1); 641 } 642 // Make sure the following LoadConstant doesn't mess with kArg1. 643 LockTemp(TargetReg(kArg1)); 644 LoadConstant(TargetReg(kArg0), v2); 645 func_offset = QUICK_ENTRYPOINT_OFFSET(pThrowArrayBounds); 646 break; 647 case kThrowArrayBounds: 648 // Move v1 (array index) to kArg0 and v2 (array length) to kArg1 649 if (v2 != TargetReg(kArg0)) { 650 OpRegCopy(TargetReg(kArg0), v1); 651 if (target_x86) { 652 // x86 leaves the array pointer in v2, so load the array length that the handler expects 653 OpRegMem(kOpMov, TargetReg(kArg1), v2, mirror::Array::LengthOffset().Int32Value()); 654 } else { 655 OpRegCopy(TargetReg(kArg1), v2); 656 } 657 } else { 658 if (v1 == TargetReg(kArg1)) { 659 // Swap v1 and v2, using kArg2 as a temp 660 OpRegCopy(TargetReg(kArg2), v1); 661 if (target_x86) { 662 // x86 leaves the array pointer in v2; load the array length that the handler expects 663 OpRegMem(kOpMov, TargetReg(kArg1), v2, mirror::Array::LengthOffset().Int32Value()); 664 } else { 665 OpRegCopy(TargetReg(kArg1), v2); 666 } 667 OpRegCopy(TargetReg(kArg0), TargetReg(kArg2)); 668 } else { 669 if (target_x86) { 670 // x86 leaves the array pointer in v2; load the array length that the handler expects 671 OpRegMem(kOpMov, TargetReg(kArg1), v2, mirror::Array::LengthOffset().Int32Value()); 672 } else { 673 OpRegCopy(TargetReg(kArg1), v2); 674 } 675 OpRegCopy(TargetReg(kArg0), v1); 676 } 677 } 678 func_offset = QUICK_ENTRYPOINT_OFFSET(pThrowArrayBounds); 679 break; 680 case kThrowDivZero: 681 func_offset = QUICK_ENTRYPOINT_OFFSET(pThrowDivZero); 682 break; 683 case kThrowNoSuchMethod: 684 OpRegCopy(TargetReg(kArg0), v1); 685 func_offset = 686 QUICK_ENTRYPOINT_OFFSET(pThrowNoSuchMethod); 687 break; 688 case kThrowStackOverflow: 689 func_offset = QUICK_ENTRYPOINT_OFFSET(pThrowStackOverflow); 690 // Restore stack alignment 691 if (target_x86) { 692 OpRegImm(kOpAdd, TargetReg(kSp), frame_size_); 693 } else { 694 OpRegImm(kOpAdd, TargetReg(kSp), (num_core_spills_ + num_fp_spills_) * 4); 695 } 696 break; 697 default: 698 LOG(FATAL) << "Unexpected throw kind: " << lab->operands[0]; 699 } 700 ClobberCallerSave(); 701 int r_tgt = CallHelperSetup(func_offset); 702 CallHelper(r_tgt, func_offset, true /* MarkSafepointPC */); 703 } 704} 705 706void Mir2Lir::GenIGet(MIR* mir, int opt_flags, OpSize size, 707 RegLocation rl_dest, RegLocation rl_obj, bool is_long_or_double, 708 bool is_object) { 709 const MirIFieldLoweringInfo& field_info = mir_graph_->GetIFieldLoweringInfo(mir); 710 cu_->compiler_driver->ProcessedInstanceField(field_info.FastGet()); 711 if (field_info.FastGet() && !SLOW_FIELD_PATH) { 712 RegLocation rl_result; 713 RegisterClass reg_class = oat_reg_class_by_size(size); 714 DCHECK_GE(field_info.FieldOffset().Int32Value(), 0); 715 rl_obj = LoadValue(rl_obj, kCoreReg); 716 if (is_long_or_double) { 717 DCHECK(rl_dest.wide); 718 GenNullCheck(rl_obj.reg.GetReg(), opt_flags); 719 if (cu_->instruction_set == kX86) { 720 rl_result = EvalLoc(rl_dest, reg_class, true); 721 GenNullCheck(rl_obj.reg.GetReg(), opt_flags); 722 LoadBaseDispWide(rl_obj.reg.GetReg(), field_info.FieldOffset().Int32Value(), 723 rl_result.reg.GetReg(), 724 rl_result.reg.GetHighReg(), rl_obj.s_reg_low); 725 MarkPossibleNullPointerException(opt_flags); 726 if (field_info.IsVolatile()) { 727 GenMemBarrier(kLoadLoad); 728 } 729 } else { 730 int reg_ptr = AllocTemp(); 731 OpRegRegImm(kOpAdd, reg_ptr, rl_obj.reg.GetReg(), field_info.FieldOffset().Int32Value()); 732 rl_result = EvalLoc(rl_dest, reg_class, true); 733 LoadBaseDispWide(reg_ptr, 0, rl_result.reg.GetReg(), rl_result.reg.GetHighReg(), 734 INVALID_SREG); 735 if (field_info.IsVolatile()) { 736 GenMemBarrier(kLoadLoad); 737 } 738 FreeTemp(reg_ptr); 739 } 740 StoreValueWide(rl_dest, rl_result); 741 } else { 742 rl_result = EvalLoc(rl_dest, reg_class, true); 743 GenNullCheck(rl_obj.reg.GetReg(), opt_flags); 744 LoadBaseDisp(rl_obj.reg.GetReg(), field_info.FieldOffset().Int32Value(), 745 rl_result.reg.GetReg(), kWord, rl_obj.s_reg_low); 746 MarkPossibleNullPointerException(opt_flags); 747 if (field_info.IsVolatile()) { 748 GenMemBarrier(kLoadLoad); 749 } 750 StoreValue(rl_dest, rl_result); 751 } 752 } else { 753 ThreadOffset getterOffset = 754 is_long_or_double ? QUICK_ENTRYPOINT_OFFSET(pGet64Instance) 755 : (is_object ? QUICK_ENTRYPOINT_OFFSET(pGetObjInstance) 756 : QUICK_ENTRYPOINT_OFFSET(pGet32Instance)); 757 CallRuntimeHelperImmRegLocation(getterOffset, field_info.FieldIndex(), rl_obj, true); 758 if (is_long_or_double) { 759 RegLocation rl_result = GetReturnWide(rl_dest.fp); 760 StoreValueWide(rl_dest, rl_result); 761 } else { 762 RegLocation rl_result = GetReturn(rl_dest.fp); 763 StoreValue(rl_dest, rl_result); 764 } 765 } 766} 767 768void Mir2Lir::GenIPut(MIR* mir, int opt_flags, OpSize size, 769 RegLocation rl_src, RegLocation rl_obj, bool is_long_or_double, 770 bool is_object) { 771 const MirIFieldLoweringInfo& field_info = mir_graph_->GetIFieldLoweringInfo(mir); 772 cu_->compiler_driver->ProcessedInstanceField(field_info.FastPut()); 773 if (field_info.FastPut() && !SLOW_FIELD_PATH) { 774 RegisterClass reg_class = oat_reg_class_by_size(size); 775 DCHECK_GE(field_info.FieldOffset().Int32Value(), 0); 776 rl_obj = LoadValue(rl_obj, kCoreReg); 777 if (is_long_or_double) { 778 int reg_ptr; 779 rl_src = LoadValueWide(rl_src, kAnyReg); 780 GenNullCheck(rl_obj.reg.GetReg(), opt_flags); 781 reg_ptr = AllocTemp(); 782 OpRegRegImm(kOpAdd, reg_ptr, rl_obj.reg.GetReg(), field_info.FieldOffset().Int32Value()); 783 if (field_info.IsVolatile()) { 784 GenMemBarrier(kStoreStore); 785 } 786 StoreBaseDispWide(reg_ptr, 0, rl_src.reg.GetReg(), rl_src.reg.GetHighReg()); 787 MarkPossibleNullPointerException(opt_flags); 788 if (field_info.IsVolatile()) { 789 GenMemBarrier(kLoadLoad); 790 } 791 FreeTemp(reg_ptr); 792 } else { 793 rl_src = LoadValue(rl_src, reg_class); 794 GenNullCheck(rl_obj.reg.GetReg(), opt_flags); 795 if (field_info.IsVolatile()) { 796 GenMemBarrier(kStoreStore); 797 } 798 StoreBaseDisp(rl_obj.reg.GetReg(), field_info.FieldOffset().Int32Value(), 799 rl_src.reg.GetReg(), kWord); 800 MarkPossibleNullPointerException(opt_flags); 801 if (field_info.IsVolatile()) { 802 GenMemBarrier(kLoadLoad); 803 } 804 if (is_object && !mir_graph_->IsConstantNullRef(rl_src)) { 805 MarkGCCard(rl_src.reg.GetReg(), rl_obj.reg.GetReg()); 806 } 807 } 808 } else { 809 ThreadOffset setter_offset = 810 is_long_or_double ? QUICK_ENTRYPOINT_OFFSET(pSet64Instance) 811 : (is_object ? QUICK_ENTRYPOINT_OFFSET(pSetObjInstance) 812 : QUICK_ENTRYPOINT_OFFSET(pSet32Instance)); 813 CallRuntimeHelperImmRegLocationRegLocation(setter_offset, field_info.FieldIndex(), 814 rl_obj, rl_src, true); 815 } 816} 817 818void Mir2Lir::GenArrayObjPut(int opt_flags, RegLocation rl_array, RegLocation rl_index, 819 RegLocation rl_src) { 820 bool needs_range_check = !(opt_flags & MIR_IGNORE_RANGE_CHECK); 821 bool needs_null_check = !((cu_->disable_opt & (1 << kNullCheckElimination)) && 822 (opt_flags & MIR_IGNORE_NULL_CHECK)); 823 ThreadOffset helper = needs_range_check 824 ? (needs_null_check ? QUICK_ENTRYPOINT_OFFSET(pAputObjectWithNullAndBoundCheck) 825 : QUICK_ENTRYPOINT_OFFSET(pAputObjectWithBoundCheck)) 826 : QUICK_ENTRYPOINT_OFFSET(pAputObject); 827 CallRuntimeHelperRegLocationRegLocationRegLocation(helper, rl_array, rl_index, rl_src, true); 828} 829 830void Mir2Lir::GenConstClass(uint32_t type_idx, RegLocation rl_dest) { 831 RegLocation rl_method = LoadCurrMethod(); 832 int res_reg = AllocTemp(); 833 RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); 834 if (!cu_->compiler_driver->CanAccessTypeWithoutChecks(cu_->method_idx, 835 *cu_->dex_file, 836 type_idx)) { 837 // Call out to helper which resolves type and verifies access. 838 // Resolved type returned in kRet0. 839 CallRuntimeHelperImmReg(QUICK_ENTRYPOINT_OFFSET(pInitializeTypeAndVerifyAccess), 840 type_idx, rl_method.reg.GetReg(), true); 841 RegLocation rl_result = GetReturn(false); 842 StoreValue(rl_dest, rl_result); 843 } else { 844 // We're don't need access checks, load type from dex cache 845 int32_t dex_cache_offset = 846 mirror::ArtMethod::DexCacheResolvedTypesOffset().Int32Value(); 847 LoadWordDisp(rl_method.reg.GetReg(), dex_cache_offset, res_reg); 848 int32_t offset_of_type = 849 mirror::Array::DataOffset(sizeof(mirror::Class*)).Int32Value() + (sizeof(mirror::Class*) 850 * type_idx); 851 LoadWordDisp(res_reg, offset_of_type, rl_result.reg.GetReg()); 852 if (!cu_->compiler_driver->CanAssumeTypeIsPresentInDexCache(*cu_->dex_file, 853 type_idx) || SLOW_TYPE_PATH) { 854 // Slow path, at runtime test if type is null and if so initialize 855 FlushAllRegs(); 856 LIR* branch = OpCmpImmBranch(kCondEq, rl_result.reg.GetReg(), 0, NULL); 857 LIR* cont = NewLIR0(kPseudoTargetLabel); 858 859 // Object to generate the slow path for class resolution. 860 class SlowPath : public LIRSlowPath { 861 public: 862 SlowPath(Mir2Lir* m2l, LIR* fromfast, LIR* cont, const int type_idx, 863 const RegLocation& rl_method, const RegLocation& rl_result) : 864 LIRSlowPath(m2l, m2l->GetCurrentDexPc(), fromfast, cont), type_idx_(type_idx), 865 rl_method_(rl_method), rl_result_(rl_result) { 866 } 867 868 void Compile() { 869 GenerateTargetLabel(); 870 871 m2l_->CallRuntimeHelperImmReg(QUICK_ENTRYPOINT_OFFSET(pInitializeType), type_idx_, 872 rl_method_.reg.GetReg(), true); 873 m2l_->OpRegCopy(rl_result_.reg.GetReg(), m2l_->TargetReg(kRet0)); 874 875 m2l_->OpUnconditionalBranch(cont_); 876 } 877 878 private: 879 const int type_idx_; 880 const RegLocation rl_method_; 881 const RegLocation rl_result_; 882 }; 883 884 // Add to list for future. 885 AddSlowPath(new (arena_) SlowPath(this, branch, cont, 886 type_idx, rl_method, rl_result)); 887 888 StoreValue(rl_dest, rl_result); 889 } else { 890 // Fast path, we're done - just store result 891 StoreValue(rl_dest, rl_result); 892 } 893 } 894} 895 896void Mir2Lir::GenConstString(uint32_t string_idx, RegLocation rl_dest) { 897 /* NOTE: Most strings should be available at compile time */ 898 int32_t offset_of_string = mirror::Array::DataOffset(sizeof(mirror::String*)).Int32Value() + 899 (sizeof(mirror::String*) * string_idx); 900 if (!cu_->compiler_driver->CanAssumeStringIsPresentInDexCache( 901 *cu_->dex_file, string_idx) || SLOW_STRING_PATH) { 902 // slow path, resolve string if not in dex cache 903 FlushAllRegs(); 904 LockCallTemps(); // Using explicit registers 905 906 // If the Method* is already in a register, we can save a copy. 907 RegLocation rl_method = mir_graph_->GetMethodLoc(); 908 int r_method; 909 if (rl_method.location == kLocPhysReg) { 910 // A temp would conflict with register use below. 911 DCHECK(!IsTemp(rl_method.reg.GetReg())); 912 r_method = rl_method.reg.GetReg(); 913 } else { 914 r_method = TargetReg(kArg2); 915 LoadCurrMethodDirect(r_method); 916 } 917 LoadWordDisp(r_method, mirror::ArtMethod::DexCacheStringsOffset().Int32Value(), 918 TargetReg(kArg0)); 919 920 // Might call out to helper, which will return resolved string in kRet0 921 LoadWordDisp(TargetReg(kArg0), offset_of_string, TargetReg(kRet0)); 922 if (cu_->instruction_set == kThumb2 || 923 cu_->instruction_set == kMips) { 924 // OpRegImm(kOpCmp, TargetReg(kRet0), 0); // Is resolved? 925 LoadConstant(TargetReg(kArg1), string_idx); 926 LIR* fromfast = OpCmpImmBranch(kCondEq, TargetReg(kRet0), 0, NULL); 927 LIR* cont = NewLIR0(kPseudoTargetLabel); 928 GenBarrier(); 929 930 // Object to generate the slow path for string resolution. 931 class SlowPath : public LIRSlowPath { 932 public: 933 SlowPath(Mir2Lir* m2l, LIR* fromfast, LIR* cont, int r_method) : 934 LIRSlowPath(m2l, m2l->GetCurrentDexPc(), fromfast, cont), r_method_(r_method) { 935 } 936 937 void Compile() { 938 GenerateTargetLabel(); 939 940 int r_tgt = m2l_->CallHelperSetup(QUICK_ENTRYPOINT_OFFSET(pResolveString)); 941 942 m2l_->OpRegCopy(m2l_->TargetReg(kArg0), r_method_); // .eq 943 LIR* call_inst = m2l_->OpReg(kOpBlx, r_tgt); 944 m2l_->MarkSafepointPC(call_inst); 945 m2l_->FreeTemp(r_tgt); 946 947 m2l_->OpUnconditionalBranch(cont_); 948 } 949 950 private: 951 int r_method_; 952 }; 953 954 // Add to list for future. 955 AddSlowPath(new (arena_) SlowPath(this, fromfast, cont, r_method)); 956 } else { 957 DCHECK_EQ(cu_->instruction_set, kX86); 958 LIR* branch = OpCmpImmBranch(kCondNe, TargetReg(kRet0), 0, NULL); 959 LoadConstant(TargetReg(kArg1), string_idx); 960 CallRuntimeHelperRegReg(QUICK_ENTRYPOINT_OFFSET(pResolveString), r_method, 961 TargetReg(kArg1), true); 962 LIR* target = NewLIR0(kPseudoTargetLabel); 963 branch->target = target; 964 } 965 GenBarrier(); 966 StoreValue(rl_dest, GetReturn(false)); 967 } else { 968 RegLocation rl_method = LoadCurrMethod(); 969 int res_reg = AllocTemp(); 970 RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); 971 LoadWordDisp(rl_method.reg.GetReg(), 972 mirror::ArtMethod::DexCacheStringsOffset().Int32Value(), res_reg); 973 LoadWordDisp(res_reg, offset_of_string, rl_result.reg.GetReg()); 974 StoreValue(rl_dest, rl_result); 975 } 976} 977 978/* 979 * Let helper function take care of everything. Will 980 * call Class::NewInstanceFromCode(type_idx, method); 981 */ 982void Mir2Lir::GenNewInstance(uint32_t type_idx, RegLocation rl_dest) { 983 FlushAllRegs(); /* Everything to home location */ 984 // alloc will always check for resolution, do we also need to verify 985 // access because the verifier was unable to? 986 ThreadOffset func_offset(-1); 987 const DexFile* dex_file = cu_->dex_file; 988 CompilerDriver* driver = cu_->compiler_driver; 989 if (driver->CanAccessInstantiableTypeWithoutChecks( 990 cu_->method_idx, *dex_file, type_idx)) { 991 bool is_type_initialized; 992 bool use_direct_type_ptr; 993 uintptr_t direct_type_ptr; 994 if (kEmbedClassInCode && 995 driver->CanEmbedTypeInCode(*dex_file, type_idx, 996 &is_type_initialized, &use_direct_type_ptr, &direct_type_ptr)) { 997 // The fast path. 998 if (!use_direct_type_ptr) { 999 LoadClassType(type_idx, kArg0); 1000 if (!is_type_initialized) { 1001 func_offset = QUICK_ENTRYPOINT_OFFSET(pAllocObjectResolved); 1002 CallRuntimeHelperRegMethod(func_offset, TargetReg(kArg0), true); 1003 } else { 1004 func_offset = QUICK_ENTRYPOINT_OFFSET(pAllocObjectInitialized); 1005 CallRuntimeHelperRegMethod(func_offset, TargetReg(kArg0), true); 1006 } 1007 } else { 1008 // Use the direct pointer. 1009 if (!is_type_initialized) { 1010 func_offset = QUICK_ENTRYPOINT_OFFSET(pAllocObjectResolved); 1011 CallRuntimeHelperImmMethod(func_offset, direct_type_ptr, true); 1012 } else { 1013 func_offset = QUICK_ENTRYPOINT_OFFSET(pAllocObjectInitialized); 1014 CallRuntimeHelperImmMethod(func_offset, direct_type_ptr, true); 1015 } 1016 } 1017 } else { 1018 // The slow path. 1019 DCHECK_EQ(func_offset.Int32Value(), -1); 1020 func_offset = QUICK_ENTRYPOINT_OFFSET(pAllocObject); 1021 CallRuntimeHelperImmMethod(func_offset, type_idx, true); 1022 } 1023 DCHECK_NE(func_offset.Int32Value(), -1); 1024 } else { 1025 func_offset = QUICK_ENTRYPOINT_OFFSET(pAllocObjectWithAccessCheck); 1026 CallRuntimeHelperImmMethod(func_offset, type_idx, true); 1027 } 1028 RegLocation rl_result = GetReturn(false); 1029 StoreValue(rl_dest, rl_result); 1030} 1031 1032void Mir2Lir::GenThrow(RegLocation rl_src) { 1033 FlushAllRegs(); 1034 CallRuntimeHelperRegLocation(QUICK_ENTRYPOINT_OFFSET(pDeliverException), rl_src, true); 1035} 1036 1037// For final classes there are no sub-classes to check and so we can answer the instance-of 1038// question with simple comparisons. 1039void Mir2Lir::GenInstanceofFinal(bool use_declaring_class, uint32_t type_idx, RegLocation rl_dest, 1040 RegLocation rl_src) { 1041 // X86 has its own implementation. 1042 DCHECK_NE(cu_->instruction_set, kX86); 1043 1044 RegLocation object = LoadValue(rl_src, kCoreReg); 1045 RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); 1046 int result_reg = rl_result.reg.GetReg(); 1047 if (result_reg == object.reg.GetReg()) { 1048 result_reg = AllocTypedTemp(false, kCoreReg); 1049 } 1050 LoadConstant(result_reg, 0); // assume false 1051 LIR* null_branchover = OpCmpImmBranch(kCondEq, object.reg.GetReg(), 0, NULL); 1052 1053 int check_class = AllocTypedTemp(false, kCoreReg); 1054 int object_class = AllocTypedTemp(false, kCoreReg); 1055 1056 LoadCurrMethodDirect(check_class); 1057 if (use_declaring_class) { 1058 LoadWordDisp(check_class, mirror::ArtMethod::DeclaringClassOffset().Int32Value(), 1059 check_class); 1060 LoadWordDisp(object.reg.GetReg(), mirror::Object::ClassOffset().Int32Value(), object_class); 1061 } else { 1062 LoadWordDisp(check_class, mirror::ArtMethod::DexCacheResolvedTypesOffset().Int32Value(), 1063 check_class); 1064 LoadWordDisp(object.reg.GetReg(), mirror::Object::ClassOffset().Int32Value(), object_class); 1065 int32_t offset_of_type = 1066 mirror::Array::DataOffset(sizeof(mirror::Class*)).Int32Value() + 1067 (sizeof(mirror::Class*) * type_idx); 1068 LoadWordDisp(check_class, offset_of_type, check_class); 1069 } 1070 1071 LIR* ne_branchover = NULL; 1072 if (cu_->instruction_set == kThumb2) { 1073 OpRegReg(kOpCmp, check_class, object_class); // Same? 1074 OpIT(kCondEq, ""); // if-convert the test 1075 LoadConstant(result_reg, 1); // .eq case - load true 1076 } else { 1077 ne_branchover = OpCmpBranch(kCondNe, check_class, object_class, NULL); 1078 LoadConstant(result_reg, 1); // eq case - load true 1079 } 1080 LIR* target = NewLIR0(kPseudoTargetLabel); 1081 null_branchover->target = target; 1082 if (ne_branchover != NULL) { 1083 ne_branchover->target = target; 1084 } 1085 FreeTemp(object_class); 1086 FreeTemp(check_class); 1087 if (IsTemp(result_reg)) { 1088 OpRegCopy(rl_result.reg.GetReg(), result_reg); 1089 FreeTemp(result_reg); 1090 } 1091 StoreValue(rl_dest, rl_result); 1092} 1093 1094void Mir2Lir::GenInstanceofCallingHelper(bool needs_access_check, bool type_known_final, 1095 bool type_known_abstract, bool use_declaring_class, 1096 bool can_assume_type_is_in_dex_cache, 1097 uint32_t type_idx, RegLocation rl_dest, 1098 RegLocation rl_src) { 1099 // X86 has its own implementation. 1100 DCHECK_NE(cu_->instruction_set, kX86); 1101 1102 FlushAllRegs(); 1103 // May generate a call - use explicit registers 1104 LockCallTemps(); 1105 LoadCurrMethodDirect(TargetReg(kArg1)); // kArg1 <= current Method* 1106 int class_reg = TargetReg(kArg2); // kArg2 will hold the Class* 1107 if (needs_access_check) { 1108 // Check we have access to type_idx and if not throw IllegalAccessError, 1109 // returns Class* in kArg0 1110 CallRuntimeHelperImm(QUICK_ENTRYPOINT_OFFSET(pInitializeTypeAndVerifyAccess), 1111 type_idx, true); 1112 OpRegCopy(class_reg, TargetReg(kRet0)); // Align usage with fast path 1113 LoadValueDirectFixed(rl_src, TargetReg(kArg0)); // kArg0 <= ref 1114 } else if (use_declaring_class) { 1115 LoadValueDirectFixed(rl_src, TargetReg(kArg0)); // kArg0 <= ref 1116 LoadWordDisp(TargetReg(kArg1), 1117 mirror::ArtMethod::DeclaringClassOffset().Int32Value(), class_reg); 1118 } else { 1119 // Load dex cache entry into class_reg (kArg2) 1120 LoadValueDirectFixed(rl_src, TargetReg(kArg0)); // kArg0 <= ref 1121 LoadWordDisp(TargetReg(kArg1), 1122 mirror::ArtMethod::DexCacheResolvedTypesOffset().Int32Value(), class_reg); 1123 int32_t offset_of_type = 1124 mirror::Array::DataOffset(sizeof(mirror::Class*)).Int32Value() + (sizeof(mirror::Class*) 1125 * type_idx); 1126 LoadWordDisp(class_reg, offset_of_type, class_reg); 1127 if (!can_assume_type_is_in_dex_cache) { 1128 // Need to test presence of type in dex cache at runtime 1129 LIR* hop_branch = OpCmpImmBranch(kCondNe, class_reg, 0, NULL); 1130 // Not resolved 1131 // Call out to helper, which will return resolved type in kRet0 1132 CallRuntimeHelperImm(QUICK_ENTRYPOINT_OFFSET(pInitializeType), type_idx, true); 1133 OpRegCopy(TargetReg(kArg2), TargetReg(kRet0)); // Align usage with fast path 1134 LoadValueDirectFixed(rl_src, TargetReg(kArg0)); /* reload Ref */ 1135 // Rejoin code paths 1136 LIR* hop_target = NewLIR0(kPseudoTargetLabel); 1137 hop_branch->target = hop_target; 1138 } 1139 } 1140 /* kArg0 is ref, kArg2 is class. If ref==null, use directly as bool result */ 1141 RegLocation rl_result = GetReturn(false); 1142 if (cu_->instruction_set == kMips) { 1143 // On MIPS rArg0 != rl_result, place false in result if branch is taken. 1144 LoadConstant(rl_result.reg.GetReg(), 0); 1145 } 1146 LIR* branch1 = OpCmpImmBranch(kCondEq, TargetReg(kArg0), 0, NULL); 1147 1148 /* load object->klass_ */ 1149 DCHECK_EQ(mirror::Object::ClassOffset().Int32Value(), 0); 1150 LoadWordDisp(TargetReg(kArg0), mirror::Object::ClassOffset().Int32Value(), TargetReg(kArg1)); 1151 /* kArg0 is ref, kArg1 is ref->klass_, kArg2 is class */ 1152 LIR* branchover = NULL; 1153 if (type_known_final) { 1154 // rl_result == ref == null == 0. 1155 if (cu_->instruction_set == kThumb2) { 1156 OpRegReg(kOpCmp, TargetReg(kArg1), TargetReg(kArg2)); // Same? 1157 OpIT(kCondEq, "E"); // if-convert the test 1158 LoadConstant(rl_result.reg.GetReg(), 1); // .eq case - load true 1159 LoadConstant(rl_result.reg.GetReg(), 0); // .ne case - load false 1160 } else { 1161 LoadConstant(rl_result.reg.GetReg(), 0); // ne case - load false 1162 branchover = OpCmpBranch(kCondNe, TargetReg(kArg1), TargetReg(kArg2), NULL); 1163 LoadConstant(rl_result.reg.GetReg(), 1); // eq case - load true 1164 } 1165 } else { 1166 if (cu_->instruction_set == kThumb2) { 1167 int r_tgt = LoadHelper(QUICK_ENTRYPOINT_OFFSET(pInstanceofNonTrivial)); 1168 if (!type_known_abstract) { 1169 /* Uses conditional nullification */ 1170 OpRegReg(kOpCmp, TargetReg(kArg1), TargetReg(kArg2)); // Same? 1171 OpIT(kCondEq, "EE"); // if-convert the test 1172 LoadConstant(TargetReg(kArg0), 1); // .eq case - load true 1173 } 1174 OpRegCopy(TargetReg(kArg0), TargetReg(kArg2)); // .ne case - arg0 <= class 1175 OpReg(kOpBlx, r_tgt); // .ne case: helper(class, ref->class) 1176 FreeTemp(r_tgt); 1177 } else { 1178 if (!type_known_abstract) { 1179 /* Uses branchovers */ 1180 LoadConstant(rl_result.reg.GetReg(), 1); // assume true 1181 branchover = OpCmpBranch(kCondEq, TargetReg(kArg1), TargetReg(kArg2), NULL); 1182 } 1183 int r_tgt = LoadHelper(QUICK_ENTRYPOINT_OFFSET(pInstanceofNonTrivial)); 1184 OpRegCopy(TargetReg(kArg0), TargetReg(kArg2)); // .ne case - arg0 <= class 1185 OpReg(kOpBlx, r_tgt); // .ne case: helper(class, ref->class) 1186 FreeTemp(r_tgt); 1187 } 1188 } 1189 // TODO: only clobber when type isn't final? 1190 ClobberCallerSave(); 1191 /* branch targets here */ 1192 LIR* target = NewLIR0(kPseudoTargetLabel); 1193 StoreValue(rl_dest, rl_result); 1194 branch1->target = target; 1195 if (branchover != NULL) { 1196 branchover->target = target; 1197 } 1198} 1199 1200void Mir2Lir::GenInstanceof(uint32_t type_idx, RegLocation rl_dest, RegLocation rl_src) { 1201 bool type_known_final, type_known_abstract, use_declaring_class; 1202 bool needs_access_check = !cu_->compiler_driver->CanAccessTypeWithoutChecks(cu_->method_idx, 1203 *cu_->dex_file, 1204 type_idx, 1205 &type_known_final, 1206 &type_known_abstract, 1207 &use_declaring_class); 1208 bool can_assume_type_is_in_dex_cache = !needs_access_check && 1209 cu_->compiler_driver->CanAssumeTypeIsPresentInDexCache(*cu_->dex_file, type_idx); 1210 1211 if ((use_declaring_class || can_assume_type_is_in_dex_cache) && type_known_final) { 1212 GenInstanceofFinal(use_declaring_class, type_idx, rl_dest, rl_src); 1213 } else { 1214 GenInstanceofCallingHelper(needs_access_check, type_known_final, type_known_abstract, 1215 use_declaring_class, can_assume_type_is_in_dex_cache, 1216 type_idx, rl_dest, rl_src); 1217 } 1218} 1219 1220void Mir2Lir::GenCheckCast(uint32_t insn_idx, uint32_t type_idx, RegLocation rl_src) { 1221 bool type_known_final, type_known_abstract, use_declaring_class; 1222 bool needs_access_check = !cu_->compiler_driver->CanAccessTypeWithoutChecks(cu_->method_idx, 1223 *cu_->dex_file, 1224 type_idx, 1225 &type_known_final, 1226 &type_known_abstract, 1227 &use_declaring_class); 1228 // Note: currently type_known_final is unused, as optimizing will only improve the performance 1229 // of the exception throw path. 1230 DexCompilationUnit* cu = mir_graph_->GetCurrentDexCompilationUnit(); 1231 if (!needs_access_check && cu_->compiler_driver->IsSafeCast(cu, insn_idx)) { 1232 // Verifier type analysis proved this check cast would never cause an exception. 1233 return; 1234 } 1235 FlushAllRegs(); 1236 // May generate a call - use explicit registers 1237 LockCallTemps(); 1238 LoadCurrMethodDirect(TargetReg(kArg1)); // kArg1 <= current Method* 1239 int class_reg = TargetReg(kArg2); // kArg2 will hold the Class* 1240 if (needs_access_check) { 1241 // Check we have access to type_idx and if not throw IllegalAccessError, 1242 // returns Class* in kRet0 1243 // InitializeTypeAndVerifyAccess(idx, method) 1244 CallRuntimeHelperImmReg(QUICK_ENTRYPOINT_OFFSET(pInitializeTypeAndVerifyAccess), 1245 type_idx, TargetReg(kArg1), true); 1246 OpRegCopy(class_reg, TargetReg(kRet0)); // Align usage with fast path 1247 } else if (use_declaring_class) { 1248 LoadWordDisp(TargetReg(kArg1), 1249 mirror::ArtMethod::DeclaringClassOffset().Int32Value(), class_reg); 1250 } else { 1251 // Load dex cache entry into class_reg (kArg2) 1252 LoadWordDisp(TargetReg(kArg1), 1253 mirror::ArtMethod::DexCacheResolvedTypesOffset().Int32Value(), class_reg); 1254 int32_t offset_of_type = 1255 mirror::Array::DataOffset(sizeof(mirror::Class*)).Int32Value() + 1256 (sizeof(mirror::Class*) * type_idx); 1257 LoadWordDisp(class_reg, offset_of_type, class_reg); 1258 if (!cu_->compiler_driver->CanAssumeTypeIsPresentInDexCache(*cu_->dex_file, type_idx)) { 1259 // Need to test presence of type in dex cache at runtime 1260 LIR* hop_branch = OpCmpImmBranch(kCondEq, class_reg, 0, NULL); 1261 LIR* cont = NewLIR0(kPseudoTargetLabel); 1262 1263 // Slow path to initialize the type. Executed if the type is NULL. 1264 class SlowPath : public LIRSlowPath { 1265 public: 1266 SlowPath(Mir2Lir* m2l, LIR* fromfast, LIR* cont, const int type_idx, 1267 const int class_reg) : 1268 LIRSlowPath(m2l, m2l->GetCurrentDexPc(), fromfast, cont), type_idx_(type_idx), 1269 class_reg_(class_reg) { 1270 } 1271 1272 void Compile() { 1273 GenerateTargetLabel(); 1274 1275 // Call out to helper, which will return resolved type in kArg0 1276 // InitializeTypeFromCode(idx, method) 1277 m2l_->CallRuntimeHelperImmReg(QUICK_ENTRYPOINT_OFFSET(pInitializeType), type_idx_, 1278 m2l_->TargetReg(kArg1), true); 1279 m2l_->OpRegCopy(class_reg_, m2l_->TargetReg(kRet0)); // Align usage with fast path 1280 m2l_->OpUnconditionalBranch(cont_); 1281 } 1282 public: 1283 const int type_idx_; 1284 const int class_reg_; 1285 }; 1286 1287 AddSlowPath(new (arena_) SlowPath(this, hop_branch, cont, 1288 type_idx, class_reg)); 1289 } 1290 } 1291 // At this point, class_reg (kArg2) has class 1292 LoadValueDirectFixed(rl_src, TargetReg(kArg0)); // kArg0 <= ref 1293 1294 // Slow path for the case where the classes are not equal. In this case we need 1295 // to call a helper function to do the check. 1296 class SlowPath : public LIRSlowPath { 1297 public: 1298 SlowPath(Mir2Lir* m2l, LIR* fromfast, LIR* cont, bool load): 1299 LIRSlowPath(m2l, m2l->GetCurrentDexPc(), fromfast, cont), load_(load) { 1300 } 1301 1302 void Compile() { 1303 GenerateTargetLabel(); 1304 1305 if (load_) { 1306 m2l_->LoadWordDisp(m2l_->TargetReg(kArg0), mirror::Object::ClassOffset().Int32Value(), 1307 m2l_->TargetReg(kArg1)); 1308 } 1309 m2l_->CallRuntimeHelperRegReg(QUICK_ENTRYPOINT_OFFSET(pCheckCast), m2l_->TargetReg(kArg2), 1310 m2l_->TargetReg(kArg1), true); 1311 1312 m2l_->OpUnconditionalBranch(cont_); 1313 } 1314 1315 private: 1316 bool load_; 1317 }; 1318 1319 if (type_known_abstract) { 1320 // Easier case, run slow path if target is non-null (slow path will load from target) 1321 LIR* branch = OpCmpImmBranch(kCondNe, TargetReg(kArg0), 0, NULL); 1322 LIR* cont = NewLIR0(kPseudoTargetLabel); 1323 AddSlowPath(new (arena_) SlowPath(this, branch, cont, true)); 1324 } else { 1325 // Harder, more common case. We need to generate a forward branch over the load 1326 // if the target is null. If it's non-null we perform the load and branch to the 1327 // slow path if the classes are not equal. 1328 1329 /* Null is OK - continue */ 1330 LIR* branch1 = OpCmpImmBranch(kCondEq, TargetReg(kArg0), 0, NULL); 1331 /* load object->klass_ */ 1332 DCHECK_EQ(mirror::Object::ClassOffset().Int32Value(), 0); 1333 LoadWordDisp(TargetReg(kArg0), mirror::Object::ClassOffset().Int32Value(), 1334 TargetReg(kArg1)); 1335 1336 LIR* branch2 = OpCmpBranch(kCondNe, TargetReg(kArg1), class_reg, NULL); 1337 LIR* cont = NewLIR0(kPseudoTargetLabel); 1338 1339 // Add the slow path that will not perform load since this is already done. 1340 AddSlowPath(new (arena_) SlowPath(this, branch2, cont, false)); 1341 1342 // Set the null check to branch to the continuation. 1343 branch1->target = cont; 1344 } 1345} 1346 1347void Mir2Lir::GenLong3Addr(OpKind first_op, OpKind second_op, RegLocation rl_dest, 1348 RegLocation rl_src1, RegLocation rl_src2) { 1349 RegLocation rl_result; 1350 if (cu_->instruction_set == kThumb2) { 1351 /* 1352 * NOTE: This is the one place in the code in which we might have 1353 * as many as six live temporary registers. There are 5 in the normal 1354 * set for Arm. Until we have spill capabilities, temporarily add 1355 * lr to the temp set. It is safe to do this locally, but note that 1356 * lr is used explicitly elsewhere in the code generator and cannot 1357 * normally be used as a general temp register. 1358 */ 1359 MarkTemp(TargetReg(kLr)); // Add lr to the temp pool 1360 FreeTemp(TargetReg(kLr)); // and make it available 1361 } 1362 rl_src1 = LoadValueWide(rl_src1, kCoreReg); 1363 rl_src2 = LoadValueWide(rl_src2, kCoreReg); 1364 rl_result = EvalLoc(rl_dest, kCoreReg, true); 1365 // The longs may overlap - use intermediate temp if so 1366 if ((rl_result.reg.GetReg() == rl_src1.reg.GetHighReg()) || (rl_result.reg.GetReg() == rl_src2.reg.GetHighReg())) { 1367 int t_reg = AllocTemp(); 1368 OpRegRegReg(first_op, t_reg, rl_src1.reg.GetReg(), rl_src2.reg.GetReg()); 1369 OpRegRegReg(second_op, rl_result.reg.GetHighReg(), rl_src1.reg.GetHighReg(), rl_src2.reg.GetHighReg()); 1370 OpRegCopy(rl_result.reg.GetReg(), t_reg); 1371 FreeTemp(t_reg); 1372 } else { 1373 OpRegRegReg(first_op, rl_result.reg.GetReg(), rl_src1.reg.GetReg(), rl_src2.reg.GetReg()); 1374 OpRegRegReg(second_op, rl_result.reg.GetHighReg(), rl_src1.reg.GetHighReg(), 1375 rl_src2.reg.GetHighReg()); 1376 } 1377 /* 1378 * NOTE: If rl_dest refers to a frame variable in a large frame, the 1379 * following StoreValueWide might need to allocate a temp register. 1380 * To further work around the lack of a spill capability, explicitly 1381 * free any temps from rl_src1 & rl_src2 that aren't still live in rl_result. 1382 * Remove when spill is functional. 1383 */ 1384 FreeRegLocTemps(rl_result, rl_src1); 1385 FreeRegLocTemps(rl_result, rl_src2); 1386 StoreValueWide(rl_dest, rl_result); 1387 if (cu_->instruction_set == kThumb2) { 1388 Clobber(TargetReg(kLr)); 1389 UnmarkTemp(TargetReg(kLr)); // Remove lr from the temp pool 1390 } 1391} 1392 1393 1394void Mir2Lir::GenShiftOpLong(Instruction::Code opcode, RegLocation rl_dest, 1395 RegLocation rl_src1, RegLocation rl_shift) { 1396 ThreadOffset func_offset(-1); 1397 1398 switch (opcode) { 1399 case Instruction::SHL_LONG: 1400 case Instruction::SHL_LONG_2ADDR: 1401 func_offset = QUICK_ENTRYPOINT_OFFSET(pShlLong); 1402 break; 1403 case Instruction::SHR_LONG: 1404 case Instruction::SHR_LONG_2ADDR: 1405 func_offset = QUICK_ENTRYPOINT_OFFSET(pShrLong); 1406 break; 1407 case Instruction::USHR_LONG: 1408 case Instruction::USHR_LONG_2ADDR: 1409 func_offset = QUICK_ENTRYPOINT_OFFSET(pUshrLong); 1410 break; 1411 default: 1412 LOG(FATAL) << "Unexpected case"; 1413 } 1414 FlushAllRegs(); /* Send everything to home location */ 1415 CallRuntimeHelperRegLocationRegLocation(func_offset, rl_src1, rl_shift, false); 1416 RegLocation rl_result = GetReturnWide(false); 1417 StoreValueWide(rl_dest, rl_result); 1418} 1419 1420 1421void Mir2Lir::GenArithOpInt(Instruction::Code opcode, RegLocation rl_dest, 1422 RegLocation rl_src1, RegLocation rl_src2) { 1423 DCHECK_NE(cu_->instruction_set, kX86); 1424 OpKind op = kOpBkpt; 1425 bool is_div_rem = false; 1426 bool check_zero = false; 1427 bool unary = false; 1428 RegLocation rl_result; 1429 bool shift_op = false; 1430 switch (opcode) { 1431 case Instruction::NEG_INT: 1432 op = kOpNeg; 1433 unary = true; 1434 break; 1435 case Instruction::NOT_INT: 1436 op = kOpMvn; 1437 unary = true; 1438 break; 1439 case Instruction::ADD_INT: 1440 case Instruction::ADD_INT_2ADDR: 1441 op = kOpAdd; 1442 break; 1443 case Instruction::SUB_INT: 1444 case Instruction::SUB_INT_2ADDR: 1445 op = kOpSub; 1446 break; 1447 case Instruction::MUL_INT: 1448 case Instruction::MUL_INT_2ADDR: 1449 op = kOpMul; 1450 break; 1451 case Instruction::DIV_INT: 1452 case Instruction::DIV_INT_2ADDR: 1453 check_zero = true; 1454 op = kOpDiv; 1455 is_div_rem = true; 1456 break; 1457 /* NOTE: returns in kArg1 */ 1458 case Instruction::REM_INT: 1459 case Instruction::REM_INT_2ADDR: 1460 check_zero = true; 1461 op = kOpRem; 1462 is_div_rem = true; 1463 break; 1464 case Instruction::AND_INT: 1465 case Instruction::AND_INT_2ADDR: 1466 op = kOpAnd; 1467 break; 1468 case Instruction::OR_INT: 1469 case Instruction::OR_INT_2ADDR: 1470 op = kOpOr; 1471 break; 1472 case Instruction::XOR_INT: 1473 case Instruction::XOR_INT_2ADDR: 1474 op = kOpXor; 1475 break; 1476 case Instruction::SHL_INT: 1477 case Instruction::SHL_INT_2ADDR: 1478 shift_op = true; 1479 op = kOpLsl; 1480 break; 1481 case Instruction::SHR_INT: 1482 case Instruction::SHR_INT_2ADDR: 1483 shift_op = true; 1484 op = kOpAsr; 1485 break; 1486 case Instruction::USHR_INT: 1487 case Instruction::USHR_INT_2ADDR: 1488 shift_op = true; 1489 op = kOpLsr; 1490 break; 1491 default: 1492 LOG(FATAL) << "Invalid word arith op: " << opcode; 1493 } 1494 if (!is_div_rem) { 1495 if (unary) { 1496 rl_src1 = LoadValue(rl_src1, kCoreReg); 1497 rl_result = EvalLoc(rl_dest, kCoreReg, true); 1498 OpRegReg(op, rl_result.reg.GetReg(), rl_src1.reg.GetReg()); 1499 } else { 1500 if (shift_op) { 1501 int t_reg = INVALID_REG; 1502 rl_src2 = LoadValue(rl_src2, kCoreReg); 1503 t_reg = AllocTemp(); 1504 OpRegRegImm(kOpAnd, t_reg, rl_src2.reg.GetReg(), 31); 1505 rl_src1 = LoadValue(rl_src1, kCoreReg); 1506 rl_result = EvalLoc(rl_dest, kCoreReg, true); 1507 OpRegRegReg(op, rl_result.reg.GetReg(), rl_src1.reg.GetReg(), t_reg); 1508 FreeTemp(t_reg); 1509 } else { 1510 rl_src1 = LoadValue(rl_src1, kCoreReg); 1511 rl_src2 = LoadValue(rl_src2, kCoreReg); 1512 rl_result = EvalLoc(rl_dest, kCoreReg, true); 1513 OpRegRegReg(op, rl_result.reg.GetReg(), rl_src1.reg.GetReg(), rl_src2.reg.GetReg()); 1514 } 1515 } 1516 StoreValue(rl_dest, rl_result); 1517 } else { 1518 bool done = false; // Set to true if we happen to find a way to use a real instruction. 1519 if (cu_->instruction_set == kMips) { 1520 rl_src1 = LoadValue(rl_src1, kCoreReg); 1521 rl_src2 = LoadValue(rl_src2, kCoreReg); 1522 if (check_zero) { 1523 GenImmedCheck(kCondEq, rl_src2.reg.GetReg(), 0, kThrowDivZero); 1524 } 1525 rl_result = GenDivRem(rl_dest, rl_src1.reg.GetReg(), rl_src2.reg.GetReg(), op == kOpDiv); 1526 done = true; 1527 } else if (cu_->instruction_set == kThumb2) { 1528 if (cu_->GetInstructionSetFeatures().HasDivideInstruction()) { 1529 // Use ARM SDIV instruction for division. For remainder we also need to 1530 // calculate using a MUL and subtract. 1531 rl_src1 = LoadValue(rl_src1, kCoreReg); 1532 rl_src2 = LoadValue(rl_src2, kCoreReg); 1533 if (check_zero) { 1534 GenImmedCheck(kCondEq, rl_src2.reg.GetReg(), 0, kThrowDivZero); 1535 } 1536 rl_result = GenDivRem(rl_dest, rl_src1.reg.GetReg(), rl_src2.reg.GetReg(), op == kOpDiv); 1537 done = true; 1538 } 1539 } 1540 1541 // If we haven't already generated the code use the callout function. 1542 if (!done) { 1543 ThreadOffset func_offset = QUICK_ENTRYPOINT_OFFSET(pIdivmod); 1544 FlushAllRegs(); /* Send everything to home location */ 1545 LoadValueDirectFixed(rl_src2, TargetReg(kArg1)); 1546 int r_tgt = CallHelperSetup(func_offset); 1547 LoadValueDirectFixed(rl_src1, TargetReg(kArg0)); 1548 if (check_zero) { 1549 GenImmedCheck(kCondEq, TargetReg(kArg1), 0, kThrowDivZero); 1550 } 1551 // NOTE: callout here is not a safepoint. 1552 CallHelper(r_tgt, func_offset, false /* not a safepoint */); 1553 if (op == kOpDiv) 1554 rl_result = GetReturn(false); 1555 else 1556 rl_result = GetReturnAlt(); 1557 } 1558 StoreValue(rl_dest, rl_result); 1559 } 1560} 1561 1562/* 1563 * The following are the first-level codegen routines that analyze the format 1564 * of each bytecode then either dispatch special purpose codegen routines 1565 * or produce corresponding Thumb instructions directly. 1566 */ 1567 1568// Returns true if no more than two bits are set in 'x'. 1569static bool IsPopCountLE2(unsigned int x) { 1570 x &= x - 1; 1571 return (x & (x - 1)) == 0; 1572} 1573 1574// Returns true if it added instructions to 'cu' to divide 'rl_src' by 'lit' 1575// and store the result in 'rl_dest'. 1576bool Mir2Lir::HandleEasyDivRem(Instruction::Code dalvik_opcode, bool is_div, 1577 RegLocation rl_src, RegLocation rl_dest, int lit) { 1578 if ((lit < 2) || ((cu_->instruction_set != kThumb2) && !IsPowerOfTwo(lit))) { 1579 return false; 1580 } 1581 // No divide instruction for Arm, so check for more special cases 1582 if ((cu_->instruction_set == kThumb2) && !IsPowerOfTwo(lit)) { 1583 return SmallLiteralDivRem(dalvik_opcode, is_div, rl_src, rl_dest, lit); 1584 } 1585 int k = LowestSetBit(lit); 1586 if (k >= 30) { 1587 // Avoid special cases. 1588 return false; 1589 } 1590 rl_src = LoadValue(rl_src, kCoreReg); 1591 RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); 1592 if (is_div) { 1593 int t_reg = AllocTemp(); 1594 if (lit == 2) { 1595 // Division by 2 is by far the most common division by constant. 1596 OpRegRegImm(kOpLsr, t_reg, rl_src.reg.GetReg(), 32 - k); 1597 OpRegRegReg(kOpAdd, t_reg, t_reg, rl_src.reg.GetReg()); 1598 OpRegRegImm(kOpAsr, rl_result.reg.GetReg(), t_reg, k); 1599 } else { 1600 OpRegRegImm(kOpAsr, t_reg, rl_src.reg.GetReg(), 31); 1601 OpRegRegImm(kOpLsr, t_reg, t_reg, 32 - k); 1602 OpRegRegReg(kOpAdd, t_reg, t_reg, rl_src.reg.GetReg()); 1603 OpRegRegImm(kOpAsr, rl_result.reg.GetReg(), t_reg, k); 1604 } 1605 } else { 1606 int t_reg1 = AllocTemp(); 1607 int t_reg2 = AllocTemp(); 1608 if (lit == 2) { 1609 OpRegRegImm(kOpLsr, t_reg1, rl_src.reg.GetReg(), 32 - k); 1610 OpRegRegReg(kOpAdd, t_reg2, t_reg1, rl_src.reg.GetReg()); 1611 OpRegRegImm(kOpAnd, t_reg2, t_reg2, lit -1); 1612 OpRegRegReg(kOpSub, rl_result.reg.GetReg(), t_reg2, t_reg1); 1613 } else { 1614 OpRegRegImm(kOpAsr, t_reg1, rl_src.reg.GetReg(), 31); 1615 OpRegRegImm(kOpLsr, t_reg1, t_reg1, 32 - k); 1616 OpRegRegReg(kOpAdd, t_reg2, t_reg1, rl_src.reg.GetReg()); 1617 OpRegRegImm(kOpAnd, t_reg2, t_reg2, lit - 1); 1618 OpRegRegReg(kOpSub, rl_result.reg.GetReg(), t_reg2, t_reg1); 1619 } 1620 } 1621 StoreValue(rl_dest, rl_result); 1622 return true; 1623} 1624 1625// Returns true if it added instructions to 'cu' to multiply 'rl_src' by 'lit' 1626// and store the result in 'rl_dest'. 1627bool Mir2Lir::HandleEasyMultiply(RegLocation rl_src, RegLocation rl_dest, int lit) { 1628 // Can we simplify this multiplication? 1629 bool power_of_two = false; 1630 bool pop_count_le2 = false; 1631 bool power_of_two_minus_one = false; 1632 if (lit < 2) { 1633 // Avoid special cases. 1634 return false; 1635 } else if (IsPowerOfTwo(lit)) { 1636 power_of_two = true; 1637 } else if (IsPopCountLE2(lit)) { 1638 pop_count_le2 = true; 1639 } else if (IsPowerOfTwo(lit + 1)) { 1640 power_of_two_minus_one = true; 1641 } else { 1642 return false; 1643 } 1644 rl_src = LoadValue(rl_src, kCoreReg); 1645 RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); 1646 if (power_of_two) { 1647 // Shift. 1648 OpRegRegImm(kOpLsl, rl_result.reg.GetReg(), rl_src.reg.GetReg(), LowestSetBit(lit)); 1649 } else if (pop_count_le2) { 1650 // Shift and add and shift. 1651 int first_bit = LowestSetBit(lit); 1652 int second_bit = LowestSetBit(lit ^ (1 << first_bit)); 1653 GenMultiplyByTwoBitMultiplier(rl_src, rl_result, lit, first_bit, second_bit); 1654 } else { 1655 // Reverse subtract: (src << (shift + 1)) - src. 1656 DCHECK(power_of_two_minus_one); 1657 // TUNING: rsb dst, src, src lsl#LowestSetBit(lit + 1) 1658 int t_reg = AllocTemp(); 1659 OpRegRegImm(kOpLsl, t_reg, rl_src.reg.GetReg(), LowestSetBit(lit + 1)); 1660 OpRegRegReg(kOpSub, rl_result.reg.GetReg(), t_reg, rl_src.reg.GetReg()); 1661 } 1662 StoreValue(rl_dest, rl_result); 1663 return true; 1664} 1665 1666void Mir2Lir::GenArithOpIntLit(Instruction::Code opcode, RegLocation rl_dest, RegLocation rl_src, 1667 int lit) { 1668 RegLocation rl_result; 1669 OpKind op = static_cast<OpKind>(0); /* Make gcc happy */ 1670 int shift_op = false; 1671 bool is_div = false; 1672 1673 switch (opcode) { 1674 case Instruction::RSUB_INT_LIT8: 1675 case Instruction::RSUB_INT: { 1676 rl_src = LoadValue(rl_src, kCoreReg); 1677 rl_result = EvalLoc(rl_dest, kCoreReg, true); 1678 if (cu_->instruction_set == kThumb2) { 1679 OpRegRegImm(kOpRsub, rl_result.reg.GetReg(), rl_src.reg.GetReg(), lit); 1680 } else { 1681 OpRegReg(kOpNeg, rl_result.reg.GetReg(), rl_src.reg.GetReg()); 1682 OpRegImm(kOpAdd, rl_result.reg.GetReg(), lit); 1683 } 1684 StoreValue(rl_dest, rl_result); 1685 return; 1686 } 1687 1688 case Instruction::SUB_INT: 1689 case Instruction::SUB_INT_2ADDR: 1690 lit = -lit; 1691 // Intended fallthrough 1692 case Instruction::ADD_INT: 1693 case Instruction::ADD_INT_2ADDR: 1694 case Instruction::ADD_INT_LIT8: 1695 case Instruction::ADD_INT_LIT16: 1696 op = kOpAdd; 1697 break; 1698 case Instruction::MUL_INT: 1699 case Instruction::MUL_INT_2ADDR: 1700 case Instruction::MUL_INT_LIT8: 1701 case Instruction::MUL_INT_LIT16: { 1702 if (HandleEasyMultiply(rl_src, rl_dest, lit)) { 1703 return; 1704 } 1705 op = kOpMul; 1706 break; 1707 } 1708 case Instruction::AND_INT: 1709 case Instruction::AND_INT_2ADDR: 1710 case Instruction::AND_INT_LIT8: 1711 case Instruction::AND_INT_LIT16: 1712 op = kOpAnd; 1713 break; 1714 case Instruction::OR_INT: 1715 case Instruction::OR_INT_2ADDR: 1716 case Instruction::OR_INT_LIT8: 1717 case Instruction::OR_INT_LIT16: 1718 op = kOpOr; 1719 break; 1720 case Instruction::XOR_INT: 1721 case Instruction::XOR_INT_2ADDR: 1722 case Instruction::XOR_INT_LIT8: 1723 case Instruction::XOR_INT_LIT16: 1724 op = kOpXor; 1725 break; 1726 case Instruction::SHL_INT_LIT8: 1727 case Instruction::SHL_INT: 1728 case Instruction::SHL_INT_2ADDR: 1729 lit &= 31; 1730 shift_op = true; 1731 op = kOpLsl; 1732 break; 1733 case Instruction::SHR_INT_LIT8: 1734 case Instruction::SHR_INT: 1735 case Instruction::SHR_INT_2ADDR: 1736 lit &= 31; 1737 shift_op = true; 1738 op = kOpAsr; 1739 break; 1740 case Instruction::USHR_INT_LIT8: 1741 case Instruction::USHR_INT: 1742 case Instruction::USHR_INT_2ADDR: 1743 lit &= 31; 1744 shift_op = true; 1745 op = kOpLsr; 1746 break; 1747 1748 case Instruction::DIV_INT: 1749 case Instruction::DIV_INT_2ADDR: 1750 case Instruction::DIV_INT_LIT8: 1751 case Instruction::DIV_INT_LIT16: 1752 case Instruction::REM_INT: 1753 case Instruction::REM_INT_2ADDR: 1754 case Instruction::REM_INT_LIT8: 1755 case Instruction::REM_INT_LIT16: { 1756 if (lit == 0) { 1757 GenImmedCheck(kCondAl, 0, 0, kThrowDivZero); 1758 return; 1759 } 1760 if ((opcode == Instruction::DIV_INT) || 1761 (opcode == Instruction::DIV_INT_2ADDR) || 1762 (opcode == Instruction::DIV_INT_LIT8) || 1763 (opcode == Instruction::DIV_INT_LIT16)) { 1764 is_div = true; 1765 } else { 1766 is_div = false; 1767 } 1768 if (HandleEasyDivRem(opcode, is_div, rl_src, rl_dest, lit)) { 1769 return; 1770 } 1771 1772 bool done = false; 1773 if (cu_->instruction_set == kMips) { 1774 rl_src = LoadValue(rl_src, kCoreReg); 1775 rl_result = GenDivRemLit(rl_dest, rl_src.reg.GetReg(), lit, is_div); 1776 done = true; 1777 } else if (cu_->instruction_set == kX86) { 1778 rl_result = GenDivRemLit(rl_dest, rl_src, lit, is_div); 1779 done = true; 1780 } else if (cu_->instruction_set == kThumb2) { 1781 if (cu_->GetInstructionSetFeatures().HasDivideInstruction()) { 1782 // Use ARM SDIV instruction for division. For remainder we also need to 1783 // calculate using a MUL and subtract. 1784 rl_src = LoadValue(rl_src, kCoreReg); 1785 rl_result = GenDivRemLit(rl_dest, rl_src.reg.GetReg(), lit, is_div); 1786 done = true; 1787 } 1788 } 1789 1790 if (!done) { 1791 FlushAllRegs(); /* Everything to home location. */ 1792 LoadValueDirectFixed(rl_src, TargetReg(kArg0)); 1793 Clobber(TargetReg(kArg0)); 1794 ThreadOffset func_offset = QUICK_ENTRYPOINT_OFFSET(pIdivmod); 1795 CallRuntimeHelperRegImm(func_offset, TargetReg(kArg0), lit, false); 1796 if (is_div) 1797 rl_result = GetReturn(false); 1798 else 1799 rl_result = GetReturnAlt(); 1800 } 1801 StoreValue(rl_dest, rl_result); 1802 return; 1803 } 1804 default: 1805 LOG(FATAL) << "Unexpected opcode " << opcode; 1806 } 1807 rl_src = LoadValue(rl_src, kCoreReg); 1808 rl_result = EvalLoc(rl_dest, kCoreReg, true); 1809 // Avoid shifts by literal 0 - no support in Thumb. Change to copy. 1810 if (shift_op && (lit == 0)) { 1811 OpRegCopy(rl_result.reg.GetReg(), rl_src.reg.GetReg()); 1812 } else { 1813 OpRegRegImm(op, rl_result.reg.GetReg(), rl_src.reg.GetReg(), lit); 1814 } 1815 StoreValue(rl_dest, rl_result); 1816} 1817 1818void Mir2Lir::GenArithOpLong(Instruction::Code opcode, RegLocation rl_dest, 1819 RegLocation rl_src1, RegLocation rl_src2) { 1820 RegLocation rl_result; 1821 OpKind first_op = kOpBkpt; 1822 OpKind second_op = kOpBkpt; 1823 bool call_out = false; 1824 bool check_zero = false; 1825 ThreadOffset func_offset(-1); 1826 int ret_reg = TargetReg(kRet0); 1827 1828 switch (opcode) { 1829 case Instruction::NOT_LONG: 1830 rl_src2 = LoadValueWide(rl_src2, kCoreReg); 1831 rl_result = EvalLoc(rl_dest, kCoreReg, true); 1832 // Check for destructive overlap 1833 if (rl_result.reg.GetReg() == rl_src2.reg.GetHighReg()) { 1834 int t_reg = AllocTemp(); 1835 OpRegCopy(t_reg, rl_src2.reg.GetHighReg()); 1836 OpRegReg(kOpMvn, rl_result.reg.GetReg(), rl_src2.reg.GetReg()); 1837 OpRegReg(kOpMvn, rl_result.reg.GetHighReg(), t_reg); 1838 FreeTemp(t_reg); 1839 } else { 1840 OpRegReg(kOpMvn, rl_result.reg.GetReg(), rl_src2.reg.GetReg()); 1841 OpRegReg(kOpMvn, rl_result.reg.GetHighReg(), rl_src2.reg.GetHighReg()); 1842 } 1843 StoreValueWide(rl_dest, rl_result); 1844 return; 1845 case Instruction::ADD_LONG: 1846 case Instruction::ADD_LONG_2ADDR: 1847 if (cu_->instruction_set != kThumb2) { 1848 GenAddLong(opcode, rl_dest, rl_src1, rl_src2); 1849 return; 1850 } 1851 first_op = kOpAdd; 1852 second_op = kOpAdc; 1853 break; 1854 case Instruction::SUB_LONG: 1855 case Instruction::SUB_LONG_2ADDR: 1856 if (cu_->instruction_set != kThumb2) { 1857 GenSubLong(opcode, rl_dest, rl_src1, rl_src2); 1858 return; 1859 } 1860 first_op = kOpSub; 1861 second_op = kOpSbc; 1862 break; 1863 case Instruction::MUL_LONG: 1864 case Instruction::MUL_LONG_2ADDR: 1865 if (cu_->instruction_set != kMips) { 1866 GenMulLong(opcode, rl_dest, rl_src1, rl_src2); 1867 return; 1868 } else { 1869 call_out = true; 1870 ret_reg = TargetReg(kRet0); 1871 func_offset = QUICK_ENTRYPOINT_OFFSET(pLmul); 1872 } 1873 break; 1874 case Instruction::DIV_LONG: 1875 case Instruction::DIV_LONG_2ADDR: 1876 call_out = true; 1877 check_zero = true; 1878 ret_reg = TargetReg(kRet0); 1879 func_offset = QUICK_ENTRYPOINT_OFFSET(pLdiv); 1880 break; 1881 case Instruction::REM_LONG: 1882 case Instruction::REM_LONG_2ADDR: 1883 call_out = true; 1884 check_zero = true; 1885 func_offset = QUICK_ENTRYPOINT_OFFSET(pLmod); 1886 /* NOTE - for Arm, result is in kArg2/kArg3 instead of kRet0/kRet1 */ 1887 ret_reg = (cu_->instruction_set == kThumb2) ? TargetReg(kArg2) : TargetReg(kRet0); 1888 break; 1889 case Instruction::AND_LONG_2ADDR: 1890 case Instruction::AND_LONG: 1891 if (cu_->instruction_set == kX86) { 1892 return GenAndLong(opcode, rl_dest, rl_src1, rl_src2); 1893 } 1894 first_op = kOpAnd; 1895 second_op = kOpAnd; 1896 break; 1897 case Instruction::OR_LONG: 1898 case Instruction::OR_LONG_2ADDR: 1899 if (cu_->instruction_set == kX86) { 1900 GenOrLong(opcode, rl_dest, rl_src1, rl_src2); 1901 return; 1902 } 1903 first_op = kOpOr; 1904 second_op = kOpOr; 1905 break; 1906 case Instruction::XOR_LONG: 1907 case Instruction::XOR_LONG_2ADDR: 1908 if (cu_->instruction_set == kX86) { 1909 GenXorLong(opcode, rl_dest, rl_src1, rl_src2); 1910 return; 1911 } 1912 first_op = kOpXor; 1913 second_op = kOpXor; 1914 break; 1915 case Instruction::NEG_LONG: { 1916 GenNegLong(rl_dest, rl_src2); 1917 return; 1918 } 1919 default: 1920 LOG(FATAL) << "Invalid long arith op"; 1921 } 1922 if (!call_out) { 1923 GenLong3Addr(first_op, second_op, rl_dest, rl_src1, rl_src2); 1924 } else { 1925 FlushAllRegs(); /* Send everything to home location */ 1926 if (check_zero) { 1927 LoadValueDirectWideFixed(rl_src2, TargetReg(kArg2), TargetReg(kArg3)); 1928 int r_tgt = CallHelperSetup(func_offset); 1929 GenDivZeroCheck(TargetReg(kArg2), TargetReg(kArg3)); 1930 LoadValueDirectWideFixed(rl_src1, TargetReg(kArg0), TargetReg(kArg1)); 1931 // NOTE: callout here is not a safepoint 1932 CallHelper(r_tgt, func_offset, false /* not safepoint */); 1933 } else { 1934 CallRuntimeHelperRegLocationRegLocation(func_offset, rl_src1, rl_src2, false); 1935 } 1936 // Adjust return regs in to handle case of rem returning kArg2/kArg3 1937 if (ret_reg == TargetReg(kRet0)) 1938 rl_result = GetReturnWide(false); 1939 else 1940 rl_result = GetReturnWideAlt(); 1941 StoreValueWide(rl_dest, rl_result); 1942 } 1943} 1944 1945void Mir2Lir::GenConversionCall(ThreadOffset func_offset, 1946 RegLocation rl_dest, RegLocation rl_src) { 1947 /* 1948 * Don't optimize the register usage since it calls out to support 1949 * functions 1950 */ 1951 FlushAllRegs(); /* Send everything to home location */ 1952 CallRuntimeHelperRegLocation(func_offset, rl_src, false); 1953 if (rl_dest.wide) { 1954 RegLocation rl_result; 1955 rl_result = GetReturnWide(rl_dest.fp); 1956 StoreValueWide(rl_dest, rl_result); 1957 } else { 1958 RegLocation rl_result; 1959 rl_result = GetReturn(rl_dest.fp); 1960 StoreValue(rl_dest, rl_result); 1961 } 1962} 1963 1964/* Check if we need to check for pending suspend request */ 1965void Mir2Lir::GenSuspendTest(int opt_flags) { 1966 if (Runtime::Current()->ExplicitSuspendChecks()) { 1967 if (NO_SUSPEND || (opt_flags & MIR_IGNORE_SUSPEND_CHECK)) { 1968 return; 1969 } 1970 FlushAllRegs(); 1971 LIR* branch = OpTestSuspend(NULL); 1972 LIR* ret_lab = NewLIR0(kPseudoTargetLabel); 1973 LIR* target = RawLIR(current_dalvik_offset_, kPseudoSuspendTarget, WrapPointer(ret_lab), 1974 current_dalvik_offset_); 1975 branch->target = target; 1976 suspend_launchpads_.Insert(target); 1977 } else { 1978 if (NO_SUSPEND || (opt_flags & MIR_IGNORE_SUSPEND_CHECK)) { 1979 return; 1980 } 1981 FlushAllRegs(); // TODO: needed? 1982 LIR* inst = CheckSuspendUsingLoad(); 1983 MarkSafepointPC(inst); 1984 } 1985} 1986 1987/* Check if we need to check for pending suspend request */ 1988void Mir2Lir::GenSuspendTestAndBranch(int opt_flags, LIR* target) { 1989 if (Runtime::Current()->ExplicitSuspendChecks()) { 1990 if (NO_SUSPEND || (opt_flags & MIR_IGNORE_SUSPEND_CHECK)) { 1991 OpUnconditionalBranch(target); 1992 return; 1993 } 1994 OpTestSuspend(target); 1995 LIR* launch_pad = 1996 RawLIR(current_dalvik_offset_, kPseudoSuspendTarget, WrapPointer(target), 1997 current_dalvik_offset_); 1998 FlushAllRegs(); 1999 OpUnconditionalBranch(launch_pad); 2000 suspend_launchpads_.Insert(launch_pad); 2001 } else { 2002 // For the implicit suspend check, just perform the trigger 2003 // load and branch to the target. 2004 if (NO_SUSPEND || (opt_flags & MIR_IGNORE_SUSPEND_CHECK)) { 2005 OpUnconditionalBranch(target); 2006 return; 2007 } 2008 FlushAllRegs(); 2009 LIR* inst = CheckSuspendUsingLoad(); 2010 MarkSafepointPC(inst); 2011 OpUnconditionalBranch(target); 2012 } 2013} 2014 2015/* Call out to helper assembly routine that will null check obj and then lock it. */ 2016void Mir2Lir::GenMonitorEnter(int opt_flags, RegLocation rl_src) { 2017 FlushAllRegs(); 2018 CallRuntimeHelperRegLocation(QUICK_ENTRYPOINT_OFFSET(pLockObject), rl_src, true); 2019} 2020 2021/* Call out to helper assembly routine that will null check obj and then unlock it. */ 2022void Mir2Lir::GenMonitorExit(int opt_flags, RegLocation rl_src) { 2023 FlushAllRegs(); 2024 CallRuntimeHelperRegLocation(QUICK_ENTRYPOINT_OFFSET(pUnlockObject), rl_src, true); 2025} 2026 2027/* Generic code for generating a wide constant into a VR. */ 2028void Mir2Lir::GenConstWide(RegLocation rl_dest, int64_t value) { 2029 RegLocation rl_result = EvalLoc(rl_dest, kAnyReg, true); 2030 LoadConstantWide(rl_result.reg.GetReg(), rl_result.reg.GetHighReg(), value); 2031 StoreValueWide(rl_dest, rl_result); 2032} 2033 2034} // namespace art 2035