gen_invoke.cc revision 31c2aac7137b69d5622eea09597500731fbee2ef
1/* 2 * Copyright (C) 2012 The Android Open Source Project 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17#include "dex/compiler_ir.h" 18#include "dex/frontend.h" 19#include "dex/quick/dex_file_method_inliner.h" 20#include "dex/quick/dex_file_to_method_inliner_map.h" 21#include "dex_file-inl.h" 22#include "entrypoints/quick/quick_entrypoints.h" 23#include "invoke_type.h" 24#include "mirror/array.h" 25#include "mirror/string.h" 26#include "mir_to_lir-inl.h" 27#include "x86/codegen_x86.h" 28 29namespace art { 30 31/* 32 * This source files contains "gen" codegen routines that should 33 * be applicable to most targets. Only mid-level support utilities 34 * and "op" calls may be used here. 35 */ 36 37/* 38 * To save scheduling time, helper calls are broken into two parts: generation of 39 * the helper target address, and the actuall call to the helper. Because x86 40 * has a memory call operation, part 1 is a NOP for x86. For other targets, 41 * load arguments between the two parts. 42 */ 43int Mir2Lir::CallHelperSetup(ThreadOffset helper_offset) { 44 return (cu_->instruction_set == kX86) ? 0 : LoadHelper(helper_offset); 45} 46 47/* NOTE: if r_tgt is a temp, it will be freed following use */ 48LIR* Mir2Lir::CallHelper(int r_tgt, ThreadOffset helper_offset, bool safepoint_pc) { 49 LIR* call_inst; 50 if (cu_->instruction_set == kX86) { 51 call_inst = OpThreadMem(kOpBlx, helper_offset); 52 } else { 53 call_inst = OpReg(kOpBlx, r_tgt); 54 FreeTemp(r_tgt); 55 } 56 if (safepoint_pc) { 57 MarkSafepointPC(call_inst); 58 } 59 return call_inst; 60} 61 62void Mir2Lir::CallRuntimeHelperImm(ThreadOffset helper_offset, int arg0, bool safepoint_pc) { 63 int r_tgt = CallHelperSetup(helper_offset); 64 LoadConstant(TargetReg(kArg0), arg0); 65 ClobberCallerSave(); 66 CallHelper(r_tgt, helper_offset, safepoint_pc); 67} 68 69void Mir2Lir::CallRuntimeHelperReg(ThreadOffset helper_offset, int arg0, bool safepoint_pc) { 70 int r_tgt = CallHelperSetup(helper_offset); 71 OpRegCopy(TargetReg(kArg0), arg0); 72 ClobberCallerSave(); 73 CallHelper(r_tgt, helper_offset, safepoint_pc); 74} 75 76void Mir2Lir::CallRuntimeHelperRegLocation(ThreadOffset helper_offset, RegLocation arg0, 77 bool safepoint_pc) { 78 int r_tgt = CallHelperSetup(helper_offset); 79 if (arg0.wide == 0) { 80 LoadValueDirectFixed(arg0, TargetReg(kArg0)); 81 } else { 82 LoadValueDirectWideFixed(arg0, TargetReg(kArg0), TargetReg(kArg1)); 83 } 84 ClobberCallerSave(); 85 CallHelper(r_tgt, helper_offset, safepoint_pc); 86} 87 88void Mir2Lir::CallRuntimeHelperImmImm(ThreadOffset helper_offset, int arg0, int arg1, 89 bool safepoint_pc) { 90 int r_tgt = CallHelperSetup(helper_offset); 91 LoadConstant(TargetReg(kArg0), arg0); 92 LoadConstant(TargetReg(kArg1), arg1); 93 ClobberCallerSave(); 94 CallHelper(r_tgt, helper_offset, safepoint_pc); 95} 96 97void Mir2Lir::CallRuntimeHelperImmRegLocation(ThreadOffset helper_offset, int arg0, 98 RegLocation arg1, bool safepoint_pc) { 99 int r_tgt = CallHelperSetup(helper_offset); 100 if (arg1.wide == 0) { 101 LoadValueDirectFixed(arg1, TargetReg(kArg1)); 102 } else { 103 LoadValueDirectWideFixed(arg1, TargetReg(kArg1), TargetReg(kArg2)); 104 } 105 LoadConstant(TargetReg(kArg0), arg0); 106 ClobberCallerSave(); 107 CallHelper(r_tgt, helper_offset, safepoint_pc); 108} 109 110void Mir2Lir::CallRuntimeHelperRegLocationImm(ThreadOffset helper_offset, RegLocation arg0, int arg1, 111 bool safepoint_pc) { 112 int r_tgt = CallHelperSetup(helper_offset); 113 LoadValueDirectFixed(arg0, TargetReg(kArg0)); 114 LoadConstant(TargetReg(kArg1), arg1); 115 ClobberCallerSave(); 116 CallHelper(r_tgt, helper_offset, safepoint_pc); 117} 118 119void Mir2Lir::CallRuntimeHelperImmReg(ThreadOffset helper_offset, int arg0, int arg1, 120 bool safepoint_pc) { 121 int r_tgt = CallHelperSetup(helper_offset); 122 OpRegCopy(TargetReg(kArg1), arg1); 123 LoadConstant(TargetReg(kArg0), arg0); 124 ClobberCallerSave(); 125 CallHelper(r_tgt, helper_offset, safepoint_pc); 126} 127 128void Mir2Lir::CallRuntimeHelperRegImm(ThreadOffset helper_offset, int arg0, int arg1, 129 bool safepoint_pc) { 130 int r_tgt = CallHelperSetup(helper_offset); 131 OpRegCopy(TargetReg(kArg0), arg0); 132 LoadConstant(TargetReg(kArg1), arg1); 133 ClobberCallerSave(); 134 CallHelper(r_tgt, helper_offset, safepoint_pc); 135} 136 137void Mir2Lir::CallRuntimeHelperImmMethod(ThreadOffset helper_offset, int arg0, bool safepoint_pc) { 138 int r_tgt = CallHelperSetup(helper_offset); 139 LoadCurrMethodDirect(TargetReg(kArg1)); 140 LoadConstant(TargetReg(kArg0), arg0); 141 ClobberCallerSave(); 142 CallHelper(r_tgt, helper_offset, safepoint_pc); 143} 144 145void Mir2Lir::CallRuntimeHelperRegLocationRegLocation(ThreadOffset helper_offset, RegLocation arg0, 146 RegLocation arg1, bool safepoint_pc) { 147 int r_tgt = CallHelperSetup(helper_offset); 148 if (arg0.wide == 0) { 149 LoadValueDirectFixed(arg0, arg0.fp ? TargetReg(kFArg0) : TargetReg(kArg0)); 150 if (arg1.wide == 0) { 151 if (cu_->instruction_set == kMips) { 152 LoadValueDirectFixed(arg1, arg1.fp ? TargetReg(kFArg2) : TargetReg(kArg1)); 153 } else { 154 LoadValueDirectFixed(arg1, TargetReg(kArg1)); 155 } 156 } else { 157 if (cu_->instruction_set == kMips) { 158 LoadValueDirectWideFixed(arg1, arg1.fp ? TargetReg(kFArg2) : TargetReg(kArg1), arg1.fp ? TargetReg(kFArg3) : TargetReg(kArg2)); 159 } else { 160 LoadValueDirectWideFixed(arg1, TargetReg(kArg1), TargetReg(kArg2)); 161 } 162 } 163 } else { 164 LoadValueDirectWideFixed(arg0, arg0.fp ? TargetReg(kFArg0) : TargetReg(kArg0), arg0.fp ? TargetReg(kFArg1) : TargetReg(kArg1)); 165 if (arg1.wide == 0) { 166 LoadValueDirectFixed(arg1, arg1.fp ? TargetReg(kFArg2) : TargetReg(kArg2)); 167 } else { 168 LoadValueDirectWideFixed(arg1, arg1.fp ? TargetReg(kFArg2) : TargetReg(kArg2), arg1.fp ? TargetReg(kFArg3) : TargetReg(kArg3)); 169 } 170 } 171 ClobberCallerSave(); 172 CallHelper(r_tgt, helper_offset, safepoint_pc); 173} 174 175void Mir2Lir::CallRuntimeHelperRegReg(ThreadOffset helper_offset, int arg0, int arg1, 176 bool safepoint_pc) { 177 int r_tgt = CallHelperSetup(helper_offset); 178 DCHECK_NE(TargetReg(kArg0), arg1); // check copy into arg0 won't clobber arg1 179 OpRegCopy(TargetReg(kArg0), arg0); 180 OpRegCopy(TargetReg(kArg1), arg1); 181 ClobberCallerSave(); 182 CallHelper(r_tgt, helper_offset, safepoint_pc); 183} 184 185void Mir2Lir::CallRuntimeHelperRegRegImm(ThreadOffset helper_offset, int arg0, int arg1, 186 int arg2, bool safepoint_pc) { 187 int r_tgt = CallHelperSetup(helper_offset); 188 DCHECK_NE(TargetReg(kArg0), arg1); // check copy into arg0 won't clobber arg1 189 OpRegCopy(TargetReg(kArg0), arg0); 190 OpRegCopy(TargetReg(kArg1), arg1); 191 LoadConstant(TargetReg(kArg2), arg2); 192 ClobberCallerSave(); 193 CallHelper(r_tgt, helper_offset, safepoint_pc); 194} 195 196void Mir2Lir::CallRuntimeHelperImmMethodRegLocation(ThreadOffset helper_offset, 197 int arg0, RegLocation arg2, bool safepoint_pc) { 198 int r_tgt = CallHelperSetup(helper_offset); 199 LoadValueDirectFixed(arg2, TargetReg(kArg2)); 200 LoadCurrMethodDirect(TargetReg(kArg1)); 201 LoadConstant(TargetReg(kArg0), arg0); 202 ClobberCallerSave(); 203 CallHelper(r_tgt, helper_offset, safepoint_pc); 204} 205 206void Mir2Lir::CallRuntimeHelperImmMethodImm(ThreadOffset helper_offset, int arg0, 207 int arg2, bool safepoint_pc) { 208 int r_tgt = CallHelperSetup(helper_offset); 209 LoadCurrMethodDirect(TargetReg(kArg1)); 210 LoadConstant(TargetReg(kArg2), arg2); 211 LoadConstant(TargetReg(kArg0), arg0); 212 ClobberCallerSave(); 213 CallHelper(r_tgt, helper_offset, safepoint_pc); 214} 215 216void Mir2Lir::CallRuntimeHelperImmRegLocationRegLocation(ThreadOffset helper_offset, 217 int arg0, RegLocation arg1, 218 RegLocation arg2, bool safepoint_pc) { 219 int r_tgt = CallHelperSetup(helper_offset); 220 DCHECK_EQ(arg1.wide, 0U); 221 LoadValueDirectFixed(arg1, TargetReg(kArg1)); 222 if (arg2.wide == 0) { 223 LoadValueDirectFixed(arg2, TargetReg(kArg2)); 224 } else { 225 LoadValueDirectWideFixed(arg2, TargetReg(kArg2), TargetReg(kArg3)); 226 } 227 LoadConstant(TargetReg(kArg0), arg0); 228 ClobberCallerSave(); 229 CallHelper(r_tgt, helper_offset, safepoint_pc); 230} 231 232void Mir2Lir::CallRuntimeHelperRegLocationRegLocationRegLocation(ThreadOffset helper_offset, 233 RegLocation arg0, RegLocation arg1, 234 RegLocation arg2, 235 bool safepoint_pc) { 236 int r_tgt = CallHelperSetup(helper_offset); 237 DCHECK_EQ(arg0.wide, 0U); 238 LoadValueDirectFixed(arg0, TargetReg(kArg0)); 239 DCHECK_EQ(arg1.wide, 0U); 240 LoadValueDirectFixed(arg1, TargetReg(kArg1)); 241 DCHECK_EQ(arg1.wide, 0U); 242 LoadValueDirectFixed(arg2, TargetReg(kArg2)); 243 ClobberCallerSave(); 244 CallHelper(r_tgt, helper_offset, safepoint_pc); 245} 246 247/* 248 * If there are any ins passed in registers that have not been promoted 249 * to a callee-save register, flush them to the frame. Perform intial 250 * assignment of promoted arguments. 251 * 252 * ArgLocs is an array of location records describing the incoming arguments 253 * with one location record per word of argument. 254 */ 255void Mir2Lir::FlushIns(RegLocation* ArgLocs, RegLocation rl_method) { 256 /* 257 * Dummy up a RegLocation for the incoming Method* 258 * It will attempt to keep kArg0 live (or copy it to home location 259 * if promoted). 260 */ 261 RegLocation rl_src = rl_method; 262 rl_src.location = kLocPhysReg; 263 rl_src.low_reg = TargetReg(kArg0); 264 rl_src.home = false; 265 MarkLive(rl_src.low_reg, rl_src.s_reg_low); 266 StoreValue(rl_method, rl_src); 267 // If Method* has been promoted, explicitly flush 268 if (rl_method.location == kLocPhysReg) { 269 StoreWordDisp(TargetReg(kSp), 0, TargetReg(kArg0)); 270 } 271 272 if (cu_->num_ins == 0) 273 return; 274 const int num_arg_regs = 3; 275 static SpecialTargetRegister arg_regs[] = {kArg1, kArg2, kArg3}; 276 int start_vreg = cu_->num_dalvik_registers - cu_->num_ins; 277 /* 278 * Copy incoming arguments to their proper home locations. 279 * NOTE: an older version of dx had an issue in which 280 * it would reuse static method argument registers. 281 * This could result in the same Dalvik virtual register 282 * being promoted to both core and fp regs. To account for this, 283 * we only copy to the corresponding promoted physical register 284 * if it matches the type of the SSA name for the incoming 285 * argument. It is also possible that long and double arguments 286 * end up half-promoted. In those cases, we must flush the promoted 287 * half to memory as well. 288 */ 289 for (int i = 0; i < cu_->num_ins; i++) { 290 PromotionMap* v_map = &promotion_map_[start_vreg + i]; 291 if (i < num_arg_regs) { 292 // If arriving in register 293 bool need_flush = true; 294 RegLocation* t_loc = &ArgLocs[i]; 295 if ((v_map->core_location == kLocPhysReg) && !t_loc->fp) { 296 OpRegCopy(v_map->core_reg, TargetReg(arg_regs[i])); 297 need_flush = false; 298 } else if ((v_map->fp_location == kLocPhysReg) && t_loc->fp) { 299 OpRegCopy(v_map->FpReg, TargetReg(arg_regs[i])); 300 need_flush = false; 301 } else { 302 need_flush = true; 303 } 304 305 // For wide args, force flush if not fully promoted 306 if (t_loc->wide) { 307 PromotionMap* p_map = v_map + (t_loc->high_word ? -1 : +1); 308 // Is only half promoted? 309 need_flush |= (p_map->core_location != v_map->core_location) || 310 (p_map->fp_location != v_map->fp_location); 311 if ((cu_->instruction_set == kThumb2) && t_loc->fp && !need_flush) { 312 /* 313 * In Arm, a double is represented as a pair of consecutive single float 314 * registers starting at an even number. It's possible that both Dalvik vRegs 315 * representing the incoming double were independently promoted as singles - but 316 * not in a form usable as a double. If so, we need to flush - even though the 317 * incoming arg appears fully in register. At this point in the code, both 318 * halves of the double are promoted. Make sure they are in a usable form. 319 */ 320 int lowreg_index = start_vreg + i + (t_loc->high_word ? -1 : 0); 321 int low_reg = promotion_map_[lowreg_index].FpReg; 322 int high_reg = promotion_map_[lowreg_index + 1].FpReg; 323 if (((low_reg & 0x1) != 0) || (high_reg != (low_reg + 1))) { 324 need_flush = true; 325 } 326 } 327 } 328 if (need_flush) { 329 StoreBaseDisp(TargetReg(kSp), SRegOffset(start_vreg + i), 330 TargetReg(arg_regs[i]), kWord); 331 } 332 } else { 333 // If arriving in frame & promoted 334 if (v_map->core_location == kLocPhysReg) { 335 LoadWordDisp(TargetReg(kSp), SRegOffset(start_vreg + i), 336 v_map->core_reg); 337 } 338 if (v_map->fp_location == kLocPhysReg) { 339 LoadWordDisp(TargetReg(kSp), SRegOffset(start_vreg + i), 340 v_map->FpReg); 341 } 342 } 343 } 344} 345 346/* 347 * Bit of a hack here - in the absence of a real scheduling pass, 348 * emit the next instruction in static & direct invoke sequences. 349 */ 350static int NextSDCallInsn(CompilationUnit* cu, CallInfo* info, 351 int state, const MethodReference& target_method, 352 uint32_t unused, 353 uintptr_t direct_code, uintptr_t direct_method, 354 InvokeType type) { 355 Mir2Lir* cg = static_cast<Mir2Lir*>(cu->cg.get()); 356 if (direct_code != 0 && direct_method != 0) { 357 switch (state) { 358 case 0: // Get the current Method* [sets kArg0] 359 if (direct_code != static_cast<unsigned int>(-1)) { 360 if (cu->instruction_set != kX86) { 361 cg->LoadConstant(cg->TargetReg(kInvokeTgt), direct_code); 362 } 363 } else { 364 CHECK_EQ(cu->dex_file, target_method.dex_file); 365 LIR* data_target = cg->ScanLiteralPool(cg->code_literal_list_, 366 target_method.dex_method_index, 0); 367 if (data_target == NULL) { 368 data_target = cg->AddWordData(&cg->code_literal_list_, target_method.dex_method_index); 369 data_target->operands[1] = type; 370 } 371 LIR* load_pc_rel = cg->OpPcRelLoad(cg->TargetReg(kInvokeTgt), data_target); 372 cg->AppendLIR(load_pc_rel); 373 DCHECK_EQ(cu->instruction_set, kThumb2) << reinterpret_cast<void*>(data_target); 374 } 375 if (direct_method != static_cast<unsigned int>(-1)) { 376 cg->LoadConstant(cg->TargetReg(kArg0), direct_method); 377 } else { 378 CHECK_EQ(cu->dex_file, target_method.dex_file); 379 LIR* data_target = cg->ScanLiteralPool(cg->method_literal_list_, 380 target_method.dex_method_index, 0); 381 if (data_target == NULL) { 382 data_target = cg->AddWordData(&cg->method_literal_list_, target_method.dex_method_index); 383 data_target->operands[1] = type; 384 } 385 LIR* load_pc_rel = cg->OpPcRelLoad(cg->TargetReg(kArg0), data_target); 386 cg->AppendLIR(load_pc_rel); 387 DCHECK_EQ(cu->instruction_set, kThumb2) << reinterpret_cast<void*>(data_target); 388 } 389 break; 390 default: 391 return -1; 392 } 393 } else { 394 switch (state) { 395 case 0: // Get the current Method* [sets kArg0] 396 // TUNING: we can save a reg copy if Method* has been promoted. 397 cg->LoadCurrMethodDirect(cg->TargetReg(kArg0)); 398 break; 399 case 1: // Get method->dex_cache_resolved_methods_ 400 cg->LoadWordDisp(cg->TargetReg(kArg0), 401 mirror::ArtMethod::DexCacheResolvedMethodsOffset().Int32Value(), cg->TargetReg(kArg0)); 402 // Set up direct code if known. 403 if (direct_code != 0) { 404 if (direct_code != static_cast<unsigned int>(-1)) { 405 cg->LoadConstant(cg->TargetReg(kInvokeTgt), direct_code); 406 } else { 407 CHECK_EQ(cu->dex_file, target_method.dex_file); 408 CHECK_LT(target_method.dex_method_index, target_method.dex_file->NumMethodIds()); 409 LIR* data_target = cg->ScanLiteralPool(cg->code_literal_list_, 410 target_method.dex_method_index, 0); 411 if (data_target == NULL) { 412 data_target = cg->AddWordData(&cg->code_literal_list_, target_method.dex_method_index); 413 data_target->operands[1] = type; 414 } 415 LIR* load_pc_rel = cg->OpPcRelLoad(cg->TargetReg(kInvokeTgt), data_target); 416 cg->AppendLIR(load_pc_rel); 417 DCHECK_EQ(cu->instruction_set, kThumb2) << reinterpret_cast<void*>(data_target); 418 } 419 } 420 break; 421 case 2: // Grab target method* 422 CHECK_EQ(cu->dex_file, target_method.dex_file); 423 cg->LoadWordDisp(cg->TargetReg(kArg0), 424 mirror::Array::DataOffset(sizeof(mirror::Object*)).Int32Value() + 425 (target_method.dex_method_index * 4), 426 cg-> TargetReg(kArg0)); 427 break; 428 case 3: // Grab the code from the method* 429 if (cu->instruction_set != kX86) { 430 if (direct_code == 0) { 431 cg->LoadWordDisp(cg->TargetReg(kArg0), 432 mirror::ArtMethod::GetEntryPointFromCompiledCodeOffset().Int32Value(), 433 cg->TargetReg(kInvokeTgt)); 434 } 435 break; 436 } 437 // Intentional fallthrough for x86 438 default: 439 return -1; 440 } 441 } 442 return state + 1; 443} 444 445/* 446 * Bit of a hack here - in the absence of a real scheduling pass, 447 * emit the next instruction in a virtual invoke sequence. 448 * We can use kLr as a temp prior to target address loading 449 * Note also that we'll load the first argument ("this") into 450 * kArg1 here rather than the standard LoadArgRegs. 451 */ 452static int NextVCallInsn(CompilationUnit* cu, CallInfo* info, 453 int state, const MethodReference& target_method, 454 uint32_t method_idx, uintptr_t unused, uintptr_t unused2, 455 InvokeType unused3) { 456 Mir2Lir* cg = static_cast<Mir2Lir*>(cu->cg.get()); 457 /* 458 * This is the fast path in which the target virtual method is 459 * fully resolved at compile time. 460 */ 461 switch (state) { 462 case 0: { // Get "this" [set kArg1] 463 RegLocation rl_arg = info->args[0]; 464 cg->LoadValueDirectFixed(rl_arg, cg->TargetReg(kArg1)); 465 break; 466 } 467 case 1: // Is "this" null? [use kArg1] 468 cg->GenNullCheck(info->args[0].s_reg_low, cg->TargetReg(kArg1), info->opt_flags); 469 // get this->klass_ [use kArg1, set kInvokeTgt] 470 cg->LoadWordDisp(cg->TargetReg(kArg1), mirror::Object::ClassOffset().Int32Value(), 471 cg->TargetReg(kInvokeTgt)); 472 break; 473 case 2: // Get this->klass_->vtable [usr kInvokeTgt, set kInvokeTgt] 474 cg->LoadWordDisp(cg->TargetReg(kInvokeTgt), mirror::Class::VTableOffset().Int32Value(), 475 cg->TargetReg(kInvokeTgt)); 476 break; 477 case 3: // Get target method [use kInvokeTgt, set kArg0] 478 cg->LoadWordDisp(cg->TargetReg(kInvokeTgt), (method_idx * 4) + 479 mirror::Array::DataOffset(sizeof(mirror::Object*)).Int32Value(), 480 cg->TargetReg(kArg0)); 481 break; 482 case 4: // Get the compiled code address [uses kArg0, sets kInvokeTgt] 483 if (cu->instruction_set != kX86) { 484 cg->LoadWordDisp(cg->TargetReg(kArg0), 485 mirror::ArtMethod::GetEntryPointFromCompiledCodeOffset().Int32Value(), 486 cg->TargetReg(kInvokeTgt)); 487 break; 488 } 489 // Intentional fallthrough for X86 490 default: 491 return -1; 492 } 493 return state + 1; 494} 495 496/* 497 * Emit the next instruction in an invoke interface sequence. This will do a lookup in the 498 * class's IMT, calling either the actual method or art_quick_imt_conflict_trampoline if 499 * more than one interface method map to the same index. Note also that we'll load the first 500 * argument ("this") into kArg1 here rather than the standard LoadArgRegs. 501 */ 502static int NextInterfaceCallInsn(CompilationUnit* cu, CallInfo* info, int state, 503 const MethodReference& target_method, 504 uint32_t method_idx, uintptr_t unused, 505 uintptr_t direct_method, InvokeType unused2) { 506 Mir2Lir* cg = static_cast<Mir2Lir*>(cu->cg.get()); 507 508 switch (state) { 509 case 0: // Set target method index in case of conflict [set kHiddenArg, kHiddenFpArg (x86)] 510 CHECK_EQ(cu->dex_file, target_method.dex_file); 511 CHECK_LT(target_method.dex_method_index, target_method.dex_file->NumMethodIds()); 512 cg->LoadConstant(cg->TargetReg(kHiddenArg), target_method.dex_method_index); 513 if (cu->instruction_set == kX86) { 514 cg->OpRegCopy(cg->TargetReg(kHiddenFpArg), cg->TargetReg(kHiddenArg)); 515 } 516 break; 517 case 1: { // Get "this" [set kArg1] 518 RegLocation rl_arg = info->args[0]; 519 cg->LoadValueDirectFixed(rl_arg, cg->TargetReg(kArg1)); 520 break; 521 } 522 case 2: // Is "this" null? [use kArg1] 523 cg->GenNullCheck(info->args[0].s_reg_low, cg->TargetReg(kArg1), info->opt_flags); 524 // Get this->klass_ [use kArg1, set kInvokeTgt] 525 cg->LoadWordDisp(cg->TargetReg(kArg1), mirror::Object::ClassOffset().Int32Value(), 526 cg->TargetReg(kInvokeTgt)); 527 break; 528 case 3: // Get this->klass_->imtable [use kInvokeTgt, set kInvokeTgt] 529 cg->LoadWordDisp(cg->TargetReg(kInvokeTgt), mirror::Class::ImTableOffset().Int32Value(), 530 cg->TargetReg(kInvokeTgt)); 531 break; 532 case 4: // Get target method [use kInvokeTgt, set kArg0] 533 cg->LoadWordDisp(cg->TargetReg(kInvokeTgt), ((method_idx % ClassLinker::kImtSize) * 4) + 534 mirror::Array::DataOffset(sizeof(mirror::Object*)).Int32Value(), 535 cg->TargetReg(kArg0)); 536 break; 537 case 5: // Get the compiled code address [use kArg0, set kInvokeTgt] 538 if (cu->instruction_set != kX86) { 539 cg->LoadWordDisp(cg->TargetReg(kArg0), 540 mirror::ArtMethod::GetEntryPointFromCompiledCodeOffset().Int32Value(), 541 cg->TargetReg(kInvokeTgt)); 542 break; 543 } 544 // Intentional fallthrough for X86 545 default: 546 return -1; 547 } 548 return state + 1; 549} 550 551static int NextInvokeInsnSP(CompilationUnit* cu, CallInfo* info, ThreadOffset trampoline, 552 int state, const MethodReference& target_method, 553 uint32_t method_idx) { 554 Mir2Lir* cg = static_cast<Mir2Lir*>(cu->cg.get()); 555 /* 556 * This handles the case in which the base method is not fully 557 * resolved at compile time, we bail to a runtime helper. 558 */ 559 if (state == 0) { 560 if (cu->instruction_set != kX86) { 561 // Load trampoline target 562 cg->LoadWordDisp(cg->TargetReg(kSelf), trampoline.Int32Value(), cg->TargetReg(kInvokeTgt)); 563 } 564 // Load kArg0 with method index 565 CHECK_EQ(cu->dex_file, target_method.dex_file); 566 cg->LoadConstant(cg->TargetReg(kArg0), target_method.dex_method_index); 567 return 1; 568 } 569 return -1; 570} 571 572static int NextStaticCallInsnSP(CompilationUnit* cu, CallInfo* info, 573 int state, 574 const MethodReference& target_method, 575 uint32_t method_idx, 576 uintptr_t unused, uintptr_t unused2, 577 InvokeType unused3) { 578 ThreadOffset trampoline = QUICK_ENTRYPOINT_OFFSET(pInvokeStaticTrampolineWithAccessCheck); 579 return NextInvokeInsnSP(cu, info, trampoline, state, target_method, 0); 580} 581 582static int NextDirectCallInsnSP(CompilationUnit* cu, CallInfo* info, int state, 583 const MethodReference& target_method, 584 uint32_t method_idx, uintptr_t unused, 585 uintptr_t unused2, InvokeType unused3) { 586 ThreadOffset trampoline = QUICK_ENTRYPOINT_OFFSET(pInvokeDirectTrampolineWithAccessCheck); 587 return NextInvokeInsnSP(cu, info, trampoline, state, target_method, 0); 588} 589 590static int NextSuperCallInsnSP(CompilationUnit* cu, CallInfo* info, int state, 591 const MethodReference& target_method, 592 uint32_t method_idx, uintptr_t unused, 593 uintptr_t unused2, InvokeType unused3) { 594 ThreadOffset trampoline = QUICK_ENTRYPOINT_OFFSET(pInvokeSuperTrampolineWithAccessCheck); 595 return NextInvokeInsnSP(cu, info, trampoline, state, target_method, 0); 596} 597 598static int NextVCallInsnSP(CompilationUnit* cu, CallInfo* info, int state, 599 const MethodReference& target_method, 600 uint32_t method_idx, uintptr_t unused, 601 uintptr_t unused2, InvokeType unused3) { 602 ThreadOffset trampoline = QUICK_ENTRYPOINT_OFFSET(pInvokeVirtualTrampolineWithAccessCheck); 603 return NextInvokeInsnSP(cu, info, trampoline, state, target_method, 0); 604} 605 606static int NextInterfaceCallInsnWithAccessCheck(CompilationUnit* cu, 607 CallInfo* info, int state, 608 const MethodReference& target_method, 609 uint32_t unused, 610 uintptr_t unused2, uintptr_t unused3, 611 InvokeType unused4) { 612 ThreadOffset trampoline = QUICK_ENTRYPOINT_OFFSET(pInvokeInterfaceTrampolineWithAccessCheck); 613 return NextInvokeInsnSP(cu, info, trampoline, state, target_method, 0); 614} 615 616int Mir2Lir::LoadArgRegs(CallInfo* info, int call_state, 617 NextCallInsn next_call_insn, 618 const MethodReference& target_method, 619 uint32_t vtable_idx, uintptr_t direct_code, 620 uintptr_t direct_method, InvokeType type, bool skip_this) { 621 int last_arg_reg = TargetReg(kArg3); 622 int next_reg = TargetReg(kArg1); 623 int next_arg = 0; 624 if (skip_this) { 625 next_reg++; 626 next_arg++; 627 } 628 for (; (next_reg <= last_arg_reg) && (next_arg < info->num_arg_words); next_reg++) { 629 RegLocation rl_arg = info->args[next_arg++]; 630 rl_arg = UpdateRawLoc(rl_arg); 631 if (rl_arg.wide && (next_reg <= TargetReg(kArg2))) { 632 LoadValueDirectWideFixed(rl_arg, next_reg, next_reg + 1); 633 next_reg++; 634 next_arg++; 635 } else { 636 if (rl_arg.wide) { 637 rl_arg.wide = false; 638 rl_arg.is_const = false; 639 } 640 LoadValueDirectFixed(rl_arg, next_reg); 641 } 642 call_state = next_call_insn(cu_, info, call_state, target_method, vtable_idx, 643 direct_code, direct_method, type); 644 } 645 return call_state; 646} 647 648/* 649 * Load up to 5 arguments, the first three of which will be in 650 * kArg1 .. kArg3. On entry kArg0 contains the current method pointer, 651 * and as part of the load sequence, it must be replaced with 652 * the target method pointer. Note, this may also be called 653 * for "range" variants if the number of arguments is 5 or fewer. 654 */ 655int Mir2Lir::GenDalvikArgsNoRange(CallInfo* info, 656 int call_state, LIR** pcrLabel, NextCallInsn next_call_insn, 657 const MethodReference& target_method, 658 uint32_t vtable_idx, uintptr_t direct_code, 659 uintptr_t direct_method, InvokeType type, bool skip_this) { 660 RegLocation rl_arg; 661 662 /* If no arguments, just return */ 663 if (info->num_arg_words == 0) 664 return call_state; 665 666 call_state = next_call_insn(cu_, info, call_state, target_method, vtable_idx, 667 direct_code, direct_method, type); 668 669 DCHECK_LE(info->num_arg_words, 5); 670 if (info->num_arg_words > 3) { 671 int32_t next_use = 3; 672 // Detect special case of wide arg spanning arg3/arg4 673 RegLocation rl_use0 = info->args[0]; 674 RegLocation rl_use1 = info->args[1]; 675 RegLocation rl_use2 = info->args[2]; 676 if (((!rl_use0.wide && !rl_use1.wide) || rl_use0.wide) && 677 rl_use2.wide) { 678 int reg = -1; 679 // Wide spans, we need the 2nd half of uses[2]. 680 rl_arg = UpdateLocWide(rl_use2); 681 if (rl_arg.location == kLocPhysReg) { 682 reg = rl_arg.high_reg; 683 } else { 684 // kArg2 & rArg3 can safely be used here 685 reg = TargetReg(kArg3); 686 LoadWordDisp(TargetReg(kSp), SRegOffset(rl_arg.s_reg_low) + 4, reg); 687 call_state = next_call_insn(cu_, info, call_state, target_method, 688 vtable_idx, direct_code, direct_method, type); 689 } 690 StoreBaseDisp(TargetReg(kSp), (next_use + 1) * 4, reg, kWord); 691 StoreBaseDisp(TargetReg(kSp), 16 /* (3+1)*4 */, reg, kWord); 692 call_state = next_call_insn(cu_, info, call_state, target_method, vtable_idx, 693 direct_code, direct_method, type); 694 next_use++; 695 } 696 // Loop through the rest 697 while (next_use < info->num_arg_words) { 698 int low_reg; 699 int high_reg = -1; 700 rl_arg = info->args[next_use]; 701 rl_arg = UpdateRawLoc(rl_arg); 702 if (rl_arg.location == kLocPhysReg) { 703 low_reg = rl_arg.low_reg; 704 high_reg = rl_arg.high_reg; 705 } else { 706 low_reg = TargetReg(kArg2); 707 if (rl_arg.wide) { 708 high_reg = TargetReg(kArg3); 709 LoadValueDirectWideFixed(rl_arg, low_reg, high_reg); 710 } else { 711 LoadValueDirectFixed(rl_arg, low_reg); 712 } 713 call_state = next_call_insn(cu_, info, call_state, target_method, 714 vtable_idx, direct_code, direct_method, type); 715 } 716 int outs_offset = (next_use + 1) * 4; 717 if (rl_arg.wide) { 718 StoreBaseDispWide(TargetReg(kSp), outs_offset, low_reg, high_reg); 719 next_use += 2; 720 } else { 721 StoreWordDisp(TargetReg(kSp), outs_offset, low_reg); 722 next_use++; 723 } 724 call_state = next_call_insn(cu_, info, call_state, target_method, vtable_idx, 725 direct_code, direct_method, type); 726 } 727 } 728 729 call_state = LoadArgRegs(info, call_state, next_call_insn, 730 target_method, vtable_idx, direct_code, direct_method, 731 type, skip_this); 732 733 if (pcrLabel) { 734 *pcrLabel = GenNullCheck(info->args[0].s_reg_low, TargetReg(kArg1), info->opt_flags); 735 } 736 return call_state; 737} 738 739/* 740 * May have 0+ arguments (also used for jumbo). Note that 741 * source virtual registers may be in physical registers, so may 742 * need to be flushed to home location before copying. This 743 * applies to arg3 and above (see below). 744 * 745 * Two general strategies: 746 * If < 20 arguments 747 * Pass args 3-18 using vldm/vstm block copy 748 * Pass arg0, arg1 & arg2 in kArg1-kArg3 749 * If 20+ arguments 750 * Pass args arg19+ using memcpy block copy 751 * Pass arg0, arg1 & arg2 in kArg1-kArg3 752 * 753 */ 754int Mir2Lir::GenDalvikArgsRange(CallInfo* info, int call_state, 755 LIR** pcrLabel, NextCallInsn next_call_insn, 756 const MethodReference& target_method, 757 uint32_t vtable_idx, uintptr_t direct_code, uintptr_t direct_method, 758 InvokeType type, bool skip_this) { 759 // If we can treat it as non-range (Jumbo ops will use range form) 760 if (info->num_arg_words <= 5) 761 return GenDalvikArgsNoRange(info, call_state, pcrLabel, 762 next_call_insn, target_method, vtable_idx, 763 direct_code, direct_method, type, skip_this); 764 /* 765 * First load the non-register arguments. Both forms expect all 766 * of the source arguments to be in their home frame location, so 767 * scan the s_reg names and flush any that have been promoted to 768 * frame backing storage. 769 */ 770 // Scan the rest of the args - if in phys_reg flush to memory 771 for (int next_arg = 0; next_arg < info->num_arg_words;) { 772 RegLocation loc = info->args[next_arg]; 773 if (loc.wide) { 774 loc = UpdateLocWide(loc); 775 if ((next_arg >= 2) && (loc.location == kLocPhysReg)) { 776 StoreBaseDispWide(TargetReg(kSp), SRegOffset(loc.s_reg_low), 777 loc.low_reg, loc.high_reg); 778 } 779 next_arg += 2; 780 } else { 781 loc = UpdateLoc(loc); 782 if ((next_arg >= 3) && (loc.location == kLocPhysReg)) { 783 StoreBaseDisp(TargetReg(kSp), SRegOffset(loc.s_reg_low), 784 loc.low_reg, kWord); 785 } 786 next_arg++; 787 } 788 } 789 790 int start_offset = SRegOffset(info->args[3].s_reg_low); 791 int outs_offset = 4 /* Method* */ + (3 * 4); 792 if (cu_->instruction_set != kThumb2) { 793 // Generate memcpy 794 OpRegRegImm(kOpAdd, TargetReg(kArg0), TargetReg(kSp), outs_offset); 795 OpRegRegImm(kOpAdd, TargetReg(kArg1), TargetReg(kSp), start_offset); 796 CallRuntimeHelperRegRegImm(QUICK_ENTRYPOINT_OFFSET(pMemcpy), TargetReg(kArg0), 797 TargetReg(kArg1), (info->num_arg_words - 3) * 4, false); 798 } else { 799 if (info->num_arg_words >= 20) { 800 // Generate memcpy 801 OpRegRegImm(kOpAdd, TargetReg(kArg0), TargetReg(kSp), outs_offset); 802 OpRegRegImm(kOpAdd, TargetReg(kArg1), TargetReg(kSp), start_offset); 803 CallRuntimeHelperRegRegImm(QUICK_ENTRYPOINT_OFFSET(pMemcpy), TargetReg(kArg0), 804 TargetReg(kArg1), (info->num_arg_words - 3) * 4, false); 805 } else { 806 // Use vldm/vstm pair using kArg3 as a temp 807 int regs_left = std::min(info->num_arg_words - 3, 16); 808 call_state = next_call_insn(cu_, info, call_state, target_method, vtable_idx, 809 direct_code, direct_method, type); 810 OpRegRegImm(kOpAdd, TargetReg(kArg3), TargetReg(kSp), start_offset); 811 LIR* ld = OpVldm(TargetReg(kArg3), regs_left); 812 // TUNING: loosen barrier 813 ld->u.m.def_mask = ENCODE_ALL; 814 SetMemRefType(ld, true /* is_load */, kDalvikReg); 815 call_state = next_call_insn(cu_, info, call_state, target_method, vtable_idx, 816 direct_code, direct_method, type); 817 OpRegRegImm(kOpAdd, TargetReg(kArg3), TargetReg(kSp), 4 /* Method* */ + (3 * 4)); 818 call_state = next_call_insn(cu_, info, call_state, target_method, vtable_idx, 819 direct_code, direct_method, type); 820 LIR* st = OpVstm(TargetReg(kArg3), regs_left); 821 SetMemRefType(st, false /* is_load */, kDalvikReg); 822 st->u.m.def_mask = ENCODE_ALL; 823 call_state = next_call_insn(cu_, info, call_state, target_method, vtable_idx, 824 direct_code, direct_method, type); 825 } 826 } 827 828 call_state = LoadArgRegs(info, call_state, next_call_insn, 829 target_method, vtable_idx, direct_code, direct_method, 830 type, skip_this); 831 832 call_state = next_call_insn(cu_, info, call_state, target_method, vtable_idx, 833 direct_code, direct_method, type); 834 if (pcrLabel) { 835 *pcrLabel = GenNullCheck(info->args[0].s_reg_low, TargetReg(kArg1), info->opt_flags); 836 } 837 return call_state; 838} 839 840RegLocation Mir2Lir::InlineTarget(CallInfo* info) { 841 RegLocation res; 842 if (info->result.location == kLocInvalid) { 843 res = GetReturn(false); 844 } else { 845 res = info->result; 846 } 847 return res; 848} 849 850RegLocation Mir2Lir::InlineTargetWide(CallInfo* info) { 851 RegLocation res; 852 if (info->result.location == kLocInvalid) { 853 res = GetReturnWide(false); 854 } else { 855 res = info->result; 856 } 857 return res; 858} 859 860bool Mir2Lir::GenInlinedCharAt(CallInfo* info) { 861 if (cu_->instruction_set == kMips) { 862 // TODO - add Mips implementation 863 return false; 864 } 865 // Location of reference to data array 866 int value_offset = mirror::String::ValueOffset().Int32Value(); 867 // Location of count 868 int count_offset = mirror::String::CountOffset().Int32Value(); 869 // Starting offset within data array 870 int offset_offset = mirror::String::OffsetOffset().Int32Value(); 871 // Start of char data with array_ 872 int data_offset = mirror::Array::DataOffset(sizeof(uint16_t)).Int32Value(); 873 874 RegLocation rl_obj = info->args[0]; 875 RegLocation rl_idx = info->args[1]; 876 rl_obj = LoadValue(rl_obj, kCoreReg); 877 rl_idx = LoadValue(rl_idx, kCoreReg); 878 int reg_max; 879 GenNullCheck(rl_obj.s_reg_low, rl_obj.low_reg, info->opt_flags); 880 bool range_check = (!(info->opt_flags & MIR_IGNORE_RANGE_CHECK)); 881 LIR* launch_pad = NULL; 882 int reg_off = INVALID_REG; 883 int reg_ptr = INVALID_REG; 884 if (cu_->instruction_set != kX86) { 885 reg_off = AllocTemp(); 886 reg_ptr = AllocTemp(); 887 if (range_check) { 888 reg_max = AllocTemp(); 889 LoadWordDisp(rl_obj.low_reg, count_offset, reg_max); 890 } 891 LoadWordDisp(rl_obj.low_reg, offset_offset, reg_off); 892 LoadWordDisp(rl_obj.low_reg, value_offset, reg_ptr); 893 if (range_check) { 894 // Set up a launch pad to allow retry in case of bounds violation */ 895 launch_pad = RawLIR(0, kPseudoIntrinsicRetry, WrapPointer(info)); 896 intrinsic_launchpads_.Insert(launch_pad); 897 OpRegReg(kOpCmp, rl_idx.low_reg, reg_max); 898 FreeTemp(reg_max); 899 OpCondBranch(kCondCs, launch_pad); 900 } 901 } else { 902 if (range_check) { 903 reg_max = AllocTemp(); 904 LoadWordDisp(rl_obj.low_reg, count_offset, reg_max); 905 // Set up a launch pad to allow retry in case of bounds violation */ 906 launch_pad = RawLIR(0, kPseudoIntrinsicRetry, WrapPointer(info)); 907 intrinsic_launchpads_.Insert(launch_pad); 908 OpRegReg(kOpCmp, rl_idx.low_reg, reg_max); 909 FreeTemp(reg_max); 910 OpCondBranch(kCondCc, launch_pad); 911 } 912 reg_off = AllocTemp(); 913 reg_ptr = AllocTemp(); 914 LoadWordDisp(rl_obj.low_reg, offset_offset, reg_off); 915 LoadWordDisp(rl_obj.low_reg, value_offset, reg_ptr); 916 } 917 OpRegImm(kOpAdd, reg_ptr, data_offset); 918 OpRegReg(kOpAdd, reg_off, rl_idx.low_reg); 919 FreeTemp(rl_obj.low_reg); 920 FreeTemp(rl_idx.low_reg); 921 RegLocation rl_dest = InlineTarget(info); 922 RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); 923 LoadBaseIndexed(reg_ptr, reg_off, rl_result.low_reg, 1, kUnsignedHalf); 924 FreeTemp(reg_off); 925 FreeTemp(reg_ptr); 926 StoreValue(rl_dest, rl_result); 927 if (range_check) { 928 launch_pad->operands[2] = 0; // no resumption 929 } 930 // Record that we've already inlined & null checked 931 info->opt_flags |= (MIR_INLINED | MIR_IGNORE_NULL_CHECK); 932 return true; 933} 934 935// Generates an inlined String.is_empty or String.length. 936bool Mir2Lir::GenInlinedStringIsEmptyOrLength(CallInfo* info, bool is_empty) { 937 if (cu_->instruction_set == kMips) { 938 // TODO - add Mips implementation 939 return false; 940 } 941 // dst = src.length(); 942 RegLocation rl_obj = info->args[0]; 943 rl_obj = LoadValue(rl_obj, kCoreReg); 944 RegLocation rl_dest = InlineTarget(info); 945 RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); 946 GenNullCheck(rl_obj.s_reg_low, rl_obj.low_reg, info->opt_flags); 947 LoadWordDisp(rl_obj.low_reg, mirror::String::CountOffset().Int32Value(), rl_result.low_reg); 948 if (is_empty) { 949 // dst = (dst == 0); 950 if (cu_->instruction_set == kThumb2) { 951 int t_reg = AllocTemp(); 952 OpRegReg(kOpNeg, t_reg, rl_result.low_reg); 953 OpRegRegReg(kOpAdc, rl_result.low_reg, rl_result.low_reg, t_reg); 954 } else { 955 DCHECK_EQ(cu_->instruction_set, kX86); 956 OpRegImm(kOpSub, rl_result.low_reg, 1); 957 OpRegImm(kOpLsr, rl_result.low_reg, 31); 958 } 959 } 960 StoreValue(rl_dest, rl_result); 961 return true; 962} 963 964bool Mir2Lir::GenInlinedReverseBytes(CallInfo* info, OpSize size) { 965 if (cu_->instruction_set == kMips) { 966 // TODO - add Mips implementation 967 return false; 968 } 969 RegLocation rl_src_i = info->args[0]; 970 RegLocation rl_dest = InlineTarget(info); // result reg 971 RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); 972 if (size == kLong) { 973 RegLocation rl_i = LoadValueWide(rl_src_i, kCoreReg); 974 int r_i_low = rl_i.low_reg; 975 if (rl_i.low_reg == rl_result.low_reg) { 976 // First REV shall clobber rl_result.low_reg, save the value in a temp for the second REV. 977 r_i_low = AllocTemp(); 978 OpRegCopy(r_i_low, rl_i.low_reg); 979 } 980 OpRegReg(kOpRev, rl_result.low_reg, rl_i.high_reg); 981 OpRegReg(kOpRev, rl_result.high_reg, r_i_low); 982 if (rl_i.low_reg == rl_result.low_reg) { 983 FreeTemp(r_i_low); 984 } 985 StoreValueWide(rl_dest, rl_result); 986 } else { 987 DCHECK(size == kWord || size == kSignedHalf); 988 OpKind op = (size == kWord) ? kOpRev : kOpRevsh; 989 RegLocation rl_i = LoadValue(rl_src_i, kCoreReg); 990 OpRegReg(op, rl_result.low_reg, rl_i.low_reg); 991 StoreValue(rl_dest, rl_result); 992 } 993 return true; 994} 995 996bool Mir2Lir::GenInlinedAbsInt(CallInfo* info) { 997 if (cu_->instruction_set == kMips) { 998 // TODO - add Mips implementation 999 return false; 1000 } 1001 RegLocation rl_src = info->args[0]; 1002 rl_src = LoadValue(rl_src, kCoreReg); 1003 RegLocation rl_dest = InlineTarget(info); 1004 RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); 1005 int sign_reg = AllocTemp(); 1006 // abs(x) = y<=x>>31, (x+y)^y. 1007 OpRegRegImm(kOpAsr, sign_reg, rl_src.low_reg, 31); 1008 OpRegRegReg(kOpAdd, rl_result.low_reg, rl_src.low_reg, sign_reg); 1009 OpRegReg(kOpXor, rl_result.low_reg, sign_reg); 1010 StoreValue(rl_dest, rl_result); 1011 return true; 1012} 1013 1014bool Mir2Lir::GenInlinedAbsLong(CallInfo* info) { 1015 if (cu_->instruction_set == kMips) { 1016 // TODO - add Mips implementation 1017 return false; 1018 } 1019 if (cu_->instruction_set == kThumb2) { 1020 RegLocation rl_src = info->args[0]; 1021 rl_src = LoadValueWide(rl_src, kCoreReg); 1022 RegLocation rl_dest = InlineTargetWide(info); 1023 RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); 1024 int sign_reg = AllocTemp(); 1025 // abs(x) = y<=x>>31, (x+y)^y. 1026 OpRegRegImm(kOpAsr, sign_reg, rl_src.high_reg, 31); 1027 OpRegRegReg(kOpAdd, rl_result.low_reg, rl_src.low_reg, sign_reg); 1028 OpRegRegReg(kOpAdc, rl_result.high_reg, rl_src.high_reg, sign_reg); 1029 OpRegReg(kOpXor, rl_result.low_reg, sign_reg); 1030 OpRegReg(kOpXor, rl_result.high_reg, sign_reg); 1031 StoreValueWide(rl_dest, rl_result); 1032 return true; 1033 } else { 1034 DCHECK_EQ(cu_->instruction_set, kX86); 1035 // Reuse source registers to avoid running out of temps 1036 RegLocation rl_src = info->args[0]; 1037 rl_src = LoadValueWide(rl_src, kCoreReg); 1038 RegLocation rl_dest = InlineTargetWide(info); 1039 RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); 1040 OpRegCopyWide(rl_result.low_reg, rl_result.high_reg, rl_src.low_reg, rl_src.high_reg); 1041 FreeTemp(rl_src.low_reg); 1042 FreeTemp(rl_src.high_reg); 1043 int sign_reg = AllocTemp(); 1044 // abs(x) = y<=x>>31, (x+y)^y. 1045 OpRegRegImm(kOpAsr, sign_reg, rl_result.high_reg, 31); 1046 OpRegReg(kOpAdd, rl_result.low_reg, sign_reg); 1047 OpRegReg(kOpAdc, rl_result.high_reg, sign_reg); 1048 OpRegReg(kOpXor, rl_result.low_reg, sign_reg); 1049 OpRegReg(kOpXor, rl_result.high_reg, sign_reg); 1050 StoreValueWide(rl_dest, rl_result); 1051 return true; 1052 } 1053} 1054 1055bool Mir2Lir::GenInlinedFloatCvt(CallInfo* info) { 1056 if (cu_->instruction_set == kMips) { 1057 // TODO - add Mips implementation 1058 return false; 1059 } 1060 RegLocation rl_src = info->args[0]; 1061 RegLocation rl_dest = InlineTarget(info); 1062 StoreValue(rl_dest, rl_src); 1063 return true; 1064} 1065 1066bool Mir2Lir::GenInlinedDoubleCvt(CallInfo* info) { 1067 if (cu_->instruction_set == kMips) { 1068 // TODO - add Mips implementation 1069 return false; 1070 } 1071 RegLocation rl_src = info->args[0]; 1072 RegLocation rl_dest = InlineTargetWide(info); 1073 StoreValueWide(rl_dest, rl_src); 1074 return true; 1075} 1076 1077/* 1078 * Fast string.index_of(I) & (II). Tests for simple case of char <= 0xffff, 1079 * otherwise bails to standard library code. 1080 */ 1081bool Mir2Lir::GenInlinedIndexOf(CallInfo* info, bool zero_based) { 1082 if (cu_->instruction_set == kMips) { 1083 // TODO - add Mips implementation 1084 return false; 1085 } 1086 ClobberCallerSave(); 1087 LockCallTemps(); // Using fixed registers 1088 int reg_ptr = TargetReg(kArg0); 1089 int reg_char = TargetReg(kArg1); 1090 int reg_start = TargetReg(kArg2); 1091 1092 RegLocation rl_obj = info->args[0]; 1093 RegLocation rl_char = info->args[1]; 1094 RegLocation rl_start = info->args[2]; 1095 LoadValueDirectFixed(rl_obj, reg_ptr); 1096 LoadValueDirectFixed(rl_char, reg_char); 1097 if (zero_based) { 1098 LoadConstant(reg_start, 0); 1099 } else { 1100 LoadValueDirectFixed(rl_start, reg_start); 1101 } 1102 int r_tgt = (cu_->instruction_set != kX86) ? LoadHelper(QUICK_ENTRYPOINT_OFFSET(pIndexOf)) : 0; 1103 GenNullCheck(rl_obj.s_reg_low, reg_ptr, info->opt_flags); 1104 LIR* launch_pad = RawLIR(0, kPseudoIntrinsicRetry, WrapPointer(info)); 1105 intrinsic_launchpads_.Insert(launch_pad); 1106 OpCmpImmBranch(kCondGt, reg_char, 0xFFFF, launch_pad); 1107 // NOTE: not a safepoint 1108 if (cu_->instruction_set != kX86) { 1109 OpReg(kOpBlx, r_tgt); 1110 } else { 1111 OpThreadMem(kOpBlx, QUICK_ENTRYPOINT_OFFSET(pIndexOf)); 1112 } 1113 LIR* resume_tgt = NewLIR0(kPseudoTargetLabel); 1114 launch_pad->operands[2] = WrapPointer(resume_tgt); 1115 // Record that we've already inlined & null checked 1116 info->opt_flags |= (MIR_INLINED | MIR_IGNORE_NULL_CHECK); 1117 RegLocation rl_return = GetReturn(false); 1118 RegLocation rl_dest = InlineTarget(info); 1119 StoreValue(rl_dest, rl_return); 1120 return true; 1121} 1122 1123/* Fast string.compareTo(Ljava/lang/string;)I. */ 1124bool Mir2Lir::GenInlinedStringCompareTo(CallInfo* info) { 1125 if (cu_->instruction_set == kMips) { 1126 // TODO - add Mips implementation 1127 return false; 1128 } 1129 ClobberCallerSave(); 1130 LockCallTemps(); // Using fixed registers 1131 int reg_this = TargetReg(kArg0); 1132 int reg_cmp = TargetReg(kArg1); 1133 1134 RegLocation rl_this = info->args[0]; 1135 RegLocation rl_cmp = info->args[1]; 1136 LoadValueDirectFixed(rl_this, reg_this); 1137 LoadValueDirectFixed(rl_cmp, reg_cmp); 1138 int r_tgt = (cu_->instruction_set != kX86) ? 1139 LoadHelper(QUICK_ENTRYPOINT_OFFSET(pStringCompareTo)) : 0; 1140 GenNullCheck(rl_this.s_reg_low, reg_this, info->opt_flags); 1141 // TUNING: check if rl_cmp.s_reg_low is already null checked 1142 LIR* launch_pad = RawLIR(0, kPseudoIntrinsicRetry, WrapPointer(info)); 1143 intrinsic_launchpads_.Insert(launch_pad); 1144 OpCmpImmBranch(kCondEq, reg_cmp, 0, launch_pad); 1145 // NOTE: not a safepoint 1146 if (cu_->instruction_set != kX86) { 1147 OpReg(kOpBlx, r_tgt); 1148 } else { 1149 OpThreadMem(kOpBlx, QUICK_ENTRYPOINT_OFFSET(pStringCompareTo)); 1150 } 1151 launch_pad->operands[2] = 0; // No return possible 1152 // Record that we've already inlined & null checked 1153 info->opt_flags |= (MIR_INLINED | MIR_IGNORE_NULL_CHECK); 1154 RegLocation rl_return = GetReturn(false); 1155 RegLocation rl_dest = InlineTarget(info); 1156 StoreValue(rl_dest, rl_return); 1157 return true; 1158} 1159 1160bool Mir2Lir::GenInlinedCurrentThread(CallInfo* info) { 1161 RegLocation rl_dest = InlineTarget(info); 1162 RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); 1163 ThreadOffset offset = Thread::PeerOffset(); 1164 if (cu_->instruction_set == kThumb2 || cu_->instruction_set == kMips) { 1165 LoadWordDisp(TargetReg(kSelf), offset.Int32Value(), rl_result.low_reg); 1166 } else { 1167 CHECK(cu_->instruction_set == kX86); 1168 reinterpret_cast<X86Mir2Lir*>(this)->OpRegThreadMem(kOpMov, rl_result.low_reg, offset); 1169 } 1170 StoreValue(rl_dest, rl_result); 1171 return true; 1172} 1173 1174bool Mir2Lir::GenInlinedUnsafeGet(CallInfo* info, 1175 bool is_long, bool is_volatile) { 1176 if (cu_->instruction_set == kMips) { 1177 // TODO - add Mips implementation 1178 return false; 1179 } 1180 // Unused - RegLocation rl_src_unsafe = info->args[0]; 1181 RegLocation rl_src_obj = info->args[1]; // Object 1182 RegLocation rl_src_offset = info->args[2]; // long low 1183 rl_src_offset.wide = 0; // ignore high half in info->args[3] 1184 RegLocation rl_dest = InlineTarget(info); // result reg 1185 if (is_volatile) { 1186 GenMemBarrier(kLoadLoad); 1187 } 1188 RegLocation rl_object = LoadValue(rl_src_obj, kCoreReg); 1189 RegLocation rl_offset = LoadValue(rl_src_offset, kCoreReg); 1190 RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); 1191 if (is_long) { 1192 OpRegReg(kOpAdd, rl_object.low_reg, rl_offset.low_reg); 1193 LoadBaseDispWide(rl_object.low_reg, 0, rl_result.low_reg, rl_result.high_reg, INVALID_SREG); 1194 StoreValueWide(rl_dest, rl_result); 1195 } else { 1196 LoadBaseIndexed(rl_object.low_reg, rl_offset.low_reg, rl_result.low_reg, 0, kWord); 1197 StoreValue(rl_dest, rl_result); 1198 } 1199 return true; 1200} 1201 1202bool Mir2Lir::GenInlinedUnsafePut(CallInfo* info, bool is_long, 1203 bool is_object, bool is_volatile, bool is_ordered) { 1204 if (cu_->instruction_set == kMips) { 1205 // TODO - add Mips implementation 1206 return false; 1207 } 1208 if (cu_->instruction_set == kX86 && is_object) { 1209 // TODO: fix X86, it exhausts registers for card marking. 1210 return false; 1211 } 1212 // Unused - RegLocation rl_src_unsafe = info->args[0]; 1213 RegLocation rl_src_obj = info->args[1]; // Object 1214 RegLocation rl_src_offset = info->args[2]; // long low 1215 rl_src_offset.wide = 0; // ignore high half in info->args[3] 1216 RegLocation rl_src_value = info->args[4]; // value to store 1217 if (is_volatile || is_ordered) { 1218 GenMemBarrier(kStoreStore); 1219 } 1220 RegLocation rl_object = LoadValue(rl_src_obj, kCoreReg); 1221 RegLocation rl_offset = LoadValue(rl_src_offset, kCoreReg); 1222 RegLocation rl_value; 1223 if (is_long) { 1224 rl_value = LoadValueWide(rl_src_value, kCoreReg); 1225 OpRegReg(kOpAdd, rl_object.low_reg, rl_offset.low_reg); 1226 StoreBaseDispWide(rl_object.low_reg, 0, rl_value.low_reg, rl_value.high_reg); 1227 } else { 1228 rl_value = LoadValue(rl_src_value, kCoreReg); 1229 StoreBaseIndexed(rl_object.low_reg, rl_offset.low_reg, rl_value.low_reg, 0, kWord); 1230 } 1231 if (is_volatile) { 1232 GenMemBarrier(kStoreLoad); 1233 } 1234 if (is_object) { 1235 MarkGCCard(rl_value.low_reg, rl_object.low_reg); 1236 } 1237 return true; 1238} 1239 1240void Mir2Lir::GenInvoke(CallInfo* info) { 1241 if (!(info->opt_flags & MIR_INLINED)) { 1242 if (inliner_ == nullptr) { 1243 QuickCompilerContext* context = reinterpret_cast<QuickCompilerContext*>( 1244 cu_->compiler_driver->GetCompilerContext()); 1245 inliner_ = &context->GetInlinerMap()->GetMethodInliner(cu_->dex_file); 1246 } 1247 if (inliner_->GenIntrinsic(this, info)) { 1248 return; 1249 } 1250 } 1251 InvokeType original_type = info->type; // avoiding mutation by ComputeInvokeInfo 1252 int call_state = 0; 1253 LIR* null_ck; 1254 LIR** p_null_ck = NULL; 1255 NextCallInsn next_call_insn; 1256 FlushAllRegs(); /* Everything to home location */ 1257 // Explicit register usage 1258 LockCallTemps(); 1259 1260 DexCompilationUnit* cUnit = mir_graph_->GetCurrentDexCompilationUnit(); 1261 MethodReference target_method(cUnit->GetDexFile(), info->index); 1262 int vtable_idx; 1263 uintptr_t direct_code; 1264 uintptr_t direct_method; 1265 bool skip_this; 1266 bool fast_path = 1267 cu_->compiler_driver->ComputeInvokeInfo(mir_graph_->GetCurrentDexCompilationUnit(), 1268 current_dalvik_offset_, 1269 true, true, 1270 &info->type, &target_method, 1271 &vtable_idx, 1272 &direct_code, &direct_method) && !SLOW_INVOKE_PATH; 1273 if (info->type == kInterface) { 1274 next_call_insn = fast_path ? NextInterfaceCallInsn : NextInterfaceCallInsnWithAccessCheck; 1275 skip_this = fast_path; 1276 } else if (info->type == kDirect) { 1277 if (fast_path) { 1278 p_null_ck = &null_ck; 1279 } 1280 next_call_insn = fast_path ? NextSDCallInsn : NextDirectCallInsnSP; 1281 skip_this = false; 1282 } else if (info->type == kStatic) { 1283 next_call_insn = fast_path ? NextSDCallInsn : NextStaticCallInsnSP; 1284 skip_this = false; 1285 } else if (info->type == kSuper) { 1286 DCHECK(!fast_path); // Fast path is a direct call. 1287 next_call_insn = NextSuperCallInsnSP; 1288 skip_this = false; 1289 } else { 1290 DCHECK_EQ(info->type, kVirtual); 1291 next_call_insn = fast_path ? NextVCallInsn : NextVCallInsnSP; 1292 skip_this = fast_path; 1293 } 1294 if (!info->is_range) { 1295 call_state = GenDalvikArgsNoRange(info, call_state, p_null_ck, 1296 next_call_insn, target_method, 1297 vtable_idx, direct_code, direct_method, 1298 original_type, skip_this); 1299 } else { 1300 call_state = GenDalvikArgsRange(info, call_state, p_null_ck, 1301 next_call_insn, target_method, vtable_idx, 1302 direct_code, direct_method, original_type, 1303 skip_this); 1304 } 1305 // Finish up any of the call sequence not interleaved in arg loading 1306 while (call_state >= 0) { 1307 call_state = next_call_insn(cu_, info, call_state, target_method, 1308 vtable_idx, direct_code, direct_method, 1309 original_type); 1310 } 1311 LIR* call_inst; 1312 if (cu_->instruction_set != kX86) { 1313 call_inst = OpReg(kOpBlx, TargetReg(kInvokeTgt)); 1314 } else { 1315 if (fast_path) { 1316 call_inst = OpMem(kOpBlx, TargetReg(kArg0), 1317 mirror::ArtMethod::GetEntryPointFromCompiledCodeOffset().Int32Value()); 1318 } else { 1319 ThreadOffset trampoline(-1); 1320 switch (info->type) { 1321 case kInterface: 1322 trampoline = QUICK_ENTRYPOINT_OFFSET(pInvokeInterfaceTrampolineWithAccessCheck); 1323 break; 1324 case kDirect: 1325 trampoline = QUICK_ENTRYPOINT_OFFSET(pInvokeDirectTrampolineWithAccessCheck); 1326 break; 1327 case kStatic: 1328 trampoline = QUICK_ENTRYPOINT_OFFSET(pInvokeStaticTrampolineWithAccessCheck); 1329 break; 1330 case kSuper: 1331 trampoline = QUICK_ENTRYPOINT_OFFSET(pInvokeSuperTrampolineWithAccessCheck); 1332 break; 1333 case kVirtual: 1334 trampoline = QUICK_ENTRYPOINT_OFFSET(pInvokeVirtualTrampolineWithAccessCheck); 1335 break; 1336 default: 1337 LOG(FATAL) << "Unexpected invoke type"; 1338 } 1339 call_inst = OpThreadMem(kOpBlx, trampoline); 1340 } 1341 } 1342 MarkSafepointPC(call_inst); 1343 1344 ClobberCallerSave(); 1345 if (info->result.location != kLocInvalid) { 1346 // We have a following MOVE_RESULT - do it now. 1347 if (info->result.wide) { 1348 RegLocation ret_loc = GetReturnWide(info->result.fp); 1349 StoreValueWide(info->result, ret_loc); 1350 } else { 1351 RegLocation ret_loc = GetReturn(info->result.fp); 1352 StoreValue(info->result, ret_loc); 1353 } 1354 } 1355} 1356 1357} // namespace art 1358