| 3d21bdf8894e780d349c481e5c9e29fe1556051c |
|
22-Apr-2015 |
Mathieu Chartier <mathieuc@google.com> |
Move mirror::ArtMethod to native
Optimizing + quick tests are passing, devices boot.
TODO: Test and fix bugs in mips64.
Saves 16 bytes per most ArtMethod, 7.5MB reduction in system PSS.
Some of the savings are from removal of virtual methods and direct
methods object arrays.
Bug: 19264997
(cherry picked from commit e401d146407d61eeb99f8d6176b2ac13c4df1e33)
Change-Id: I622469a0cfa0e7082a2119f3d6a9491eb61e3f3d
Fix some ArtMethod related bugs
Added root visiting for runtime methods, not currently required
since the GcRoots in these methods are null.
Added missing GetInterfaceMethodIfProxy in GetMethodLine, fixes
--trace run-tests 005, 044.
Fixed optimizing compiler bug where we used a normal stack location
instead of double on ARM64, this fixes the debuggable tests.
TODO: Fix JDWP tests.
Bug: 19264997
Change-Id: I7c55f69c61d1b45351fd0dc7185ffe5efad82bd3
ART: Fix casts for 64-bit pointers on 32-bit compiler.
Bug: 19264997
Change-Id: Ief45cdd4bae5a43fc8bfdfa7cf744e2c57529457
Fix JDWP tests after ArtMethod change
Fixes Throwable::GetStackDepth for exception event detection after
internal stack trace representation change.
Adds missing ArtMethod::GetInterfaceMethodIfProxy call in case of
proxy method.
Bug: 19264997
Change-Id: I363e293796848c3ec491c963813f62d868da44d2
Fix accidental IMT and root marking regression
Was always using the conflict trampoline. Also included fix for
regression in GC time caused by extra roots. Most of the regression
was IMT.
Fixed bug in DumpGcPerformanceInfo where we would get SIGABRT due to
detached thread.
EvaluateAndApplyChanges:
From ~2500 -> ~1980
GC time: 8.2s -> 7.2s due to 1s less of MarkConcurrentRoots
Bug: 19264997
Change-Id: I4333e80a8268c2ed1284f87f25b9f113d4f2c7e0
Fix bogus image test assert
Previously we were comparing the size of the non moving space to
size of the image file.
Now we properly compare the size of the image space against the size
of the image file.
Bug: 19264997
Change-Id: I7359f1f73ae3df60c5147245935a24431c04808a
[MIPS64] Fix art_quick_invoke_stub argument offsets.
ArtMethod reference's size got bigger, so we need to move other args
and leave enough space for ArtMethod* and 'this' pointer.
This fixes mips64 boot.
Bug: 19264997
Change-Id: I47198d5f39a4caab30b3b77479d5eedaad5006ab
|
| 848f70a3d73833fc1bf3032a9ff6812e429661d9 |
|
15-Jan-2014 |
Jeff Hao <jeffhao@google.com> |
Replace String CharArray with internal uint16_t array.
Summary of high level changes:
- Adds compiler inliner support to identify string init methods
- Adds compiler support (quick & optimizing) with new invoke code path
that calls method off the thread pointer
- Adds thread entrypoints for all string init methods
- Adds map to verifier to log when receiver of string init has been
copied to other registers. used by compiler and interpreter
Change-Id: I797b992a8feb566f9ad73060011ab6f51eb7ce01
|
| fac10700fd99516e8a14f751fe35553021ce6982 |
|
22-Apr-2015 |
Vladimir Marko <vmarko@google.com> |
Quick: Remove broken Mir2Lir::LocToRegClass().
Its use in intrinsics has been bogus. In all other instances
it's been used under the assumption that the inferred type
matches the return type of associated calls. However, if the
type inference identifies a type mismatch, the assumption
doesn't hold and there isn't necessarily a valid value that
the function could reasonably return.
Bug: 19918641
Change-Id: I050934e6f9eb00427d0b888ee29ae9eeb509bb3f
|
| 87b7c52ac660119b8dea46967974b76c86d0750b |
|
08-Apr-2015 |
Vladimir Marko <vmarko@google.com> |
Quick: Clean up temp use counting.
For the boot image on arm64 and x86-64 we're using true
PC-relative addressing, so pc_rel_temp_ is nullptr and
CanUsePcRelDexCacheArrayLoad() returns true, but we're not
actually using the ArtMethod* so fix the AnalyzeMIR() to
take it into account.
Also don't count intrinsic invokes towards ArtMethod* uses.
To avoid repeated method inliner inquiries about whether a
method is intrinsic or special (requiring lock acquisition),
cache that information in MirMethodLoweringInfo. As part of
that cleanup, take quickened invokes into account for
suspend check elimination.
Change-Id: I5b4ec124221c0db1314c8e72675976c110ebe7ca
|
| 20f85597828194c12be10d3a927999def066555e |
|
19-Mar-2015 |
Vladimir Marko <vmarko@google.com> |
Fixed layout for dex caches in boot image.
Define a fixed layout for dex cache arrays (type, method,
string and field arrays) for dex caches in the boot image.
This gives those arrays fixed offsets from the boot image
code and allows PC-relative addressing of their elements.
Use the PC-relative load on arm64 for relevant instructions,
i.e. invoke-static, invoke-direct, const-string,
const-class, check-cast and instance-of. This reduces the
arm64 boot.oat on Nexus 9 by 1.1MiB.
This CL provides the infrastructure and shows on the arm64
the gains that we can achieve by having fixed dex cache
arrays' layout. To fully use this for the boot images, we
need to implement the PC-relative addressing for other
architectures. To achieve similar gains for apps, we need
to move the dex cache arrays to a .bss section of the oat
file. These changes will be implemented in subsequent CLs.
(Also remove some compiler_driver.h dependencies to reduce
incremental build times.)
Change-Id: Ib1859fa4452d01d983fd92ae22b611f45a85d69b
|
| 0b40ecf156e309aa17c72a28cd1b0237dbfb8746 |
|
20-Mar-2015 |
Vladimir Marko <vmarko@google.com> |
Quick: Clean up slow paths.
Change-Id: I278d42be77b02778c4a419ae9024b37929915b64
|
| 6ea651f0f4c7de4580beb2e887d86802c1ae0738 |
|
24-Feb-2015 |
Maja Gagic <maja.gagic@imgtec.com> |
Initial support for quick compiler on MIPS64r6.
Change-Id: I6f43027b84e4a98ea320cddb972d9cf39bf7c4f8
|
| f58c11c92df59f7ec7d9f2dfadc7e400b790883d |
|
14-Feb-2015 |
Douglas Leung <douglas.leung@imgtec.com> |
Fix argument register allocation for mips32.
Change-Id: Ic21b0371d7cafb9b67217b92bb2edb735a43d1b0
|
| e5f13e57ff8fa36342beb33830b3ec5942a61cca |
|
24-Feb-2015 |
Mathieu Chartier <mathieuc@google.com> |
Revert "Revert "Add JIT""
Added missing EntryPointToCodePointer.
This reverts commit a5ca888d715cd0c6c421313211caa1928be3e399.
Change-Id: Ia74df0ef3a7babbdcb0466fd24da28e304e3f5af
|
| a5ca888d715cd0c6c421313211caa1928be3e399 |
|
24-Feb-2015 |
Nicolas Geoffray <ngeoffray@google.com> |
Revert "Add JIT"
Sorry, run-test crashes on target:
0-05 12:15:51.633 I/DEBUG (27995): Abort message: 'art/runtime/mirror/art_method.cc:349] Check failed: PcIsWithinQuickCode(reinterpret_cast<uintptr_t>(code), pc) java.lang.Throwable java.lang.Throwable.fillInStackTrace() pc=71e3366b code=0x71e3362d size=ad000000'
10-05 12:15:51.633 I/DEBUG (27995): r0 00000000 r1 0000542b r2 00000006 r3 00000000
10-05 12:15:51.633 I/DEBUG (27995): r4 00000006 r5 b6f9addc r6 00000002 r7 0000010c
10-05 12:15:51.633 I/DEBUG (27995): r8 b63fe1e8 r9 be8e1418 sl b6427400 fp b63fcce0
10-05 12:15:51.633 I/DEBUG (27995): ip 0000542b sp be8e1358 lr b6e9a27b pc b6e9c280 cpsr 40070010
10-05 12:15:51.633 I/DEBUG (27995):
Bug: 17950037
This reverts commit 2535abe7d1fcdd0e6aca782b1f1932a703ed50a4.
Change-Id: I6f88849bc6f2befed0c0aaa0b7b2a08c967a83c3
|
| 2535abe7d1fcdd0e6aca782b1f1932a703ed50a4 |
|
17-Feb-2015 |
Mathieu Chartier <mathieuc@google.com> |
Add JIT
Currently disabled by default unless -Xjit is passed in.
The proposed JIT is a method JIT which works by utilizing interpreter
instrumentation to request compilation of hot methods async during
runtime.
JIT options:
-Xjit / -Xnojit
-Xjitcodecachesize:N
-Xjitthreshold:integervalue
The JIT has a shared copy of a compiler driver which is accessed
by worker threads to compile individual methods.
Added JIT code cache and data cache, currently sized at 2 MB
capacity by default. Most apps will only fill a small fraction of
this cache however.
Added support to the compiler for compiling interpreter quickened
byte codes.
Added test target ART_TEST_JIT=TRUE and --jit for run-test.
TODO:
Clean up code cache.
Delete compiled methods after they are added to code cache.
Add more optimizations related to runtime checks e.g. direct pointers
for invokes.
Add method recompilation.
Move instrumentation to DexFile to improve performance and reduce
memory usage.
Bug: 17950037
Change-Id: Ifa5b2684a2d5059ec5a5210733900aafa3c51bca
|
| 6ce3eba0f2e6e505ed408cdc40d213c8a512238d |
|
16-Feb-2015 |
Vladimir Marko <vmarko@google.com> |
Add suspend checks to special methods.
Generate suspend checks at the beginning of special methods.
If we need to call to runtime, go to the slow path where we
create a simplified but valid frame, spill all arguments,
call art_quick_test_suspend, restore necessary arguments and
return back to the fast path. This keeps the fast path
overhead to a minimum.
Bug: 19245639
Change-Id: I3de5aee783943941322a49c4cf2c4c94411dbaa2
|
| 0b9203e7996ee1856f620f95d95d8a273c43a3df |
|
23-Jan-2015 |
Andreas Gampe <agampe@google.com> |
ART: Some Quick cleanup
Make several fields const in CompilationUnit. May benefit some Mir2Lir
code that repeats tests, and in general immutability is good.
Remove compiler_internals.h and refactor some other headers to reduce
overly broad imports (and thus forced recompiles on changes).
Change-Id: I898405907c68923581373b5981d8a85d2e5d185a
|
| ff87d7bdc2c06bece8ea783dd4979360f1d51103 |
|
20-Jan-2015 |
Chao-ying Fu <chao-ying.fu@intel.com> |
ART: Fix GenInlined functions
This patch fixes Mir2Lir::GenInlinedReverseBytes,
Mir2Lir::GenInlinedAbsInt, Mir2Lir::GenInlinedAbsLong,
Mir2Lir::GenInlinedFloatCvt, Mir2Lir::GenInlinedDoubleCvt,
X86Mir2Lir::GenInlinedSqrt, X86Mir2Lir::GenInlinedMinMaxFP,
X86Mir2Lir::GenInlinedMinMax, X86Mir2Lir::GenInlinedPeek,
and X86Mir2Lir::GenInlinedReverseBits to generate no code, when results
are unused.
New calls without assignments are added to 082-inline-execute.
Change-Id: I7076e9ddbea43545315f2aeb677c63a8a6e95224
Signed-off-by: Chao-ying Fu <chao-ying.fu@intel.com>
|
| f681570077563bb529a30f9e7c572b837cecfb83 |
|
20-Jan-2015 |
Andreas Gampe <agampe@google.com> |
ART: Make some helpers non-virtual in Mir2Lir
These don't need to be virtual.
Change-Id: Idca3c0a4e8b5e045d354974bd993492d6c0e70ba
|
| d500b53ff8742f76b63c9f7593082d9e8114b85f |
|
17-Jan-2015 |
Andreas Gampe <agampe@google.com> |
ART: Some Quick cleanup
Move some definitions around. In case a method is already virtual,
avoid instruction-set tests.
Change-Id: I8d98f098e55ade1bc0cfa32bb2aad006caccd07d
|
| 425f239c291d435f519a1cf4bdd9ccc9a2c0c070 |
|
08-Jan-2015 |
Nicolas Geoffray <ngeoffray@google.com> |
Fix handling of long argument spanning register/memory.
Comment in arm_lir.h says:
* If a 64-bit argument would span the register/memory argument
* boundary, it will instead be fully passed in the frame.
This change implements such logic for all platforms. We still need
to pass the low part in register as well because I haven't ported
the jni compilers (x86 and mips) to it.
Once the jni compilers are updated, we can remove the register
assignment.
Note that this greatly simplifies optimizing's register allocator
by not having to understand a long spanning register and memory.
Change-Id: I59706ca5d47269fc46e5489ac99bd6576e87e7f3
|
| 1cc7dbabd03e0a6c09d68161417a21bd6f9df371 |
|
18-Dec-2014 |
Andreas Gampe <agampe@google.com> |
ART: Reorder entrypoint argument order
Shuffle the ArtMethod* referrer backwards for easier removal.
Clean up ARM & MIPS assembly code.
Change some macros to make future changes easier.
Change-Id: Ie2862b68bd6e519438e83eecd9e1611df51d7945
|
| bfe400bb1a28cde991cdb3e39bc27bae6b04b8c2 |
|
19-Dec-2014 |
Vladimir Marko <vmarko@google.com> |
Fix running out of temps when storing invoke-interface result.
On ARM, after emitting invoke-interface we didn't have any
free temps to use for storing the result, so we would crash
if the result was an unpromoted dalvik register with stack
location too far from SP.
Bug: 18769895
(cherry picked from commit d6bd06c713e8ec69de96510ef57bdf7adb4781ed)
Change-Id: Id88f6f3788eaf6ecbc7bd68880b445423f6e4f94
|
| d6bd06c713e8ec69de96510ef57bdf7adb4781ed |
|
19-Dec-2014 |
Vladimir Marko <vmarko@google.com> |
Fix running out of temps when storing invoke-interface result.
On ARM, after emitting invoke-interface we didn't have any
free temps to use for storing the result, so we would crash
if the result was an unpromoted dalvik register with stack
location too far from SP.
Bug: 18769895
Change-Id: Ie6c131d68f1853a8317b305a22eab22faea80e90
|
| 717a3e447c6f7a922cf9c3efe522747a187a045d |
|
13-Nov-2014 |
Serguei Katkov <serguei.i.katkov@intel.com> |
Re-factor Quick ABI support
Now every architecture must provide a mapper between
VRs parameters and physical registers. Additionally as
a helper function architecture can provide a bulk copy
helper for GenDalvikArgs utility.
All other things becomes a common code stuff:
GetArgMappingToPhysicalReg, GenDalvikArgsNoRange,
GenDalvikArgsRange, FlushIns.
Mapper now uses shorty representation of input
parameters. This is required due to location are not
enough to detect the type of parameter (fp or core).
For the details
see https://android-review.googlesource.com/#/c/113936/.
Change-Id: Ie762b921e0acaa936518ee6b63c9a9d25f83e434
Signed-off-by: Serguei Katkov <serguei.i.katkov@intel.com>
|
| 743b98cd3d7db1cfd6b3d7f7795e8abd9d07a42d |
|
24-Nov-2014 |
Vladimir Marko <vmarko@google.com> |
Skip null check in MarkGCCard() for known non-null values.
Use GVN's knowledge of non-null values to set a new MIR flag
for IPUT/SPUT/APUT to skip the value null check.
Change-Id: I97a8d1447acb530c9bbbf7b362add366d1486ee1
|
| 2d7210188805292e463be4bcf7a133b654d7e0ea |
|
10-Nov-2014 |
Mathieu Chartier <mathieuc@google.com> |
Change 64 bit ArtMethod fields to be pointer sized
Changed the 64 bit entrypoint and gc map fields in ArtMethod to be
pointer sized. This saves a large amount of memory on 32 bit systems.
Reduces ArtMethod size by 16 bytes on 32 bit.
Total number of ArtMethod on low memory mako: 169957
Image size: 49203 methods -> 787248 image size reduction.
Zygote space size: 1070 methods -> 17120 size reduction.
App methods: ~120k -> 2 MB savings.
Savings per app on low memory mako: 125K+ per app
(less active apps -> more image methods per app).
Savings depend on how often the shared methods are on dirty pages vs
shared.
TODO in another CL, delete gc map field from ArtMethod since we
should be able to get it from the Oat method header.
Bug: 17643507
Change-Id: Ie9508f05907a9f693882d4d32a564460bf273ee8
(cherry picked from commit e832e64a7e82d7f72aedbd7d798fb929d458ee8f)
|
| e832e64a7e82d7f72aedbd7d798fb929d458ee8f |
|
10-Nov-2014 |
Mathieu Chartier <mathieuc@google.com> |
Change 64 bit ArtMethod fields to be pointer sized
Changed the 64 bit entrypoint and gc map fields in ArtMethod to be
pointer sized. This saves a large amount of memory on 32 bit systems.
Reduces ArtMethod size by 16 bytes on 32 bit.
Total number of ArtMethod on low memory mako: 169957
Image size: 49203 methods -> 787248 image size reduction.
Zygote space size: 1070 methods -> 17120 size reduction.
App methods: ~120k -> 2 MB savings.
Savings per app on low memory mako: 125K+ per app
(less active apps -> more image methods per app).
Savings depend on how often the shared methods are on dirty pages vs
shared.
TODO in another CL, delete gc map field from ArtMethod since we
should be able to get it from the Oat method header.
Bug: 17643507
Change-Id: Ie9508f05907a9f693882d4d32a564460bf273ee8
|
| 277ccbd200ea43590dfc06a93ae184a765327ad0 |
|
04-Nov-2014 |
Andreas Gampe <agampe@google.com> |
ART: More warnings
Enable -Wno-conversion-null, -Wredundant-decls and -Wshadow in general,
and -Wunused-but-set-parameter for GCC builds.
Change-Id: I81bbdd762213444673c65d85edae594a523836e5
|
| 6a3c1fcb4ba42ad4d5d142c17a3712a6ddd3866f |
|
31-Oct-2014 |
Ian Rogers <irogers@google.com> |
Remove -Wno-unused-parameter and -Wno-sign-promo from base cflags.
Fix associated errors about unused paramenters and implict sign conversions.
For sign conversion this was largely in the area of enums, so add ostream
operators for the effected enums and fix tools/generate-operator-out.py.
Tidy arena allocation code and arena allocated data types, rather than fixing
new and delete operators.
Remove dead code.
Change-Id: I5b433e722d2f75baacfacae4d32aef4a828bfe1b
|
| 5667fdbb6e441dee7534ade18b628ed396daf593 |
|
23-Oct-2014 |
Zheng Xu <zheng.xu@arm.com> |
ARM: Use hardfp calling convention between java to java call.
This patch default to use hardfp calling convention. Softfp can be enabled
by setting kArm32QuickCodeUseSoftFloat to true.
We get about -1 ~ +5% performance improvement with different benchmark
tests. Hopefully, we should be able to get more performance by address the left
TODOs, as some part of the code takes the original assumption which is not
optimal.
DONE:
1. Interpreter to quick code
2. Quick code to interpreter
3. Transition assembly and callee-saves
4. Trampoline(generic jni, resolution, invoke with access check and etc.)
5. Pass fp arg reg following aapcs(gpr and stack do not follow aapcs)
6. Quick helper assembly routines to handle ABI differences
7. Quick code method entry
8. Quick code method invocation
9. JNI compiler
TODO:
10. Rework ArgMap, FlushIn, GenDalvikArgs and affected common code.
11. Rework CallRuntimeHelperXXX().
Change-Id: I9965d8a007f4829f2560b63bcbbde271bdcf6ec2
|
| fc787ecd91127b2c8458afd94e5148e2ae51a1f5 |
|
10-Oct-2014 |
Ian Rogers <irogers@google.com> |
Enable -Wimplicit-fallthrough.
Falling through switch cases on a clang build must now annotate the fallthrough
with the FALLTHROUGH_INTENDED macro.
Bug: 17731372
Change-Id: I836451cd5f96b01d1ababdbf9eef677fe8fa8324
|
| 7c02e918e752ab36f0b6cab7528f10c0cf55a4ee |
|
03-Oct-2014 |
buzbee <buzbee@google.com> |
Quick compiler: Fix ambiguous LoadValue()
Internal b/17790197 & hat tip to Stephen Kyle
The following custom-edited dex program demonstrated
incorrect code generation caused by type confusion.
In the example, the constant held in v0 is used in both
float and int contexts, and the register class gets
confused at the if-eq.
.method private static getInt()I
.registers 4
const/16 v0, 100
const/4 v1, 1
const/4 v2, 7
:loop
if-eq v2, v0, :done
add-int v2, v2, v1
goto :loop
:done
add-float v3, v0, v1
return v2
.end method
The bug was introduced in c/96499, "Quick compiler: reference cleanup"
That CL created a convenience variant of LoadValue which selected the
target register type based on the type of the RegLocation. It should
not have done so. The type of a RegLocation is the compiler's best
guess of the Dalvik type - and Dalvik allows constants to be used
in multiple type contexts. All code generation utilities must specify
desired register class based on the capabilities of the instructions
to be emitted. In the failing case, OpCmpImmBranch (and
GenCompareZeroAndBranch) will be using core registers, so the
LoadValue must specify either kCoreReg or kRefReg.
The CL deletes the dangerous LoadValue() variant.
Change-Id: Ie4ec6e51b19676dbbb9628c72c8b3473a419e7ec
|
| 7c2ad5af0bdd3cc1069038f8e3422d99aeb5f44c |
|
24-Sep-2014 |
Vladimir Marko <vmarko@google.com> |
Implement method calls using relative BL on ARM64.
Change-Id: I9e5d0b6c100b6cddd6bbb7ab07cff77ab104ea31
|
| ff0ac4772d489d8780bbb6bb271dc6d5333cca7c |
|
02-Oct-2014 |
Vladimir Marko <vmarko@google.com> |
Remove all uses of MIR_INLINED.
They are not needed since
https://android-review.googlesource.com/103763
Change-Id: I1dffe5e219db615be9d9aaceb72ad9bd7c69b58e
|
| 02ff2d4187249d26fabe8e5eacc27b99984ee353 |
|
04-Sep-2014 |
Serguei Katkov <serguei.i.katkov@intel.com> |
AddIntrinsicSlowPath with resume requires clobbering
AddIntrinsicSlowPath with resume results in a call.
So all temps must be clobbered at the point where
AddIntrinsicSlowPath returns.
(cherry-picked from 9863daf4fdc1a08339edac794452dbc719aef4f1)
Change-Id: If9eb887e295ff5e59920f4da1cef63258ad490b0
Signed-off-by: Serguei Katkov <serguei.i.katkov@intel.com>
|
| f4da675bbc4615c5f854c81964cac9dd1153baea |
|
01-Aug-2014 |
Vladimir Marko <vmarko@google.com> |
Implement method calls using relative BL on ARM.
Store the linker patches with each CompiledMethod instead of
keeping them in CompilerDriver. Reorganize oat file creation
to apply the patches as we're writing the method code. Add
framework for platform-specific relative call patches in the
OatWriter. Implement relative call patches for ARM.
Change-Id: Ie2effb3d92b61ac8f356140eba09dc37d62290f8
|
| 9863daf4fdc1a08339edac794452dbc719aef4f1 |
|
04-Sep-2014 |
Serguei Katkov <serguei.i.katkov@intel.com> |
AddIntrinsicSlowPath with resume requires clobbering
AddIntrinsicSlowPath with resume results in a call.
So all temps must be clobbered at the point where
AddIntrinsicSlowPath returns.
Change-Id: If9eb887e295ff5e59920f4da1cef63258ad490b0
Signed-off-by: Serguei Katkov <serguei.i.katkov@intel.com>
|
| 4e67841e99e4a206133e7010653ccd132682296a |
|
09-Sep-2014 |
Mathieu Chartier <mathieuc@google.com> |
Change Reference.get() intrinsic to Reference.getReferent().
The reference intrinsic was incorrectly inlining
PhantomReference.get(). We now get around this by adding a
layer of indirection. Reference.get() now calls getReferent()
which is intrinsified and inlined.
Requires:
https://android-review.googlesource.com/#/c/107100/
Bug: 17429865
(cherry picked from commit cd48f2d86197d4fe87cc88077bc4af5ba66e5295)
Change-Id: Ie91e70abf43cedf3c707c7bb8a5059e19d2a2577
|
| cd48f2d86197d4fe87cc88077bc4af5ba66e5295 |
|
09-Sep-2014 |
Mathieu Chartier <mathieuc@google.com> |
Change Reference.get() intrinsic to Reference.getReferent().
The reference intrinsic was incorrectly inlining
PhantomReference.get(). We now get around this by adding a
layer of indirection. Reference.get() now calls getReferent()
which is intrinsified and inlined.
Requires:
https://android-review.googlesource.com/#/c/107100/
Bug: 17429865
Change-Id: Ie91e70abf43cedf3c707c7bb8a5059e19d2a2577
|
| 90a21f8e76028b9f89e91c436fc6fe9e9a354694 |
|
07-Sep-2014 |
buzbee <buzbee@google.com> |
Quick compiler: Fix handling of unused returns
As part of the inlining process, the quick compiler will attempt
to eliminate MOVE_RESULT instructions and deliver the result of
the inlined function directly to the eventual use.
The type of the returned value is determined by the subsequent
use (which had already been typed via the size and type
inference pass). However, if a method result is never used the code
just defaulted to assigning dummy core sink register[s]. This
caused a DCHECK failure on some 64-bit systems for methods returning
an unused reference (although the generated code was correct).
This CL selects sink registers for the unused return case based
on the type of the inlined method, and adds another DCHECK to
verify that the result of the size & type inference pass matches
with the inlined method's type.
Internal b/17328561
Change-Id: I9803ad604fe1bdcf9ff9a1d310cf022a7b6deae2
|
| 8d0d03e24325463f0060abfd05dba5598044e9b1 |
|
07-Jun-2014 |
Razvan A Lupusoru <razvan.a.lupusoru@intel.com> |
ART: Change temporaries to positive names
Changes compiler temporaries to have positive names. The numbering now
puts them above the code VRs (locals + ins, in that order). The patch also
introduces APIs to query the number of temporaries, locals and ins.
The compiler temp infrastructure suffered from several issues
which are also addressed by this patch:
-There is no longer a queue of compiler temps. This would be polluted
with Method* when post opts were called multiple times.
-Sanity checks have been added to allow requesting of temps from BE
and to prevent temps after frame is committed.
-None of the structures holding temps can overflow because they are
allocated to allow holding maximum temps. Thus temps can be requested
by BE with no problem.
-Since the queue of compiler temps is no longer maintained, it is no
longer possible to refer to a temp that has invalid ssa (because it
was requested before ssa was run).
-The BE can now request temps after all ME allocations and it is guaranteed
to actually receive them.
-ME temps are now treated like normal VRs in all cases with no special
handling. Only the BE temps are handled specially because there are no
references to them from MIRs.
-Deprecated and removed several fields in CompilationUnit that saved
register information and updated callsites to call the new interface from
MIRGraph.
Change-Id: Ia8b1fec9384a1a83017800a59e5b0498dfb2698c
Signed-off-by: Razvan A Lupusoru <razvan.a.lupusoru@intel.com>
Signed-off-by: Udayan Banerji <udayan.banerji@intel.com>
|
| 37f05ef45e0393de812d51261dc293240c17294d |
|
17-Jul-2014 |
Fred Shih <ffred@google.com> |
Reduced memory usage of primitive fields smaller than 4-bytes
Reduced memory used by byte and boolean fields from 4 bytes down to a
single byte and shorts and chars down to two bytes. Fields are now
arranged as Reference followed by decreasing component sizes, with
fields shuffled forward as needed.
Bug: 8135266
Change-Id: I65eaf31ed27e5bd5ba0c7d4606454b720b074752
|
| e7f82e2515f47f3c3292281312d7031a34a58ffc |
|
06-Aug-2014 |
Fred Shih <ffred@google.com> |
Added support for patching classes from different dex files.
Added support for class patching from different dex files and moved
ScopedObjectAccess from the quick compiler to driver. Slight refactoring
for clarity.
Bug: 16656190
Change-Id: I107fcbce75db42ca61321ea1c5d5f236680a1b3d
|
| b9dbab627bdc3570d5f41cfd6de80ff3b70e1783 |
|
06-Aug-2014 |
Fred Shih <ffred@google.com> |
Revert "Temporary fix for bad LIR generation in GenInlinedGet."
This reverts commit eb76e11d836ea953b4e40a28e3e69d3b0f4c86fa.
Bug: 16656190
Change-Id: Ie2dd58436b28e79214ef3a7c7651f16fe46a60e8
|
| eb76e11d836ea953b4e40a28e3e69d3b0f4c86fa |
|
30-Jul-2014 |
Alex Light <allight@google.com> |
Temporary fix for bad LIR generation in GenInlinedGet.
In GenInlinedGet we will sometimes try to load a class directly. If
we are doing that and find one, but cannot get the direct pointer
(due to image compilation or including patch information) we might
end up generating incorrect patching code due to the changing of the
cu_->dex_file attribute.
Bug: 16656190
Change-Id: I9bada598bf4fd972d6164163eedd4a496da306d6
|
| 6bbf0967d217ab2b7bdbb78bfd076b8fb07a44e8 |
|
14-Jul-2014 |
Alexei Zavjalov <alexei.zavjalov@intel.com> |
ART: Implement the easy long division/remainder by a constant
Also optimizes long/int divisions by power-of-two values.
Also do some clean-up.
Change-Id: Ie414e64aac251c81361ae107d157c14439e6dab5
Signed-off-by: Alexei Zavjalov <alexei.zavjalov@intel.com>
|
| 2eba1fa7e9e5f91e18ae3778d529520bd2c78d55 |
|
31-Jul-2014 |
Serban Constantinescu <serban.constantinescu@arm.com> |
AArch64: Add inlining support for ceil(), floor(), rint(), round()
This patch adds inlining support for the following Math, StrictMath
methods in the ARM64 backend:
* double ceil(double)
* double floor(double)
* double rint(double)
* long round(double)
* int round(float)
Also some cleanup.
Change-Id: I9f5a2f4065b1313649f4b0c4380b8176703c3fe1
Signed-off-by: Serban Constantinescu <serban.constantinescu@arm.com>
|
| 1c7c3990fe5fc5f1afe74f3d94e95015d7419186 |
|
30-Jul-2014 |
Andreas Gampe <agampe@google.com> |
ART: Remove bogus dcheck
Mea culpa.
Change-Id: I6fd3b678e30354c5ab5ec6da5b3619c26d486563
|
| 984305917bf57b3f8d92965e4715a0370cc5bcfb |
|
28-Jul-2014 |
Andreas Gampe <agampe@google.com> |
ART: Rework quick entrypoint code in Mir2Lir, cleanup
To reduce the complexity of calling trampolines in generic code,
introduce an enumeration for entrypoints. Introduce a header that lists
the entrypoint enum and exposes a templatized method that translates an
enum value to the corresponding thread offset value.
Call helpers are rewritten to have an enum parameter instead of the
thread offset. Also rewrite LoadHelper and GenConversionCall this way.
It is now LoadHelper's duty to select the right thread offset size.
Introduce InvokeTrampoline virtual method to Mir2Lir. This allows to
further simplify the call helpers, as well as make OpThreadMem specific
to X86 only (removed from Mir2Lir).
Make GenInlinedCharAt virtual, move a copy to X86 backend, and simplify
both copies. Remove LoadBaseIndexedDisp and OpRegMem from Mir2Lir, as they
are now specific to X86 only.
Remove StoreBaseIndexedDisp from Mir2Lir, as it was only ever used in the
X86 backend.
Remove OpTlsCmp from Mir2Lir, as it was only ever used in the X86 backend.
Remove OpLea from Mir2Lir, as it was only ever defined in the X86 backend.
Remove GenImmedCheck from Mir2Lir as it was neither used nor implemented.
Change-Id: If0a6182288c5d57653e3979bf547840a4c47626e
|
| f9d6aede77c700118e225f8312cd888262b77862 |
|
17-Jul-2014 |
Vladimir Marko <vmarko@google.com> |
Use vabs/fabs on arm/arm64 for intrinsic abs().
Bug: 11579369
(cherry picked from 5030d3ee8c6fe10394912ede107cbc8df63b7b16)
Change-Id: I7b0596a8e7e3c87a93b225519c5aeedfe4f22e6d
|
| 147eb41b53729ec8d5c188d1cac90964a51afb8a |
|
11-Jul-2014 |
Dave Allison <dallison@google.com> |
Revert "Revert "Revert "Revert "Add implicit null and stack checks for x86""""
This reverts commit 0025a86411145eb7cd4971f9234fc21c7b4aced1.
Bug: 16256184
Change-Id: Ie0760a0c293aa3b62e2885398a8c512b7a946a73
Conflicts:
compiler/dex/quick/arm64/target_arm64.cc
compiler/image_test.cc
runtime/fault_handler.cc
|
| 5030d3ee8c6fe10394912ede107cbc8df63b7b16 |
|
17-Jul-2014 |
Vladimir Marko <vmarko@google.com> |
Use vabs/fabs on arm/arm64 for intrinsic abs().
Bug: 11579369
Change-Id: If09da85e22786faa13a2d74f62cee68ea67bd087
|
| d07c9cddccd0476456a5340b716bce3f107013b0 |
|
17-Jul-2014 |
Andreas Gampe <agampe@google.com> |
ART: Lock an arg reg in GenInlinedGet
Must lock an explicit target register so that it doesn't get used
for a temp and clobbered.
Bug: 16352802
(cherry picked from commit 30ab8a8a6597962adf63f3a438ec34b754cc117e)
Change-Id: Ie478ee42732d439c2a41aac48d15e3c2e71e3fee
|
| d85614222fa062ec809af9d65f04ab6b7dc1c248 |
|
11-Jul-2014 |
Fred Shih <ffred@google.com> |
Revert "Revert "Revert "Revert "Add intrinsic for Reference.get()""""
Fixed TargetReg issue causing build failure for x86.
This reverts commit 9e82bd3f0ce9e5f5777bea2f752ff3e251d32f9f.
(cherry picked from commit 4ee7a665e7f9cd2c5ace2d6304e33f64067b209f)
Change-Id: I555f4e06955711262e6b37ffbeabee9698ec695c
|
| 30ab8a8a6597962adf63f3a438ec34b754cc117e |
|
17-Jul-2014 |
Andreas Gampe <agampe@google.com> |
ART: Lock an arg reg in GenInlinedGet
Must lock an explicit target register so that it doesn't get used
for a temp and clobbered.
Bug: 16352802
Change-Id: I9e4ac76f92460cdbe59392989d12f8d0321cc624
|
| 69dfe51b684dd9d510dbcb63295fe180f998efde |
|
11-Jul-2014 |
Dave Allison <dallison@google.com> |
Revert "Revert "Revert "Revert "Add implicit null and stack checks for x86""""
This reverts commit 0025a86411145eb7cd4971f9234fc21c7b4aced1.
Bug: 16256184
Change-Id: Ie0760a0c293aa3b62e2885398a8c512b7a946a73
|
| 4ee7a665e7f9cd2c5ace2d6304e33f64067b209f |
|
11-Jul-2014 |
Fred Shih <ffred@google.com> |
Revert "Revert "Revert "Revert "Add intrinsic for Reference.get()""""
Fixed TargetReg issue causing build failure for x86.
This reverts commit 9e82bd3f0ce9e5f5777bea2f752ff3e251d32f9f.
Change-Id: I7e6a526954467aaf68deeed999880dfe9aa5f06e
|
| 98d1cc8033251c93786e2fa8c59a2e555a9493be |
|
16-May-2014 |
Mingyao Yang <mingyao@google.com> |
Improve performance of invokevirtual/invokeinterface with embedded imt/vtable
Add an embedded version of imt/vtable into class object. Both tables start at
fixed offset within class object so method/entry point can be loaded directly
from class object for invokeinterface/invokevirtual.
Bug: 8142917
Change-Id: I4240d58cfbe9250107c95c0708c036854c455968
|
| 48f5c47907654350ce30a8dfdda0e977f5d3d39f |
|
27-Jun-2014 |
Hans Boehm <hboehm@google.com> |
Replace memory barriers to better reflect Java needs.
Replaces barriers that enforce ordering of one access type
(e.g. Load) with respect to another (e.g. store) with more general
ones that better reflect both Java requirements and actual hardware
barrier/fence instructions. The old code was inconsistent and
unclear about which barriers implied which others. Sometimes
multiple barriers were generated and then eliminated;
sometimes it was assumed that certain barriers implied others.
The new barriers closely parallel those in C++11, though, for now,
we use something closer to the old naming.
Bug: 14685856
Change-Id: Ie1c80afe3470057fc6f2b693a9831dfe83add831
|
| a9b870b73a155ce70c867d5b3f9758fab0b45f07 |
|
11-Jul-2014 |
Christopher Ferris <cferris@google.com> |
Revert "Add intrinsic for Reference.get()"
This reverts commit 460503b13bc894828a2d2d47d09e5534b3e91aa1.
Change-Id: Ie63f43049307e02e3b90f4e034abc9ea54ca4e24
|
| ccc60264229ac96d798528d2cb7dbbdd0deca993 |
|
05-Jul-2014 |
Andreas Gampe <agampe@google.com> |
ART: Rework TargetReg(symbolic_reg, wide)
Make the standard implementation in Mir2Lir and the specialized one
in the x86 backend return a pair when wide = "true". Introduce
WideKind enumeration to improve code readability. Simplify generic
code based on this implementation.
Change-Id: I670d45aa2572eedfdc77ac763e6486c83f8e26b4
|
| 7fb36ded9cd5b1d254b63b3091f35c1e6471b90e |
|
10-Jul-2014 |
Dave Allison <dallison@google.com> |
Revert "Revert "Add implicit null and stack checks for x86""
Fixes x86_64 cross compile issue. Removes command line options
and property to set implicit checks - this is hard coded now.
This reverts commit 3d14eb620716e92c21c4d2c2d11a95be53319791.
Change-Id: I5404473b5aaf1a9c68b7181f5952cb174d93a90d
|
| d4415e8bd04c4a9367744ff0149597b4f37a0e0a |
|
11-Jul-2014 |
Christopher Ferris <cferris@google.com> |
Revert "Revert "Add intrinsic for Reference.get()""
This reverts commit a9b870b73a155ce70c867d5b3f9758fab0b45f07.
Change-Id: Ic2a9b47f2b911bef4b764d10bc33cf000e4b4211
|
| 9e82bd3f0ce9e5f5777bea2f752ff3e251d32f9f |
|
11-Jul-2014 |
Sebastien Hertz <shertz@google.com> |
Revert "Revert "Revert "Add intrinsic for Reference.get()"""
This reverts commit d4415e8bd04c4a9367744ff0149597b4f37a0e0a.
Change-Id: I34553ccbdcfea35c7742d21be2a74dc7085ab2a0
|
| 0025a86411145eb7cd4971f9234fc21c7b4aced1 |
|
11-Jul-2014 |
Nicolas Geoffray <ngeoffray@google.com> |
Revert "Revert "Revert "Add implicit null and stack checks for x86"""
Broke the build.
This reverts commit 7fb36ded9cd5b1d254b63b3091f35c1e6471b90e.
Change-Id: I9df0e7446ff0913a0e1276a558b2ccf6c8f4c949
|
| 460503b13bc894828a2d2d47d09e5534b3e91aa1 |
|
18-Jun-2014 |
Fred Shih <ffred@google.com> |
Add intrinsic for Reference.get()
Added an intrinsic function for Reference.get(). Return immediately
without going through JNI if the slow path is not currently in use.
Otherwise, branch off to the the existing JNI function.
Approximately 47x speedup for cases where slow path is not enabled.
Change-Id: I13ad65a356fe4e104d8d83980694dc2740d7d039
|
| a3fe7422d7ce8bfb01f95decef45f91a44d39264 |
|
09-Jul-2014 |
Zheng Xu <zheng.xu@arm.com> |
AArch64: Fix and enable reverseBytes intrinsic.
There is no revsh on arm64, use rev16 and sxth instead.
Change-Id: I5f9879352f0ad76b386c82cbf476894af888a64c
|
| 34e826ccc80dc1cf7c4c045de6b7f8360d504ccf |
|
29-May-2014 |
Dave Allison <dallison@google.com> |
Add implicit null and stack checks for x86
This adds compiler and runtime changes for x86
implicit checks. 32 bit only.
Both host and target are supported.
By default, on the host, the implicit checks are null pointer and
stack overflow. Suspend is implemented but not switched on.
Change-Id: I88a609e98d6bf32f283eaa4e6ec8bbf8dc1df78a
|
| 3d14eb620716e92c21c4d2c2d11a95be53319791 |
|
10-Jul-2014 |
Dave Allison <dallison@google.com> |
Revert "Add implicit null and stack checks for x86"
It breaks cross compilation with x86_64.
This reverts commit 34e826ccc80dc1cf7c4c045de6b7f8360d504ccf.
Change-Id: I34ba07821fc0a022fda33a7ae21850957bbec5e7
|
| 70c4f06f9965cdb9319a2c85f65acda20086d765 |
|
25-Jun-2014 |
DaniilSokolov <daniil.y.sokolov@intel.com> |
ART: Intrinsic implementation for java.lang.System.arraycopy.
Implements intrinsic for java.lang.System.arraycopy(char[], int, char[], int, int) -
this method is internal to android class libraries and used in such classes as StringBuffer and
StringBuilder. It is not possible to call it from application code. The intrinsic for
this method is implemented as inline method (assembly code is generated manually).
The intrinsic is x86 32 bit only.
Change-Id: Id1b1e0a20d5f6d5f5ebfe1fdc2447b6d8a515432
Signed-off-by: Daniil Sokolov <daniil.y.sokolov@intel.com>
|
| 7a94961d0917495644193b281b04a570a783bb07 |
|
08-Jul-2014 |
Andreas Gampe <agampe@google.com> |
ART: Do not emit load when inlining unused Thread.currentThread()
When the result is not used, do not emit the load. This avoids
uninitialized registers leading to size-check errors.
Change-Id: I212392ffea7243720f120b2f12679df286106a02
|
| 63fe93d9f9d2956b1ee2b98cdd6ddd2153f5f9cf |
|
30-Jun-2014 |
Serban Constantinescu <serban.constantinescu@arm.com> |
AArch64: Enable Inlining.
This patch fixes the remaining issues with inlining for ARM64.
Change-Id: I2d85b7c4f3fb2b667bf6029fbc271ab954378889
Signed-off-by: Serban Constantinescu <serban.constantinescu@arm.com>
Signed-off-by: Matteo Franchin <matteo.franchin@arm.com>
|
| a77ee5103532abb197f492c14a9e6fb437054e2a |
|
02-Jul-2014 |
Chao-ying Fu <chao-ying.fu@intel.com> |
x86_64: TargetReg update for x86
Also includes changes in common code. Elimination of use of TargetReg
with one parameter and direct access to special target registers.
Change-Id: Ied2c1f87d4d1e4345248afe74bca40487a46a371
Signed-off-by: Serguei Katkov <serguei.i.katkov@intel.com>
Signed-off-by: Chao-ying Fu <chao-ying.fu@intel.com>
|
| b5860fb459f1ed71f39d8a87b45bee6727d79fe8 |
|
22-Jun-2014 |
buzbee <buzbee@google.com> |
Register promotion support for 64-bit targets
Not sufficiently tested for 64-bit targets, but should be
fairly close.
A significant amount of refactoring could stil be done, (in
later CLs).
With this change we are not making any changes to the vmap
scheme. As a result, it is a requirement that if a vreg
is promoted to both a 32-bit view and the low half of a
64-bit view it must share the same physical register. We
may change this restriction later on to allow for more flexibility
for 32-bit Arm.
For example, if v4, v5, v4/v5 and v5/v6 are all hot enough to
promote, we'd end up with something like:
v4 (as an int) -> r10
v4/v5 (as a long) -> r10
v5 (as an int) -> r11
v5/v6 (as a long) -> r11
Fix a couple of ARM64 bugs on the way...
Change-Id: I6a152b9c164d9f1a053622266e165428045362f3
|
| 255e014542b2180620230e4d9d6000ae06846bbd |
|
04-Jul-2014 |
Matteo Franchin <matteo.franchin@arm.com> |
Aarch64: fix references handling in Load*Indexed.
Fix the way we handle references in Load/StoreBaseIndexed and friends.
We assume references are 64-bit RegStorage entities, with the
difference that they are load as 32-bit values.
Change-Id: I7fe987ef9e97e9a5042b85378b33d1e85710d8b5
|
| c5e4ce116e4d44bfdf162f0c949e77772d7e0654 |
|
10-Jun-2014 |
nikolay serdjuk <nikolay.y.serdjuk@intel.com> |
x86_64: Fix intrinsics
The following intrinsics have been ported:
- Abs(double/long/int/float)
- String.indexOf/charAt/compareTo/is_empty/length
- Float.floatToRawIntBits, Float.intBitsToFloat
- Double.doubleToRawLongBits, Double.longBitsToDouble
- Thread.currentThread
- Unsafe.getInt/Long/Object, Unsafe.putInt/Long/Object
- Math.sqrt, Math.max, Math.min
- Long.reverseBytes
Math.min and max for longs have been implemented for x86_64.
Commented out until good tests available:
- Memory.peekShort/Int/Long, Memory.pokeShort/Int/Long
Turned off on x86-64 as reported having problems
- Cas
Change-Id: I934bc9c90fdf953be0d3836a17b6ee4e7c98f244
|
| 23abec955e2e733999a1e2c30e4e384e46e5dde4 |
|
02-Jul-2014 |
Serban Constantinescu <serban.constantinescu@arm.com> |
AArch64: Add few more inline functions
This patch adds inlining support for the following functions:
* Math.max/min(long, long)
* Math.max/min(float, float)
* Math.max/min(double, double)
* Integer.reverse(int)
* Long.reverse(long)
Change-Id: Ia2b1619fd052358b3a0d23e5fcbfdb823d2029b9
Signed-off-by: Serban Constantinescu <serban.constantinescu@arm.com>
|
| 4b537a851b686402513a7c4a4e60f5457bb8d7c1 |
|
01-Jul-2014 |
Andreas Gampe <agampe@google.com> |
ART: Quick compiler: More size checks, add TargetReg variants
Add variants for TargetReg for requesting specific register usage,
e.g., wide and ref. More register size checks.
With code adapted from https://android-review.googlesource.com/#/c/98605/.
Change-Id: I852d3be509d4dcd242c7283da702a2a76357278d
|
| f9872f0b5f713af867b4e32e647a1b92f94fb01a |
|
02-Jul-2014 |
Andreas Gampe <agampe@google.com> |
ART: Fix size error reported by ARM64 backend
Also removes a spurious LOG in dex2oat.
Change-Id: Ia264fbfb3cb8d59978f3a61e814eb6940e272ece
|
| 2db3e269e3051dacb3c8a4af8f03fdad9b0fd740 |
|
26-Jun-2014 |
Douglas Leung <douglas@mips.com> |
Fix quick mode bugs for Mips.
This patch enable quick mode for Mips and allows the emulator to boot.
However the emulator is still not 100% functional. It still have problems
launching some apps.
Change-Id: Id46a39a649a2fd431a9f13b06ecf34cbd1d20930
Signed-off-by: Douglas Leung <douglas@mips.com>
|
| de68676b24f61a55adc0b22fe828f036a5925c41 |
|
24-Jun-2014 |
Andreas Gampe <agampe@google.com> |
Revert "ART: Split out more cases of Load/StoreRef, volatile as parameter"
This reverts commit 2689fbad6b5ec1ae8f8c8791a80c6fd3cf24144d.
Breaks the build.
Change-Id: I9faad4e9a83b32f5f38b2ef95d6f9a33345efa33
|
| 3c12c512faf6837844d5465b23b9410889e5eb11 |
|
24-Jun-2014 |
Andreas Gampe <agampe@google.com> |
Revert "Revert "ART: Split out more cases of Load/StoreRef, volatile as parameter""
This reverts commit de68676b24f61a55adc0b22fe828f036a5925c41.
Fixes an API comment, and differentiates between inserting and appending.
Change-Id: I0e9a21bb1d25766e3cbd802d8b48633ae251a6bf
|
| 2689fbad6b5ec1ae8f8c8791a80c6fd3cf24144d |
|
23-Jun-2014 |
Andreas Gampe <agampe@google.com> |
ART: Split out more cases of Load/StoreRef, volatile as parameter
Splits out more cases of ref registers being loaded or stored. For
code clarity, adds volatile as a flag parameter instead of a separate
method.
On ARM64, continue cleanup. Add flags to print/fatal on size mismatches.
Change-Id: I30ed88433a6b4ff5399aefffe44c14a5e6f4ca4e
|
| 49c5f50cbc8e4d8c195d8f1409abcfde08b39786 |
|
20-Jun-2014 |
Andreas Gampe <agampe@google.com> |
ART: Fix register overlap checks in CopyArgumentRegs
This is a make-shift CL. Expect this to be replaced by a reworked
implementation.
Change-Id: Ia74697d1436efd2971bc4c791fabed66d2e9d72d
|
| 5655e84e8d71697d8ef3ea901a0b853af42c559e |
|
18-Jun-2014 |
Andreas Gampe <agampe@google.com> |
ART: Implicit checks in the compiler are independent from Runtime
When cross-compiling, those flags are independent. This is an
initial CL that helps bypass fatal failures when cross-compiling,
as not all architectures support (and have turned on) implicit
checks.
The actual transport for the target architecture when it is
different from the runtime needs to be implemented in a follow-up
CL.
Bug: 15703710
Change-Id: Idc881a9a4abfd38643b862a491a5af9b8841f693
|
| 33ae5583bdd69847a7316ab38a8fa8ccd63093ef |
|
12-Jun-2014 |
buzbee <buzbee@google.com> |
Arm64 hard-float
Basic enabling of hard-float for Arm64. In future CLs we'll
consolidate the various targets - there is a lot of overlap.
Compilation remains turned off in this CL, but I expect
to enable a subset shortly. With compilation fully enabled
(including the EXPERIMENTAL opcodes with the exception of
REM and THROW), we get the following run-test results:
003-omnibus-opcode failures:
Classes.checkCast
Classes.arrayInstance
UnresTest2
Haven't gone deep, but these appear to be related to throw/catch and/or
stacktrace.
For REM, the generated code looks reasonable to me - my guess is that
we've got something wrong on the transition to the runtime. Haven't
looked deeper yet, though.
The bulk of the other failure also appear to be related to transitioning
to the runtime system, or handling try/catch.
run-test status:
Status with optimizations disabled, REM_FLOAT/DOUBLE and THROW disabled:
succeeded tests: 94
failed tests: 22
failed: 003-omnibus-opcodes
failed: 004-annotations
failed: 009-instanceof2
failed: 024-illegal-access
failed: 025-access-controller
failed: 031-class-attributes
failed: 044-proxy
failed: 045-reflect-array
failed: 046-reflect
failed: 058-enum-order
failed: 062-character-encodings
failed: 063-process-manager
failed: 064-field-access
failed: 068-classloader
failed: 071-dexfile
failed: 083-compiler-regressions
failed: 084-class-init
failed: 086-null-super
failed: 087-gc-after-link
failed: 100-reflect2
failed: 107-int-math2
failed: 201-built-in-exception-detail-messages
Change-Id: Ib66209285cad8998d77a14781de300af02a96b15
|
| 7e399fd3a99ba9c9dbfafdf14f75dd318fa7d454 |
|
11-Jun-2014 |
Chao-ying Fu <chao-ying.fu@intel.com> |
x86_64: Disable all optimizations and fix bugs
This disables all optimizations and ensures that art tests still pass.
Change-Id: I43217378d6889bb04f4d064f8d53cb3ff4c20aa0
Signed-off-by: Chao-ying Fu <chao-ying.fu@intel.com>
Signed-off-by: Serguei Katkov <serguei.i.katkov@intel.com>
Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
|
| 169489b4f4be8c5dd880ba6f152948324d22ff79 |
|
11-Jun-2014 |
Serban Constantinescu <serban.constantinescu@arm.com> |
AArch64: Add support for inlined methods
This patch adds support for Arm64 inlined methods.
Change-Id: Ic6aeed6d2d32f65cd1e63cf482f83cdcf958798a
|
| 8dea81ca9c0201ceaa88086b927a5838a06a3e69 |
|
06-Jun-2014 |
Vladimir Marko <vmarko@google.com> |
Rewrite use/def masks to support 128 bits.
Reduce LIR memory usage by holding masks by pointers in the
LIR rather than directly and using pre-defined const masks
for the common cases, allocating very few on the arena.
Change-Id: I0f6d27ef6867acd157184c8c74f9612cebfe6c16
|
| d3703d82a0afc28a4ea0cb0f6d88e9f8adc23e43 |
|
09-Jun-2014 |
Mark Mendell <mark.p.mendell@intel.com> |
X86_64: Pass 'hidden method index' in EAX
Method* is in EDI, and EAX isn't an argument register, so EAX is free
to hold the hidden method index.
Change-Id: I793a54d00a4593e140f97144419d849b53bfdf44
Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
|
| 2d41a655f4f0e4b2178bbd7e93901a5ed6eae4a6 |
|
09-Jun-2014 |
Zheng Xu <zheng.xu@arm.com> |
AArch64: Fix kOpLsl, rem-float/double.
Change-Id: I6f7293493c0f94f96882d2e559e3eef659a23aec
|
| 58994cdb00b323339bd83828eddc53976048006f |
|
16-May-2014 |
Dmitry Petrochenko <dmitry.petrochenko@intel.com> |
x86_64: Hard Float ABI support in QCG
This patch shows our efforts on resolving the ART limitations:
- passing "float"/"double" arguments via FPR
- passing "long" arguments via single GPR, not pair
- passing more than 3 agruments via GPR.
Work done:
- Extended SpecialTargetRegister enum with kARG4, kARG5, fARG4..fARG7.
- Created initial LoadArgRegs/GenDalvikX/FlushIns version in X86Mir2Lir.
- Unlimited number of long/double/float arguments support
- Refactored (v2)
Change-Id: I5deadd320b4341d5b2f50ba6fa4a98031abc3902
Signed-off-by: Serguei Katkov <serguei.i.katkov@intel.com>
Signed-off-by: Dmitry Petrochenko <dmitry.petrochenko@intel.com>
Signed-off-by: Chao-ying Fu <chao-ying.fu@intel.com>
Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
|
| 511c8a653d5896e81428393a1c3d427da64e36f3 |
|
03-Jun-2014 |
Zheng Xu <zheng.xu@arm.com> |
AArch64: Fix cmp-long and method with long arguments.
1. Fix cmp-long.
2. Use single register to pass long argument.
3. Flush StackReference<ArtMethod> on arm64 the same as in common code.
3. Fix the mismatch in calculate reg offset.
Change-Id: Ie2723260fb143512e4da6ee88d4f3aded80d3d5e
|
| a0cd2d701f29e0bc6275f1b13c0edfd4ec391879 |
|
01-Jun-2014 |
buzbee <buzbee@google.com> |
Quick compiler: reference cleanup
For 32-bit targets, object references are 32 bits wide both in
Dalvik virtual registers and in core physical registers. Because of
this, object references and non-floating point values were both
handled as if they had the same register class (kCoreReg).
However, for 64-bit systems, references are 32 bits in Dalvik vregs, but
64 bits in physical registers. Although the same underlying physical
core registers will still be used for object reference and non-float
values, different register class views will be used to represent them.
For example, an object reference in arm64 might be held in x3 at some
point, while the same underlying physical register, w3, would be used
to hold a 32-bit int.
This CL breaks apart the handling of object reference and non-float values
to allow the proper register class (or register view) to be used. A
new register class, kRefReg, is introduced which will map to a 32-bit
core register on 32-bit targets, and 64-bit core registers on 64-bit
targets. From this point on, object references should be allocated
registers in the kRefReg class rather than kCoreReg.
Change-Id: I6166827daa8a0ea3af326940d56a6a14874f5810
|
| ffddfdf6fec0b9d98a692e27242eecb15af5ead2 |
|
03-Jun-2014 |
Tim Murray <timmurray@google.com> |
DO NOT MERGE
Merge ART from AOSP to lmp-preview-dev.
Change-Id: I0f578733a4b8756fd780d4a052ad69b746f687a9
|
| f2c3e564fa9e484c29f35f10d4659ab2d7b8614a |
|
29-May-2014 |
buzbee <buzbee@google.com> |
Quick compiler: Method* as a reference
This is the first of two CLs intended to fix up and make consistent
the handling of references in the Quick backend. A sibling
CL c/96237 updates the runtime to treat Method* as a compressed
reference when stored. This CL makes a similar change for the
backend.
As far as the general handling of in-register references, though,
the current Quick backend is not consistent even for non-Method*
references. Sometimes they are treated as references, but other
times are handled as if they were 32-bit ints. A subsequent CL
will deal with that issue.
Change-Id: I5591c5eea6cca6ed22208ab806fd38b959c9d03d
|
| 85089dd28a39dd20f42ac258398b2a08668f9ef1 |
|
26-May-2014 |
buzbee <buzbee@google.com> |
Quick compiler: generalize NarrowRegLoc()
Some of the RegStorage utilites (DoubleToLowSingle(),
DoubleToHighSingle(), etc.) worked only for targets which
which treat double precision registers as a pair of aliased
single precision registers.
This CL elminates those utilities, and replaces them with
a new RegisterInfo utility that will search an aliased register
set and return the member matching the required storage
configuration (if it exists).
Change-Id: Iff5de10f467d20a56e1a89df9fbf30d1cf63c240
|
| 4c80043aa75d0dfa62dd2fd1845bc2b92110336d |
|
07-May-2014 |
Dmitry Petrochenko <dmitry.petrochenko@intel.com> |
x86_64: Disable all intrinsics
Intrinsics are subject to rework for x86_64 and disabled for now.
Change-Id: Ice67db083fe43dc4faa9276faf02234a4a24f207
Signed-off-by: Dmitry Petrochenko <dmitry.petrochenko@intel.com>
|
| e87f9b5185379c8cf8392d65a63e7bf7e51b97e7 |
|
30-Apr-2014 |
Mark Mendell <mark.p.mendell@intel.com> |
Allow X86 QBE to be extended
Enhancements and updates to allow X86Mir2LIR Backend to be subclassed
for experimentation. Add virtual in a whole bunch of places, and make
some other changes to get this to work.
Change-Id: I0980a19bc5d5725f91660f98c95f1f51c17ee9b6
Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
|
| 082833c8d577db0b2bebc100602f31e4e971613e |
|
18-May-2014 |
buzbee <buzbee@google.com> |
Quick compiler, out of registers fix
It turns out that the register pool sanity checker was not
working as expected, leaving some inconsistencies unreported.
This could result in "out of registers" failures, as well
as other more subtle problems.
This CL fixes the sanity checker, adds a lot more check and cleans
up the previously undetected episodes of insanity.
Cherry-pick of internal change 468162
Change-Id: Id2da97e99105a4c272c5fd256205a94b904ecea8
|
| 05d3aeb33683b16837741f9348d6fba9a8432068 |
|
18-May-2014 |
buzbee <buzbee@google.com> |
Quick compiler, out of registers fix
Fixes b/15024623
It turns out that the register pool sanity checker was not
working as expected, leaving some inconsistencies unreported.
This CL fixes the sanity checker, adds a lot more check and cleans
up the previously undetected episodes of insanity.
Change-Id: I4d67db864ca5926a1975db251e7e631b65a86275
|
| 26ee07a9dbdff5d7ea61ff412e5fb7f510972aad |
|
12-May-2014 |
Dmitry Petrochenko <dmitry.petrochenko@intel.com> |
Support any cpu register sequence in LoadArgRegs
The LoadArgRegs was designed only for case when
arg1.reg < arg2.reg < arg3.reg which is not true for x86_64 ABI.
Now LoadArgRegs supports three args passed by any cpu register.
Change-Id: I62f58c47ec12b8e3f8124724cb3b5371dde8173f
Signed-off-by: Dmitry Petrochenko <dmitry.petrochenko@intel.com>
|
| 9bf549d472462e4d1888a97c218a8c26fe3bfefb |
|
12-May-2014 |
Dmitry Petrochenko <dmitry.petrochenko@intel.com> |
x86_64: Handle UnsafeGet/Put equal to x86
This patch extends "Handle x86_64 architecture equal to x86"
and covers UnsafeGet/UnsafePut.
Change-Id: Ib07cfc217c7825cff0b49cfbb9151452d62b1b68
Signed-off-by: Dmitry Petrochenko <dmitry.petrochenko@intel.com>
|
| 3ec5da20f27da3bb8cea7ae29538c30c4b1549b4 |
|
13-May-2014 |
Andreas Gampe <agampe@google.com> |
ART: Fix typo in ThreadOffset modification
Change-Id: Ifc3bd44a2a8442dcc242f4abcb17ae2acbc3b4e7
|
| 2f244e9faccfcca68af3c5484c397a01a1c3a342 |
|
08-May-2014 |
Andreas Gampe <agampe@google.com> |
ART: Add more ThreadOffset in Mir2Lir and backends
This duplicates all methods with ThreadOffset parameters, so that
both ThreadOffset<4> and ThreadOffset<8> can be handled. Dynamic
checks against the compilation unit's instruction set determine
which pointer size to use and therefore which methods to call.
Methods with unsupported pointer sizes should fatally fail, as
this indicates an issue during method selection.
Change-Id: Ifdb445b3732d3dc5e6a220db57374a55e91e1bf6
|
| e45fb9e7976c8462b94a58ad60b006b0eacec49f |
|
06-May-2014 |
Matteo Franchin <matteo.franchin@arm.com> |
AArch64: Change arm64 backend to produce A64 code.
The arm backend clone is changed to produce A64 code. At the moment
this backend can only compile simple methods (both leaf and non-leaf).
Most of the work on the assembler (assembler_arm64.cc) has been done.
Some work on the LIR generation layer (functions such as OpRegRegImm
& friends) is still necessary. The register allocator still needs to
be adapted to the A64 instruction set (it is mostly unchanged from
the arm backend). Offsets for helpers in gen_invoke.cc still need to
be changed to work on 64-bit.
Change-Id: I388f99eeb832857981c7d9d5cb5b71af64a4b921
|
| 3bf7c60a86d49bf8c05c5d2ac5ca8e9f80bd9824 |
|
07-May-2014 |
Vladimir Marko <vmarko@google.com> |
Cleanup ARM load/store wide and remove unused param s_reg.
Use a single LDRD/VLDR instruction for wide load/store on
ARM, adjust the base pointer if needed. Remove unused
parameter s_reg from LoadBaseDisp(), LoadBaseIndexedDisp()
and StoreBaseIndexedDisp() on all architectures.
Change-Id: I25a9a42d523a68addbc11abe44ddc55a4401df98
|
| 455759b5702b9435b91d1b4dada22c4cce7cae3c |
|
06-May-2014 |
Vladimir Marko <vmarko@google.com> |
Remove LoadBaseDispWide and StoreBaseDispWide.
Just pass k64 or kDouble to non-wide versions.
Change-Id: I000619c3b78d3a71db42edc747c8a0ba1ee229be
|
| 37498b6719347190f45472ad44ea21de563585eb |
|
05-May-2014 |
Dmitry Petrochenko <dmitry.petrochenko@intel.com> |
x86_64: Fix Array::DataOffset in calls
Calculates offset using utility function
Change-Id: I19339537f4458dcae931897f4ee282f5c40746d2
Signed-off-by: Dmitry Petrochenko <dmitry.petrochenko@intel.com>
|
| 091cc408e9dc87e60fb64c61e186bea568fc3d3a |
|
31-Mar-2014 |
buzbee <buzbee@google.com> |
Quick compiler: allocate doubles as doubles
Significant refactoring of register handling to unify usage across
all targets & 32/64 backends.
Reworked RegStorage encoding to allow expanded use of
x86 xmm registers; removed vector registers as a separate
register type. Reworked RegisterInfo to describe aliased
physical registers. Eliminated quite a bit of target-specific code
and generalized common code.
Use of RegStorage instead of int for registers now propagated down
to the NewLIRx() level. In future CLs, the NewLIRx() routines will
be replaced with versions that are explicit about what kind of
operand they expect (RegStorage, displacement, etc.). The goal
is to eventually use RegStorage all the way to the assembly phase.
TBD: MIPS needs verification.
TBD: Re-enable liveness tracking.
Change-Id: I388c006d5fa9b3ea72db4e37a19ce257f2a15964
|
| ff093b31d75658c3404f9b51ee45760f346f06d9 |
|
01-May-2014 |
Ian Rogers <irogers@google.com> |
Fix a few 64-bit compilation of 32-bit code issues.
Bug: 13423943
Change-Id: I939389413af0a68c0d95b23cd598b7c42afa4383
|
| 6ffcfa04ebb2660e238742a6000f5ccebdd5df15 |
|
25-Apr-2014 |
Mingyao Yang <mingyao@google.com> |
Rewrite suspend test check with LIRSlowPath.
Change-Id: I2dc17d079655586bfc588349c7a04afc2c6879af
|
| 695d13a82d6dd801aaa57a22a9d4b3f6db0d0fdb |
|
19-Apr-2014 |
buzbee <buzbee@google.com> |
Update load/store utilities for 64-bit backends
This CL replaces the typical use of LoadWord/StoreWord
utilities (which, in practice, were 32-bit load/store) in
favor of a new set that make the size explicit. We now have:
LoadWordDisp/StoreWordDisp:
32 or 64 depending on target. Load or store the natural
word size. Expect this to be used infrequently - generally
when we know we're dealing with a native pointer or flushed
register not holding a Dalvik value (Dalvik values will flush
to home location sizes based on Dalvik, rather than the target).
Load32Disp/Store32Disp:
Load or store 32 bits, regardless of target.
Load64Disp/Store64Disp:
Load or store 64 bits, regardless of target.
LoadRefDisp:
Load a 32-bit compressed reference, and expand it to the
natural word size in the target register.
StoreRefDisp:
Compress a reference held in a register of the natural word
size and store it as a 32-bit compressed reference.
Change-Id: I50fcbc8684476abd9527777ee7c152c61ba41c6f
|
| 3a74d15ccc9a902874473ac9632e568b19b91b1c |
|
22-Apr-2014 |
Mingyao Yang <mingyao@google.com> |
Delete throw launchpads.
Bug: 13170824
Change-Id: I9d5834f5a66f5eb00f2ac80774e8c27dea99949e
|
| 80365d9bb947edef0eae0bfe62b9f7a239416e6b |
|
18-Apr-2014 |
Mingyao Yang <mingyao@google.com> |
Revert "Revert "Use LIRSlowPath for throwing ArrayOutOfBoundsException.""
This adds back using LIRSlowPath for ArrayIndexOutOfBoundsException.
And fix the host test crash.
Change-Id: Idbb602f4bb2c5ce59233feb480a0ff1b216e4887
|
| 7fff544c38f0dec3a213236bb785c3ca13d21a0f |
|
18-Apr-2014 |
Brian Carlstrom <bdc@google.com> |
Revert "Use LIRSlowPath for throwing ArrayOutOfBoundsException."
This reverts commit 9d46314a309aff327f9913789b5f61200c162609.
|
| 9d46314a309aff327f9913789b5f61200c162609 |
|
18-Apr-2014 |
Mingyao Yang <mingyao@google.com> |
Use LIRSlowPath for throwing ArrayOutOfBoundsException.
Get rid of launchpads for throwing ArrayOutOfBoundsException
and use LIRSlowPath instead.
Bug: 13170824
Change-Id: I0e27f7a261a6a7fb5c0645e6113a957e098f699e
|
| e643a179cf5585ba6bafdd4fa51730d9f50c06f6 |
|
08-Apr-2014 |
Mingyao Yang <mingyao@google.com> |
Use LIRSlowPath for throwing NPE.
Get rid of launchpads for throwing NPE and use LIRSlowPath instead.
Also clean up some code of using LIRSlowPath for checking div
by zero.
Bug: 13170824
Change-Id: I0c20a49c39feff3eb1f147755e557d9bc0ff15bb
|
| d6ed642458c8820e1beca72f3d7b5f0be4a4b64b |
|
10-Apr-2014 |
Dave Allison <dallison@google.com> |
Revert "Revert "Revert "Use trampolines for calls to helpers"""
This reverts commit f9487c039efb4112616d438593a2ab02792e0304.
Change-Id: Id48a4aae4ecce73db468587967968a3f7618b700
|
| f9487c039efb4112616d438593a2ab02792e0304 |
|
09-Apr-2014 |
Dave Allison <dallison@google.com> |
Revert "Revert "Use trampolines for calls to helpers""
This reverts commit 081f73e888b3c246cf7635db37b7f1105cf1a2ff.
Change-Id: Ibd777f8ce73cf8ed6c4cb81d50bf6437ac28cb61
Conflicts:
compiler/dex/quick/mir_to_lir.h
|
| 4289456fa265b833434c2a8eee9e7a16da31c524 |
|
07-Apr-2014 |
Mingyao Yang <mingyao@google.com> |
Use LIRSlowPath for throwing div by zero exception.
Get rid of launchpads for throwing div by zero exception and
use LIRSlowPath instead. Add a CallRuntimeHelper that takes no
argument for the runtime function.
Bug: 13170824
Change-Id: I7e0563e736c6f92bd63e3fbdfe3a777ad333e338
|
| 081f73e888b3c246cf7635db37b7f1105cf1a2ff |
|
07-Apr-2014 |
Dave Allison <dallison@google.com> |
Revert "Use trampolines for calls to helpers"
This reverts commit 754ddad084ccb610d0cf486f6131bdc69bae5bc6.
Change-Id: Icd979adee1d8d781b40a5e75daf3719444cb72e8
|
| 754ddad084ccb610d0cf486f6131bdc69bae5bc6 |
|
19-Feb-2014 |
Dave Allison <dallison@google.com> |
Use trampolines for calls to helpers
This is an ARM specific optimization to the compiler
that uses trampoline islands to make calls to runtime
helper functions. The intention is to reduce the size
of the generated code (by 2 bytes per call) without
affecting performance.
By default this is on when generating an OAT file. It is
off when compiling to memory.
To switch this off in dex2oat, use the command line option:
--no-helper-trampolines
Enhances disassembler to print the trampoline entry on the
BL instruction like this:
0xb6a850c0: f7ffff9e bl -196 (0xb6a85000) ; pTestSuspend
Bug: 12607709
Change-Id: I9202bdb7cf21252ad807bd48701f1f6ce8e3d0fe
|
| 99f391e48f79421a4d949152aec6bafe1a7b5b82 |
|
03-Apr-2014 |
Vladimir Marko <vmarko@google.com> |
Fix Unsafe.getLong()/putLong() for x86, add test.
Change-Id: Id6841ae50e1047543c04dcdae30254dd6ce82082
|
| 6a58cb16d803c9a7b3a75ccac8be19dd9d4e520d |
|
02-Apr-2014 |
Dmitry Petrochenko <dmitry.petrochenko@intel.com> |
art: Handle x86_64 architecture equal to x86
This patch forces FE/ME to treat x86_64 as x86 exactly.
The x86_64 logic will be revised later when assembly will be ready.
Change-Id: I4a92477a6eeaa9a11fd710d35c602d8d6f88cbb6
Signed-off-by: Dmitry Petrochenko <dmitry.petrochenko@intel.com>
|
| 7c95cefc168ba81b17a9ed2d987ac5bcf0b05781 |
|
03-Apr-2014 |
Mathieu Chartier <mathieuc@google.com> |
Use temp register in Unsafe Get/Put intrisics for displaced offset.
Previously, the object register would get clobberd by the adding the
offset for wide UnsafeGets and wide UnsafePuts. This resulted in heap
corruption in AtomicLongFieldUpdater.compareAndSet and possibly other
places.
Bug: 13744490
Change-Id: Ic368d930b855c5c57e22060b32b73d0745328ef2
|
| dd7624d2b9e599d57762d12031b10b89defc9807 |
|
15-Mar-2014 |
Ian Rogers <irogers@google.com> |
Allow mixing of thread offsets between 32 and 64bit architectures.
Begin a more full implementation x86-64 REX prefixes.
Doesn't implement 64bit thread offset support for the JNI compiler.
Change-Id: If9af2f08a1833c21ddb4b4077f9b03add1a05147
|
| f943914730db8ad2ff03d49a2cacd31885d08fd7 |
|
27-Mar-2014 |
Dave Allison <dallison@google.com> |
Implement implicit stack overflow checks
This also fixes some failing run tests due to missing
null pointer markers.
The implementation of the implicit stack overflow checks introduces
the ability to have a gap in the stack that is skipped during
stack walk backs. This gap is protected against read/write and
is used to trigger a SIGSEGV at function entry if the stack
will overflow.
Change-Id: I0c3e214c8b87dc250cf886472c6d327b5d58653e
|
| 2700f7e1edbcd2518f4978e4cd0e05a4149f91b6 |
|
07-Mar-2014 |
buzbee <buzbee@google.com> |
Continuing register cleanup
Ready for review.
Continue the process of using RegStorage rather than
ints to hold register value in the top layers of codegen.
Given the huge number of changes in this CL, I've attempted
to minimize the number of actual logic changes. With this
CL, the use of ints for registers has largely been eliminated
except in the lowest utility levels. "Wide" utility routines
have been updated to take a single RegStorage rather than
a pair of ints representing low and high registers.
Upcoming CLs will be smaller and more targeted. My expectations:
o Allocate float double registers as a single double rather than
a pair of float single registers.
o Refactor to push code which assumes long and double Dalvik
values are held in a pair of register to the target dependent
layer.
o Clean-up of the xxx_mir.h files to reduce the amount of #defines
for registers. May also do a register renumbering to bring all
of our targets' register naming more consistent. Possibly
introduce a target-independent float/non-float test at the
RegStorage level.
Change-Id: I646de7392bdec94595dd2c6f76e0f1c4331096ff
|
| 99ad7230ccaace93bf323dea9790f35fe991a4a2 |
|
26-Feb-2014 |
Razvan A Lupusoru <razvan.a.lupusoru@intel.com> |
Relaxed memory barriers for x86
X86 provides stronger memory guarantees and thus the memory barriers can be
optimized. This patch ensures that all memory barriers for x86 are treated
as scheduling barriers. And in cases where a barrier is needed (StoreLoad case),
an mfence is used.
Change-Id: I13d02bf3f152083ba9f358052aedb583b0d48640
Signed-off-by: Razvan A Lupusoru <razvan.a.lupusoru@intel.com>
|
| b982331680a9fa329302c68bfdcc9a4d9d403921 |
|
20-Mar-2014 |
Vladimir Marko <vmarko@google.com> |
Fix and clean up intrinsic Math.abs(long).
On ARM, make sure we don't clobber a register that we still
need for the next insn. On x86, don't free a source register
for temps if it's overlapping a result register as that
would allow the sign_reg temporary to alias with the result.
Change-Id: I785f2f607900ae8ceb2fa0b8f3eefafdf6fab5c7
|
| ec31d37f76b0d594ad1499b22b11bbeaad246c23 |
|
19-Mar-2014 |
Vladimir Marko <vmarko@google.com> |
Clean up intrinsic Math.abs(float/double).
Don't load 0x7fffffff into register.
Change-Id: I0197f9f3ad33db1f6eb09a9b4113299c00f500e3
|
| 60d7a65f7fb60f502160a2e479e86014c7787553 |
|
14-Mar-2014 |
Brian Carlstrom <bdc@google.com> |
Fix stack overflow for mutual recursion.
There was an error where we would have a pc that was in the method
which generated the stack overflow. This didn't work however
because the stack overflow check was before we stored the method in
the stack. The result was that the stack overflow handler had a PC
which wasnt necessarily in the method at the top of the stack. This
is now fixed by always restoring the link register before branching
to the throw entrypoint.
Slight code size regression on ARM/Mips (unmeasured). Regression on ARM
is 4 bytes of code per stack overflow check. Some of this regression is
mitigated by having one less GC safepoint.
Also adds test case for StackOverflowError issue (from bdc).
Tests passing: ARM, X86, Mips
Phone booting: ARM
Bug: https://code.google.com/p/android/issues/detail?id=66411
Bug: 12967914
Change-Id: I96fe667799458b58d1f86671e051968f7be78d5d
(cherry-picked from c0f96d03a1855fda7d94332331b94860404874dd)
|
| 9820b7c1dc70e75ad405b9e6e63578fa9fe94e94 |
|
02-Jan-2014 |
Vladimir Marko <vmarko@google.com> |
Early inlining of simple methods.
Inlining "special" methods: empty methods, methods returning
constants or their arguments, simple getters and setters.
Bug: 8164439
Change-Id: I8c7fa9c14351fbb2470000b378a22974daaef236
|
| c0f96d03a1855fda7d94332331b94860404874dd |
|
14-Mar-2014 |
Brian Carlstrom <bdc@google.com> |
Fix stack overflow for mutual recursion.
There was an error where we would have a pc that was in the method
which generated the stack overflow. This didn't work however
because the stack overflow check was before we stored the method in
the stack. The result was that the stack overflow handler had a PC
which wasnt necessarily in the method at the top of the stack. This
is now fixed by always restoring the link register before branching
to the throw entrypoint.
Slight code size regression on ARM/Mips (unmeasured). Regression on ARM
is 4 bytes of code per stack overflow check. Some of this regression is
mitigated by having one less GC safepoint.
Also adds test case for StackOverflowError issue (from bdc).
Tests passing: ARM, X86, Mips
Phone booting: ARM
Bug: https://code.google.com/p/android/issues/detail?id=66411
Bug: 12967914
Change-Id: I96fe667799458b58d1f86671e051968f7be78d5d
|
| 9a84ad99aab002e8cfeec9381df971a00e28d05f |
|
13-Mar-2014 |
Zheng Xu <zheng.xu@arm.com> |
Remove duplicated register load in function call to quick entry.
CallRuntimeHelperRegLocation() will load parameter to registers for native call, but
GenConversionCall() duplicates the work before it call CallRuntimeHelperRegLocation().
Instructions generated before patch:
0xf731007e: f8d9e25c ldr.w lr, [r9, #604] ; pF2l
0xf7310082: ee180a10 vmov.f32 r0, s16
0xf7310086: ee180a10 vmov.f32 r0, s16
0xf731008a: 47f0 blx lr
After:
0xf739707e: f8d9e25c ldr.w lr, [r9, #604] ; pF2l
0xf7397082: ee180a10 vmov.f32 r0, s16
0xf7397086: 47f0 blx lr
Change-Id: I1868aefa4703a0f8133eaac707f5b80f01293cb8
|
| b373e091eac39b1a79c11f2dcbd610af01e9e8a9 |
|
21-Feb-2014 |
Dave Allison <dallison@google.com> |
Implicit null/suspend checks (oat version bump)
This adds the ability to use SEGV signals
to throw NullPointerException exceptions from Java code rather
than having the compiler generate explicit comparisons and
branches. It does this by using sigaction to trap SIGSEGV and when triggered
makes sure it's in compiled code and if so, sets the return
address to the entry point to throw the exception.
It also uses this signal mechanism to determine whether to check
for thread suspension. Instead of the compiler generating calls
to a function to check for threads being suspended, the compiler
will now load indirect via an address in the TLS area. To trigger
a suspend, the contents of this address are changed from something
valid to 0. A SIGSEGV will occur and the handler will check
for a valid instruction pattern before invoking the thread
suspension check code.
If a user program taps SIGSEGV it will prevent our signal handler
working. This will cause a failure in the runtime.
There are two signal handlers at present. You can control them
individually using the flags -implicit-checks: on the runtime
command line. This takes a string parameter, a comma
separated set of strings. Each can be one of:
none switch off
null null pointer checks
suspend suspend checks
all all checks
So to switch only suspend checks on, pass:
-implicit-checks:suspend
There is also -explicit-checks to provide the reverse once
we change the default.
For dalvikvm, pass --runtime-arg -implicit-checks:foo,bar
The default is -implicit-checks:none
There is also a property 'dalvik.vm.implicit_checks' whose value is the same
string as the command option. The default is 'none'. For example to switch on
null checks using the option:
setprop dalvik.vm.implicit_checks null
It only works for ARM right now.
Bumps OAT version number due to change to Thread offsets.
Bug: 13121132
Change-Id: If743849138162f3c7c44a523247e413785677370
|
| 3bc8615332b7848dec8c2297a40f7e4d176c0efb |
|
13-Mar-2014 |
Vladimir Marko <vmarko@google.com> |
Use LIRSlowPath for intrinsics, improve String.indexOf().
Rewrite intrinsic launchpads to use the LIRSlowPath.
Improve String.indexOf for constant chars by avoiding
the check for code points over 0xFFFF.
Change-Id: I7fd5583214c5b4ab9c38ee36c5d6f003dd6345a8
|
| 49161cef10a308aedada18e9aa742498d6e6c8c7 |
|
12-Mar-2014 |
Jeff Hao <jeffhao@google.com> |
Allow patching between dex files in the boot classpath.
Change-Id: I53f219a5382d0fcd580e96e50025fdad4fc399df
|
| 2f4c3a4e1b84963e9f4465fc476d1ec804321601 |
|
12-Mar-2014 |
buzbee <buzbee@google.com> |
Remove spurious duplicate line of code
This CL removes a duplicate line of code which appears to have
been intended for removal during a cleanup, but wasn't. It would
not have affected correctness, rather it uselessly performed the
same store twice.
Bug originally reported by M Mendell.
Change-Id: If4333a29f32b6bdb944b67aa560d856611041ff6
|
| f096aad9203d7c50b2f9cbe1c1215a50c265a059 |
|
23-Jan-2014 |
Vladimir Marko <vmarko@google.com> |
Cache method lowering info in mir graph.
This should enable easy inlining checks. It should also
improve compilation time of methods that call the same
methods over and over - it is exactly such methods that
tend to exceed our 100ms time limit.
Change-Id: If01cd18e039071a74a1444570283c153429c9cd4
|
| a44d4f508fa1642294e79d3ebecd790afe75ea60 |
|
05-Mar-2014 |
buzbee <buzbee@google.com> |
Fix read of uninitialized memory in InlineIndexOf
The are two flavors of IndexOf that we treat as an intrinsic: a
zero-based verion with 2 args and a 3-arg version that also takes
a start position. The same code is used for both, but Valgrind
reminded us that we shouldn't try loading a RegLocation for the
non-extent 3rd arg in the 2 argument version.
We got lucky in that the bug was benign - the generated code would
still be correct.
Change-Id: I0bc7798c8034d35007ffe6d6d62f9ceb91fc44fd
|
| 00e1ec6581b5b7b46ca4c314c2854e9caa647dd2 |
|
28-Feb-2014 |
Bill Buzbee <buzbee@android.com> |
Revert "Revert "Rework Quick compiler's register handling""
This reverts commit 86ec520fc8b696ed6f164d7b756009ecd6e4aace.
Ready. Fixed the original type, plus some mechanical changes
for rebasing.
Still needs additional testing, but the problem with the original
CL appears to have been a typo in the definition of the x86
double return template RegLocation.
Change-Id: I828c721f91d9b2546ef008c6ea81f40756305891
|
| 86ec520fc8b696ed6f164d7b756009ecd6e4aace |
|
26-Feb-2014 |
Bill Buzbee <buzbee@android.com> |
Revert "Rework Quick compiler's register handling"
This reverts commit 2c1ed456dcdb027d097825dd98dbe48c71599b6c.
Change-Id: If88d69ba88e0af0b407ff2240566d7e4545d8a99
|
| 2c1ed456dcdb027d097825dd98dbe48c71599b6c |
|
20-Feb-2014 |
buzbee <buzbee@google.com> |
Rework Quick compiler's register handling
For historical reasons, the Quick backend found it convenient
to consider all 64-bit Dalvik values held in registers
to be contained in a pair of 32-bit registers. Though this
worked well for ARM (with double-precision registers also
treated as a pair of 32-bit single-precision registers) it doesn't
play well with other targets. And, it is somewhat problematic
for 64-bit architectures.
This is the first of several CLs that will rework the way the
Quick backend deals with physical registers. The goal is to
eliminate the "64-bit value backed with 32-bit register pair"
requirement from the target-indendent portions of the backend
and support 64-bit registers throughout.
The key RegLocation struct, which describes the location of
Dalvik virtual register & register pairs, previously contained
fields for high and low physical registers. The low_reg and
high_reg fields are being replaced with a new type: RegStorage.
There will be a single instance of RegStorage for each RegLocation.
Note that RegStorage does not increase the space used. It is
16 bits wide, the same as the sum of the 8-bit low_reg and
high_reg fields.
At a target-independent level, it will describe whether the physical
register storage associated with the Dalvik value is a single 32
bit, single 64 bit, pair of 32 bit or vector. The actual register
number encoding is left to the target-dependent code layer.
Because physical register handling is pervasive throughout the
backend, this restructuring necessarily involves large CLs with
lots of changes. I'm going to roll these out in stages, and
attempt to segregate the CLs with largely mechanical changes from
those which restructure or rework the logic.
This CL is of the mechanical change variety - it replaces low_reg
and high_reg from RegLocation and introduces RegStorage. It also
includes a lot of new code (such as many calls to GetReg())
that should go away in upcoming CLs.
The tentative plan for the subsequent CLs is:
o Rework standard register utilities such as AllocReg() and
FreeReg() to use RegStorage instead of ints.
o Rework the target-independent GenXXX, OpXXX, LoadValue,
StoreValue, etc. routines to take RegStorage rather than
int register encodings.
o Take advantage of the vector representation and eliminate
the current vector field in RegLocation.
o Replace the "wide" variants of codegen utilities that take
low_reg/high_reg pairs with versions that use RegStorage.
o Add 64-bit register target independent codegen utilities
where possible, and where not virtualize with 32-bit general
register and 64-bit general register variants in the target
dependent layer.
o Expand/rework the LIR def/use flags to allow for more registers
(currently, we lose out on 16 MIPS floating point regs as
well as ARM's D16..D31 for lack of space in the masks).
o [Possibly] move the float/non-float determination of a register
from the target-dependent encoding to RegStorage. In other
words, replace IsFpReg(register_encoding_bits).
At the end of the day, all code in the target independent layer
should be using RegStorage, as should much of the target dependent
layer. Ideally, we won't be using the physical register number
encoding extracted from RegStorage (i.e. GetReg()) until the
NewLIRx() layer.
Change-Id: Idc5c741478f720bdd1d7123b94e4288be5ce52cb
|
| 4028a6c83a339036864999fdfd2855b012a9f1a7 |
|
20-Feb-2014 |
Mark Mendell <mark.p.mendell@intel.com> |
Inline x86 String.indexOf
Take advantage of the presence of a constant search char or start index
to tune the generated code.
Change-Id: I0adcf184fb91b899a95aa4d8ef044a14deb51d88
Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
|
| 3bc01748ef1c3e43361bdf520947a9d656658bf8 |
|
06-Feb-2014 |
Razvan A Lupusoru <razvan.a.lupusoru@intel.com> |
GenSpecialCase support for x86
Moved GenSpecialCase from being ARM specific to common code to allow
it to be used by x86 quick as well.
Change-Id: I728733e8f4c4da99af6091ef77e5c76ae0fee850
Signed-off-by: Razvan A Lupusoru <razvan.a.lupusoru@intel.com>
|
| 55d0eac918321e0525f6e6491f36a80977e0d416 |
|
06-Feb-2014 |
Mark Mendell <mark.p.mendell@intel.com> |
Support Direct Method/Type access for X86
Thumb generates code to optimize calls to methods within core.oat.
Implement this for X86 as well, but take advantage of mov with 32 bit
immediate and call relative with 32 bit immediate.
Fix some incorrect return locations for long inlines.
Change-Id: I1907bdfc7574f3d0aa76c7fad13dc537acdf1ed3
Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
|
| dbb17e378b538133750e56375bbdbb217db7b248 |
|
07-Feb-2014 |
Yixin Shou <yixin.shou@intel.com> |
Added inlined abs method with float and double type
This patch added the implementation for inlining java.lang.Math.abs()
method with float and double type.
Change-Id: Ic99471b4ab4176e4a0153bef383bb49944fb636f
Signed-off-by: Yixin Shou <yixin.shou@intel.com>
|
| ef7d42fca18c16fbaf103822ad16f23246e2905d |
|
06-Jan-2014 |
Ian Rogers <irogers@google.com> |
Object model changes to support 64bit.
Modify mirror objects so that references between them use an ObjectReference
value type rather than an Object* so that functionality to compress larger
references can be captured in the ObjectRefererence implementation.
ObjectReferences are 32bit and all other aspects of object layout remain as
they are currently.
Expand fields in objects holding pointers so they can hold 64bit pointers. Its
expected the size of these will come down by improving where we hold compiler
meta-data.
Stub out x86_64 architecture specific runtime implementation.
Modify OutputStream so that reads and writes are of unsigned quantities.
Make the use of portable or quick code more explicit.
Templatize AtomicInteger to support more than just int32_t as a type.
Add missing, and fix issues relating to, missing annotalysis information on the
mutator lock.
Refactor and share implementations for array copy between System and uses
elsewhere in the runtime.
Fix numerous 64bit build issues.
Change-Id: I1a5694c251a42c9eff71084dfdd4b51fff716822
|
| 2b724cbb4cb096d3e061c3ab720954608016ee0c |
|
06-Feb-2014 |
Mark Mendell <mark.p.mendell@intel.com> |
Rewrite GenInlinedCharAt for x86
Take advantage of memory addressing modes and use constant index values
directly for x86.
Change-Id: I4476862f415908ebc38ba2bc59ec4d23785f6173
Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
|
| 2c498d1f28e62e81fbdb477ff93ca7454e7493d7 |
|
30-Jan-2014 |
Razvan A Lupusoru <razvan.a.lupusoru@intel.com> |
Specializing x86 range argument copying
The ARM implementation of range argument copying was specialized in some cases.
For all other architectures, it would fall back to generating memcpy. This patch
updates the x86 implementation so it does not call memcpy and instead generates
loads and stores, favoring movement of 128-bit chunks.
Change-Id: Ic891e5609a4b0e81a47c29cc5a9b301bd10a1933
Signed-off-by: Razvan A Lupusoru <razvan.a.lupusoru@intel.com>
|
| df8ee2ea9908db3dde463fed68391b0040517653 |
|
28-Jan-2014 |
Mark Mendell <mark.p.mendell@intel.com> |
x86 updates GenInlinedUnsafePut/GenInstanceofFinal
Allow x86 to inline GenInlinedUnsafePut by freeing up a temporary
register early. Make an x86 specific version of GenInstanceofFinal that
uses compare to memory and a setCC instruction.
Change-Id: I67788d7ae83776b0b9069fe4b379452190774992
Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
|
| bb8f0ab736b61db8f543e433859272e83f96ee9b |
|
28-Jan-2014 |
Hiroshi Yamauchi <yamauchi@google.com> |
Embed array class pointers at array allocation sites.
Following https://android-review.googlesource.com/#/c/79302, embed
array class pointers at array allocation sites in the compiled code.
Change-Id: I67a1292466dfbb7f48e746e5060e992dd93525c5
|
| be1ca55db3362f5b100c4c65da5342fd299520bb |
|
15-Jan-2014 |
Hiroshi Yamauchi <yamauchi@google.com> |
Use direct class pointers at allocation sites in the compiled code.
- Rather than looking up a class from its type ID (and checking if
it's resolved/initialized, resolving/initializing if not), use
direct class pointers, if possible (boot-code-to-boot-class pointers
and app-code-to-boot-class pointers.)
- This results in a 1-2% speedup in Ritz MemAllocTest on Nexus 4.
- Embedding the object size (along with class pointers) caused a 1-2%
slowdown in MemAllocTest and isn't implemented in this change.
- TODO: do the same for array allocations.
- TODO: when/if an application gets its own image, implement
app-code-to-app-class pointers.
- Fix a -XX:gc bug.
cf. https://android-review.googlesource.com/79460/
- Add /tmp/android-data/dalvik-cache to the list of locations to
remove oat files in clean-oat-host.
cf. https://android-review.googlesource.com/79550
- Add back a dropped UNLIKELY in FindMethodFromCode().
cf. https://android-review.googlesource.com/74205
Bug: 9986565
Change-Id: I590b96bd21f7a7472f88e36752e675547559a5b1
|
| 58af1f9385742f70aca4fcb5e13aba53b8be2ef4 |
|
19-Dec-2013 |
Vladimir Marko <vmarko@google.com> |
Clean up usage of carry flag condition codes.
On X86, kCondUlt and kCondUge are bound to CS and CC,
respectively, while on ARM it's the other way around. The
explicit binding in ConditionCode was wrong and misleading
and could lead to subtle bugs. Therefore, we detach those
constants and clean up usage. The CS and CC conditions are
now effectively unused but we keep them around as they may
eventually be useful.
And some minor cleanup and comments.
Change-Id: Ic5ed81d86b6c7f9392dd8fe9474b3ff718fee595
|
| 5816ed48bc339c983b40dc493e96b97821ce7966 |
|
27-Nov-2013 |
Vladimir Marko <vmarko@google.com> |
Detect special methods at the end of verification.
This moves special method handling to method inliner
and prepares for eventual inlining of these methods.
Change-Id: I51c51b940fb7bc714e33135cd61be69467861352
|
| e13717e796d338b08ea66f6a7e3470ca44de707f |
|
20-Nov-2013 |
Vladimir Marko <vmarko@google.com> |
Per-DexFile locking for inliner initialization.
And clean up lock and compiler driver naming.
Change-Id: I1562c7f55c4b0174a36007ba6199360da06169ff
|
| 31c2aac7137b69d5622eea09597500731fbee2ef |
|
09-Dec-2013 |
Vladimir Marko <vmarko@google.com> |
Rename ClobberCalleeSave to *Caller*, fix it for x86.
Change-Id: I6a72703a11985e2753fa9b4520c375a164301433
|
| f246af27f8c0736640eb7ae78225ef6c0c0a9f0e |
|
27-Nov-2013 |
Vladimir Marko <vmarko@google.com> |
Fix intrinsic Long.reverseBytes().
Allocate temporary only if needed and initialize it from
the correct register.
Change-Id: Ifdc0e8b586e1ef90fb817687eb86e05fba1dadbe
|
| 5c96e6b4dc354a7439b211b93462fbe8edea5e57 |
|
14-Nov-2013 |
Vladimir Marko <vmarko@google.com> |
Rewrite intrinsics detection.
Intrinsic methods should be treated as a special case of
inline methods. They should be detected early and used to
guide other optimizations. This CL rewrites the intrinsics
detection so that it can be moved to any compilation phase.
Change-Id: I4424a6a869bd98b9c478953c9e3bcaf1c6de2b33
|
| 94b400d56bb246d54a1606a3ca3f0b2157acc1fa |
|
05-Nov-2013 |
Vladimir Marko <vmarko@google.com> |
Improve Mir2Lir::GenIntrinsic() performance.
GenIntrinsic() spends most time just comparing the method's
declaring class name to the class names we're looking for
without hiting anything. Reduce the number of comparisons
by splitting the path for java.lang.* and other calls.
Change-Id: Ic0d42ee2bde9e86b602b421c11fb2315de774a29
|
| e508a2090b19fe705fbc6b99d76474037a74bbfb |
|
04-Nov-2013 |
Vladimir Marko <vmarko@google.com> |
Fix unaligned Memory peek/poke intrinsics.
Change-Id: Id454464d0b28aa37f5239f1c6589ceb0b3bbbdea
|
| 65636e5de2375839e29e3e19ee7a7db737901cf0 |
|
24-Oct-2013 |
Vladimir Marko <vmarko@google.com> |
Add intrinsics for Memory peek/poke.
Add intrinsics for single memory access (non-array)
peek/poke methods in libcore.io.Memory.
Change-Id: I5d66a5b14ea89875d8afb8252eb293f7d637b83f
|
| cdb4b715e77f427838b97da9bdb6654f561296ab |
|
01-Nov-2013 |
Vladimir Marko <vmarko@google.com> |
Fix intrinsic Long.reverseBytes().
Change-Id: I6cfab7e072f406439f0bde73f192149f0a6e58f7
|
| dfb325e0ddd746cd8f7c2e3723b3a573eb7cc111 |
|
30-Oct-2013 |
Ian Rogers <irogers@google.com> |
Don't use UTF16 length as length for MUTF8.
Bug 11367555.
Change-Id: Ia0b07072a1a49d435c3b71ed9a668b316b7ff5d8
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| 88474b416eb257078e590bf9bc7957cee604a186 |
|
24-Oct-2013 |
Jeff Hao <jeffhao@google.com> |
Implement Interface Method Tables (IMT).
Change-Id: Idf7fe85e1293453a8ad862ff2380dcd5db4e3a39
|
| 6bdf1fff5f841f3997d4b488f00647f7aa2cdaa3 |
|
29-Oct-2013 |
Vladimir Marko <vmarko@google.com> |
Add intrinsics for {Short,Int,Long}.reverseBytes().
Change-Id: I34a2ec642f59fc4ff18aed59769a9e8d7e361098
|
| 83883d7fddf30fdb8b6903560fa1337ab991e74c |
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22-Oct-2013 |
Ian Rogers <irogers@google.com> |
Populate dex cache for sharpened calls.
We ensured the resolved method was in the dex cache, but for a sharpened call
this is abstract. Ensure that the concrete method is also resolved.
Limit the use of direct dex cache based dispatch to cases where we know how to
patch the dex cache.
Bug 11389002
Change-Id: I08252686a53b5948650632837c74bcd5cbf8a862
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| 0d82948094d9a198e01aa95f64012bdedd5b6fc9 |
|
12-Oct-2013 |
buzbee <buzbee@google.com> |
64-bit prep
Preparation for 64-bit roll.
o Eliminated storing pointers in 32-bit int slots in LIR.
o General size reductions of common structures to reduce impact
of doubled pointer sizes:
- BasicBlock struct was 72 bytes, now is 48.
- MIR struct was 72 bytes, now is 64.
- RegLocation was 12 bytes, now is 8.
o Generally replaced uses of BasicBlock* pointers with 16-bit Ids.
o Replaced several doubly-linked lists with singly-linked to save
one stored pointer per node.
o We had quite a few uses of uintptr_t's that were a holdover from
the JIT (which used pointers to mapped dex & actual code cache
addresses rather than trace-relative offsets). Replaced those with
uint32_t's.
o Clean up handling of embedded data for switch tables and array data.
o Miscellaneous cleanup.
I anticipate one or two additional CLs to reduce the size of MIR and LIR
structs.
Change-Id: I58e426d3f8e5efe64c1146b2823453da99451230
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| b917ea1a62aa0ab8eca3f689ef64b5be34e11abb |
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18-Oct-2013 |
Ian Rogers <irogers@google.com> |
Fix intrinsification of floatToRawIntBits.
Accidentially lost in quick refactoring in
commit fa57c47f1b72916371a9c2d5c1389219bce655b4.
Change-Id: Ic83cf257306efa66a236f2034ffbff3b53579090
|
| a9a8254c920ce8e22210abfc16c9842ce0aea28f |
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04-Oct-2013 |
Ian Rogers <irogers@google.com> |
Improve quick codegen for aput-object.
1) don't type check known null.
2) if we know types in verify don't check at runtime.
3) if we're runtime checking then move all the code out-of-line.
Also, don't set up a callee-save frame for check-cast, do an instance-of test
then throw an exception if that fails.
Tidy quick entry point of Ldivmod to Lmod which it is on x86 and mips.
Fix monitor-enter/exit NPE for MIPS.
Fix benign bug in mirror::Class::CannotBeAssignedFromOtherTypes, a byte[]
cannot be assigned to from other types.
Change-Id: I9cb3859ec70cca71ed79331ec8df5bec969d6745
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| b48819db07f9a0992a72173380c24249d7fc648a |
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15-Sep-2013 |
buzbee <buzbee@google.com> |
Compile-time tuning: assembly phase
Not as much compile-time gain from reworking the assembly phase as I'd
hoped, but still worthwhile. Should see ~2% improvement thanks to
the assembly rework. On the other hand, expect some huge gains for some
application thanks to better detection of large machine-generated init
methods. Thinkfree shows a 25% improvement.
The major assembly change was to establish thread the LIR nodes that
require fixup into a fixup chain. Only those are processed during the
final assembly pass(es). This doesn't help for methods which only
require a single pass to assemble, but does speed up the larger methods
which required multiple assembly passes.
Also replaced the block_map_ basic block lookup table (which contained
space for a BasicBlock* for each dex instruction unit) with a block id
map - cutting its space requirements by half in a 32-bit pointer
environment.
Changes:
o Reduce size of LIR struct by 12.5% (one of the big memory users)
o Repurpose the use/def portion of the LIR after optimization complete.
o Encode instruction bits to LIR
o Thread LIR nodes requiring pc fixup
o Change follow-on assembly passes to only consider fixup LIRs
o Switch on pc-rel fixup kind
o Fast-path for small methods - single pass assembly
o Avoid using cb[n]z for null checks (almost always exceed displacement)
o Improve detection of large initialization methods.
o Rework def/use flag setup.
o Remove a sequential search from FindBlock using lookup table of 16-bit
block ids rather than full block pointers.
o Eliminate pcRelFixup and use fixup kind instead.
o Add check for 16-bit overflow on dex offset.
Change-Id: I4c6615f83fed46f84629ad6cfe4237205a9562b4
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| fc0e94bed3f88ed7e50854fd8dfaf5dcb345250f |
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24-Sep-2013 |
Ian Rogers <irogers@google.com> |
StringPiece clean up.
Profile guided clean up.
Try to avoid creating StringPieces with the contents of a dex file where
the length is known.
Try to avoid RegTypeCache::FromDescriptor when there's a class available.
Make ConstantType::ConstantValue inlinable.
Saving of about 50ms from a 2 threaded ThinkFree compile on host.
Change-Id: I47a12c3c76f46e2c9805be1c3a3e3870fe1f5d85
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| 5666afd6854b5634ae741dc8a3a633fc47d52168 |
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14-Sep-2013 |
buzbee <buzbee@google.com> |
Timely color fix
See b/10690000
For efficiency, the Quick compiler will not flush incoming register
arguments to the frame if their underlying Dalvik virtual registers
have been promoted to physical registers. In this case, though,
there was a bug on Arm devices in that an incoming Double was promoted
to physical floating point registers, but not in a usable form. The
entry code generation saw that both halves of the double were promoted,
but failed to check if it was in a form usable as a double.
In this particular case, it meant that subsequent uses of the incoming
argument referred to the uninitialized home location in the frame,
resulting in garbage color values.
That's the bug. Another problem is that the incoming double should
never have been promoted to an unusable state in the first place - but
that's merely an efficiency issue and will be addressed in another CL.
Note: no good way to generate a regression test for this issue. The
bug triggered because of an unusual sequence of events driving register
promotion that can't easily (or robustly) be triggered from Java source.
Change-Id: I7242422277193a04376461134dde71e9dec55576
(cherry picked from commit d0a03b8099347dee6e4bab3af95e14cd5a03b29c)
|
| d0a03b8099347dee6e4bab3af95e14cd5a03b29c |
|
14-Sep-2013 |
buzbee <buzbee@google.com> |
Timely color fix
See b/10690000
For efficiency, the Quick compiler will not flush incoming register
arguments to the frame if their underlying Dalvik virtual registers
have been promoted to physical registers. In this case, though,
there was a bug on Arm devices in that an incoming Double was promoted
to physical floating point registers, but not in a usable form. The
entry code generation saw that both halves of the double were promoted,
but failed to check if it was in a form usable as a double.
In this particular case, it meant that subsequent uses of the incoming
argument referred to the uninitialized home location in the frame,
resulting in garbage color values.
That's the bug. Another problem is that the incoming double should
never have been promoted to an unusable state in the first place - but
that's merely an efficiency issue and will be addressed in another CL.
Note: no good way to generate a regression test for this issue. The
bug triggered because of an unusual sequence of events driving register
promotion that can't easily (or robustly) be triggered from Java source.
Change-Id: I7242422277193a04376461134dde71e9dec55576
|
| 65ec92cf13c9d11c83711443a02e4249163d47f1 |
|
06-Sep-2013 |
Ian Rogers <irogers@google.com> |
Refactor CompilerDriver::ComputeInvokeInfo
Don't use non-const reference arguments.
Move ins before outs.
Change-Id: I4a7b8099abe91ea60f93a56077f4989303fa4876
|
| 1e54d68ce8e77dfe63340275d11a072c5184c89a |
|
06-Sep-2013 |
Sebastien Hertz <shertz@google.com> |
Disable devirtualization detection in DEX-to-DEX compiler.
This CL allows the DEX-to-DEX compiler to disable devirtualization detection.
This allows to quicken invoke-virtual/range instructions that used to be
eligible for devirtualization.
Bug: 10632943
Change-Id: I6c9f4d3249cf42b47f004be5825b3186fa83501e
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| ea46f950e7a51585db293cd7f047de190a482414 |
|
30-Jul-2013 |
Brian Carlstrom <bdc@google.com> |
Refactor java.lang.reflect implementation
Cherry-picked from commit ed41d5c44299ec5d44b8514f6e17f802f48094d1.
Move to ArtMethod/Field instead of AbstractMethod/Field and have
java.lang.reflect APIs delegate to ArtMethod/ArtField.
Bug: 10014286.
Change-Id: Iafc1d8c5b62562c9af8fb9fd8c5e1d61270536e7
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| 468532ea115657709bc32ee498e701a4c71762d4 |
|
05-Aug-2013 |
Ian Rogers <irogers@google.com> |
Entry point clean up.
Create set of entry points needed for image methods to avoid fix-up at load time:
- interpreter - bridge to interpreter, bridge to compiled code
- jni - dlsym lookup
- quick - resolution and bridge to interpreter
- portable - resolution and bridge to interpreter
Fix JNI work around to use JNI work around argument rewriting code that'd been
accidentally disabled.
Remove abstact method error stub, use interpreter bridge instead.
Consolidate trampoline (previously stub) generation in generic helper.
Simplify trampolines to jump directly into assembly code, keeps stack crawlable.
Dex: replace use of int with ThreadOffset for values that are thread offsets.
Tidy entry point routines between interpreter, jni, quick and portable.
Change-Id: I52a7c2bbb1b7e0ff8a3c3100b774212309d0828e
(cherry picked from commit 848871b4d8481229c32e0d048a9856e5a9a17ef9)
|
| 848871b4d8481229c32e0d048a9856e5a9a17ef9 |
|
05-Aug-2013 |
Ian Rogers <irogers@google.com> |
Entry point clean up.
Create set of entry points needed for image methods to avoid fix-up at load time:
- interpreter - bridge to interpreter, bridge to compiled code
- jni - dlsym lookup
- quick - resolution and bridge to interpreter
- portable - resolution and bridge to interpreter
Fix JNI work around to use JNI work around argument rewriting code that'd been
accidentally disabled.
Remove abstact method error stub, use interpreter bridge instead.
Consolidate trampoline (previously stub) generation in generic helper.
Simplify trampolines to jump directly into assembly code, keeps stack crawlable.
Dex: replace use of int with ThreadOffset for values that are thread offsets.
Tidy entry point routines between interpreter, jni, quick and portable.
Change-Id: I52a7c2bbb1b7e0ff8a3c3100b774212309d0828e
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| 834b394ee759ed31c5371d8093d7cd8cd90014a8 |
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31-Jul-2013 |
Brian Carlstrom <bdc@google.com> |
Merge remote-tracking branch 'goog/dalvik-dev' into merge-art-to-dalvik-dev
Change-Id: I323e9e8c29c3e39d50d9aba93121b26266c52a46
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| 7655f29fabc0a12765de828914a18314382e5a35 |
|
29-Jul-2013 |
Ian Rogers <irogers@google.com> |
Portable refactorings.
Separate quick from portable entrypoints.
Move architectural dependencies into arch.
Change-Id: I9adbc0a9782e2959fdc3308215f01e3107632b7c
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| 166db04e259ca51838c311891598664deeed85ad |
|
26-Jul-2013 |
Ian Rogers <irogers@google.com> |
Move assembler out of runtime into compiler/utils.
Other directory layout bits of clean up. There is still work to separate quick
and portable in some files (e.g. argument visitor, proxy..).
Change-Id: If8fecffda8ba5c4c47a035f0c622c538c6b58351
|
| 7934ac288acfb2552bb0b06ec1f61e5820d924a4 |
|
26-Jul-2013 |
Brian Carlstrom <bdc@google.com> |
Fix cpplint whitespace/comments issues
Change-Id: Iae286862c85fb8fd8901eae1204cd6d271d69496
|
| 2d88862f0752a7a0e65145b088f49dabd49d4284 |
|
19-Jul-2013 |
Brian Carlstrom <bdc@google.com> |
Fixing cpplint readability/casting issues
Change-Id: I6821da0e23737995a9b884a04e9b63fac640cd05
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| 6f485c62b9cfce3ab71020c646ab9f48d9d29d6d |
|
19-Jul-2013 |
Brian Carlstrom <bdc@google.com> |
Fix cpplint whitespace/indent issues
Change-Id: I7c1647f0c39e1e065ca5820f9b79998691ba40b1
|
| 0cd7ec2dcd8d7ba30bf3ca420b40dac52849876c |
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18-Jul-2013 |
Brian Carlstrom <bdc@google.com> |
Fix cpplint whitespace/blank_line issues
Change-Id: Ice937e95e23dd622c17054551d4ae4cebd0ef8a2
|
| 2ce745c06271d5223d57dbf08117b20d5b60694a |
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18-Jul-2013 |
Brian Carlstrom <bdc@google.com> |
Fix cpplint whitespace/braces issues
Change-Id: Ide80939faf8e8690d8842dde8133902ac725ed1a
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| 7940e44f4517de5e2634a7e07d58d0fb26160513 |
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12-Jul-2013 |
Brian Carlstrom <bdc@google.com> |
Create separate Android.mk for main build targets
The runtime, compiler, dex2oat, and oatdump now are in seperate trees
to prevent dependency creep. They can now be individually built
without rebuilding the rest of the art projects. dalvikvm and jdwpspy
were already this way. Builds in the art directory should behave as
before, building everything including tests.
Change-Id: Ic6b1151e5ed0f823c3dd301afd2b13eb2d8feb81
|