gen_invoke.cc revision 9bf549d472462e4d1888a97c218a8c26fe3bfefb
1/* 2 * Copyright (C) 2012 The Android Open Source Project 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17#include "dex/compiler_ir.h" 18#include "dex/frontend.h" 19#include "dex/quick/dex_file_method_inliner.h" 20#include "dex/quick/dex_file_to_method_inliner_map.h" 21#include "dex_file-inl.h" 22#include "entrypoints/quick/quick_entrypoints.h" 23#include "invoke_type.h" 24#include "mirror/array.h" 25#include "mirror/object_array-inl.h" 26#include "mirror/string.h" 27#include "mir_to_lir-inl.h" 28#include "x86/codegen_x86.h" 29 30namespace art { 31 32// Shortcuts to repeatedly used long types. 33typedef mirror::ObjectArray<mirror::Object> ObjArray; 34 35/* 36 * This source files contains "gen" codegen routines that should 37 * be applicable to most targets. Only mid-level support utilities 38 * and "op" calls may be used here. 39 */ 40 41void Mir2Lir::AddIntrinsicSlowPath(CallInfo* info, LIR* branch, LIR* resume) { 42 class IntrinsicSlowPathPath : public Mir2Lir::LIRSlowPath { 43 public: 44 IntrinsicSlowPathPath(Mir2Lir* m2l, CallInfo* info, LIR* branch, LIR* resume = nullptr) 45 : LIRSlowPath(m2l, info->offset, branch, resume), info_(info) { 46 } 47 48 void Compile() { 49 m2l_->ResetRegPool(); 50 m2l_->ResetDefTracking(); 51 GenerateTargetLabel(kPseudoIntrinsicRetry); 52 // NOTE: GenInvokeNoInline() handles MarkSafepointPC. 53 m2l_->GenInvokeNoInline(info_); 54 if (cont_ != nullptr) { 55 m2l_->OpUnconditionalBranch(cont_); 56 } 57 } 58 59 private: 60 CallInfo* const info_; 61 }; 62 63 AddSlowPath(new (arena_) IntrinsicSlowPathPath(this, info, branch, resume)); 64} 65 66// Macro to help instantiate. 67// TODO: This might be used to only instantiate <4> on pure 32b systems. 68#define INSTANTIATE(sig_part1, ...) \ 69 template sig_part1(ThreadOffset<4>, __VA_ARGS__); \ 70 template sig_part1(ThreadOffset<8>, __VA_ARGS__); \ 71 72 73/* 74 * To save scheduling time, helper calls are broken into two parts: generation of 75 * the helper target address, and the actual call to the helper. Because x86 76 * has a memory call operation, part 1 is a NOP for x86. For other targets, 77 * load arguments between the two parts. 78 */ 79// template <size_t pointer_size> 80RegStorage Mir2Lir::CallHelperSetup(ThreadOffset<4> helper_offset) { 81 // All CallRuntimeHelperXXX call this first. So make a central check here. 82 DCHECK_EQ(4U, GetInstructionSetPointerSize(cu_->instruction_set)); 83 84 if (cu_->instruction_set == kX86 || cu_->instruction_set == kX86_64) { 85 return RegStorage::InvalidReg(); 86 } else { 87 return LoadHelper(helper_offset); 88 } 89} 90 91RegStorage Mir2Lir::CallHelperSetup(ThreadOffset<8> helper_offset) { 92 // All CallRuntimeHelperXXX call this first. So make a central check here. 93 DCHECK_EQ(8U, GetInstructionSetPointerSize(cu_->instruction_set)); 94 95 if (cu_->instruction_set == kX86 || cu_->instruction_set == kX86_64) { 96 return RegStorage::InvalidReg(); 97 } else { 98 return LoadHelper(helper_offset); 99 } 100} 101 102/* NOTE: if r_tgt is a temp, it will be freed following use */ 103template <size_t pointer_size> 104LIR* Mir2Lir::CallHelper(RegStorage r_tgt, ThreadOffset<pointer_size> helper_offset, 105 bool safepoint_pc, bool use_link) { 106 LIR* call_inst; 107 OpKind op = use_link ? kOpBlx : kOpBx; 108 if (cu_->instruction_set == kX86 || cu_->instruction_set == kX86_64) { 109 call_inst = OpThreadMem(op, helper_offset); 110 } else { 111 call_inst = OpReg(op, r_tgt); 112 FreeTemp(r_tgt); 113 } 114 if (safepoint_pc) { 115 MarkSafepointPC(call_inst); 116 } 117 return call_inst; 118} 119template LIR* Mir2Lir::CallHelper(RegStorage r_tgt, ThreadOffset<4> helper_offset, 120 bool safepoint_pc, bool use_link); 121template LIR* Mir2Lir::CallHelper(RegStorage r_tgt, ThreadOffset<8> helper_offset, 122 bool safepoint_pc, bool use_link); 123 124template <size_t pointer_size> 125void Mir2Lir::CallRuntimeHelper(ThreadOffset<pointer_size> helper_offset, bool safepoint_pc) { 126 RegStorage r_tgt = CallHelperSetup(helper_offset); 127 ClobberCallerSave(); 128 CallHelper<pointer_size>(r_tgt, helper_offset, safepoint_pc); 129} 130INSTANTIATE(void Mir2Lir::CallRuntimeHelper, bool safepoint_pc) 131 132template <size_t pointer_size> 133void Mir2Lir::CallRuntimeHelperImm(ThreadOffset<pointer_size> helper_offset, int arg0, bool safepoint_pc) { 134 RegStorage r_tgt = CallHelperSetup(helper_offset); 135 LoadConstant(TargetReg(kArg0), arg0); 136 ClobberCallerSave(); 137 CallHelper<pointer_size>(r_tgt, helper_offset, safepoint_pc); 138} 139INSTANTIATE(void Mir2Lir::CallRuntimeHelperImm, int arg0, bool safepoint_pc) 140 141template <size_t pointer_size> 142void Mir2Lir::CallRuntimeHelperReg(ThreadOffset<pointer_size> helper_offset, RegStorage arg0, 143 bool safepoint_pc) { 144 RegStorage r_tgt = CallHelperSetup(helper_offset); 145 OpRegCopy(TargetReg(kArg0), arg0); 146 ClobberCallerSave(); 147 CallHelper<pointer_size>(r_tgt, helper_offset, safepoint_pc); 148} 149INSTANTIATE(void Mir2Lir::CallRuntimeHelperReg, RegStorage arg0, bool safepoint_pc) 150 151template <size_t pointer_size> 152void Mir2Lir::CallRuntimeHelperRegLocation(ThreadOffset<pointer_size> helper_offset, 153 RegLocation arg0, bool safepoint_pc) { 154 RegStorage r_tgt = CallHelperSetup(helper_offset); 155 if (arg0.wide == 0) { 156 LoadValueDirectFixed(arg0, TargetReg(kArg0)); 157 } else { 158 RegStorage r_tmp = RegStorage::MakeRegPair(TargetReg(kArg0), TargetReg(kArg1)); 159 LoadValueDirectWideFixed(arg0, r_tmp); 160 } 161 ClobberCallerSave(); 162 CallHelper<pointer_size>(r_tgt, helper_offset, safepoint_pc); 163} 164INSTANTIATE(void Mir2Lir::CallRuntimeHelperRegLocation, RegLocation arg0, bool safepoint_pc) 165 166template <size_t pointer_size> 167void Mir2Lir::CallRuntimeHelperImmImm(ThreadOffset<pointer_size> helper_offset, int arg0, int arg1, 168 bool safepoint_pc) { 169 RegStorage r_tgt = CallHelperSetup(helper_offset); 170 LoadConstant(TargetReg(kArg0), arg0); 171 LoadConstant(TargetReg(kArg1), arg1); 172 ClobberCallerSave(); 173 CallHelper<pointer_size>(r_tgt, helper_offset, safepoint_pc); 174} 175INSTANTIATE(void Mir2Lir::CallRuntimeHelperImmImm, int arg0, int arg1, bool safepoint_pc) 176 177template <size_t pointer_size> 178void Mir2Lir::CallRuntimeHelperImmRegLocation(ThreadOffset<pointer_size> helper_offset, int arg0, 179 RegLocation arg1, bool safepoint_pc) { 180 RegStorage r_tgt = CallHelperSetup(helper_offset); 181 if (arg1.wide == 0) { 182 LoadValueDirectFixed(arg1, TargetReg(kArg1)); 183 } else { 184 RegStorage r_tmp = RegStorage::MakeRegPair(TargetReg(kArg1), TargetReg(kArg2)); 185 LoadValueDirectWideFixed(arg1, r_tmp); 186 } 187 LoadConstant(TargetReg(kArg0), arg0); 188 ClobberCallerSave(); 189 CallHelper<pointer_size>(r_tgt, helper_offset, safepoint_pc); 190} 191INSTANTIATE(void Mir2Lir::CallRuntimeHelperImmRegLocation, int arg0, RegLocation arg1, 192 bool safepoint_pc) 193 194template <size_t pointer_size> 195void Mir2Lir::CallRuntimeHelperRegLocationImm(ThreadOffset<pointer_size> helper_offset, 196 RegLocation arg0, int arg1, bool safepoint_pc) { 197 RegStorage r_tgt = CallHelperSetup(helper_offset); 198 LoadValueDirectFixed(arg0, TargetReg(kArg0)); 199 LoadConstant(TargetReg(kArg1), arg1); 200 ClobberCallerSave(); 201 CallHelper<pointer_size>(r_tgt, helper_offset, safepoint_pc); 202} 203INSTANTIATE(void Mir2Lir::CallRuntimeHelperRegLocationImm, RegLocation arg0, int arg1, 204 bool safepoint_pc) 205 206template <size_t pointer_size> 207void Mir2Lir::CallRuntimeHelperImmReg(ThreadOffset<pointer_size> helper_offset, int arg0, 208 RegStorage arg1, bool safepoint_pc) { 209 RegStorage r_tgt = CallHelperSetup(helper_offset); 210 OpRegCopy(TargetReg(kArg1), arg1); 211 LoadConstant(TargetReg(kArg0), arg0); 212 ClobberCallerSave(); 213 CallHelper<pointer_size>(r_tgt, helper_offset, safepoint_pc); 214} 215INSTANTIATE(void Mir2Lir::CallRuntimeHelperImmReg, int arg0, RegStorage arg1, bool safepoint_pc) 216 217template <size_t pointer_size> 218void Mir2Lir::CallRuntimeHelperRegImm(ThreadOffset<pointer_size> helper_offset, RegStorage arg0, 219 int arg1, bool safepoint_pc) { 220 RegStorage r_tgt = CallHelperSetup(helper_offset); 221 OpRegCopy(TargetReg(kArg0), arg0); 222 LoadConstant(TargetReg(kArg1), arg1); 223 ClobberCallerSave(); 224 CallHelper<pointer_size>(r_tgt, helper_offset, safepoint_pc); 225} 226INSTANTIATE(void Mir2Lir::CallRuntimeHelperRegImm, RegStorage arg0, int arg1, bool safepoint_pc) 227 228template <size_t pointer_size> 229void Mir2Lir::CallRuntimeHelperImmMethod(ThreadOffset<pointer_size> helper_offset, int arg0, 230 bool safepoint_pc) { 231 RegStorage r_tgt = CallHelperSetup(helper_offset); 232 LoadCurrMethodDirect(TargetReg(kArg1)); 233 LoadConstant(TargetReg(kArg0), arg0); 234 ClobberCallerSave(); 235 CallHelper<pointer_size>(r_tgt, helper_offset, safepoint_pc); 236} 237INSTANTIATE(void Mir2Lir::CallRuntimeHelperImmMethod, int arg0, bool safepoint_pc) 238 239template <size_t pointer_size> 240void Mir2Lir::CallRuntimeHelperRegMethod(ThreadOffset<pointer_size> helper_offset, RegStorage arg0, 241 bool safepoint_pc) { 242 RegStorage r_tgt = CallHelperSetup(helper_offset); 243 DCHECK_NE(TargetReg(kArg1).GetReg(), arg0.GetReg()); 244 if (TargetReg(kArg0) != arg0) { 245 OpRegCopy(TargetReg(kArg0), arg0); 246 } 247 LoadCurrMethodDirect(TargetReg(kArg1)); 248 ClobberCallerSave(); 249 CallHelper<pointer_size>(r_tgt, helper_offset, safepoint_pc); 250} 251INSTANTIATE(void Mir2Lir::CallRuntimeHelperRegMethod, RegStorage arg0, bool safepoint_pc) 252 253template <size_t pointer_size> 254void Mir2Lir::CallRuntimeHelperRegMethodRegLocation(ThreadOffset<pointer_size> helper_offset, 255 RegStorage arg0, RegLocation arg2, 256 bool safepoint_pc) { 257 RegStorage r_tgt = CallHelperSetup(helper_offset); 258 DCHECK_NE(TargetReg(kArg1).GetReg(), arg0.GetReg()); 259 if (TargetReg(kArg0) != arg0) { 260 OpRegCopy(TargetReg(kArg0), arg0); 261 } 262 LoadCurrMethodDirect(TargetReg(kArg1)); 263 LoadValueDirectFixed(arg2, TargetReg(kArg2)); 264 ClobberCallerSave(); 265 CallHelper<pointer_size>(r_tgt, helper_offset, safepoint_pc); 266} 267INSTANTIATE(void Mir2Lir::CallRuntimeHelperRegMethodRegLocation, RegStorage arg0, RegLocation arg2, 268 bool safepoint_pc) 269 270template <size_t pointer_size> 271void Mir2Lir::CallRuntimeHelperRegLocationRegLocation(ThreadOffset<pointer_size> helper_offset, 272 RegLocation arg0, RegLocation arg1, 273 bool safepoint_pc) { 274 RegStorage r_tgt = CallHelperSetup(helper_offset); 275 if (arg0.wide == 0) { 276 LoadValueDirectFixed(arg0, arg0.fp ? TargetReg(kFArg0) : TargetReg(kArg0)); 277 if (arg1.wide == 0) { 278 if (cu_->instruction_set == kMips) { 279 LoadValueDirectFixed(arg1, arg1.fp ? TargetReg(kFArg2) : TargetReg(kArg1)); 280 } else { 281 LoadValueDirectFixed(arg1, TargetReg(kArg1)); 282 } 283 } else { 284 if (cu_->instruction_set == kMips) { 285 RegStorage r_tmp; 286 if (arg1.fp) { 287 r_tmp = RegStorage::MakeRegPair(TargetReg(kFArg2), TargetReg(kFArg3)); 288 } else { 289 r_tmp = RegStorage::MakeRegPair(TargetReg(kArg1), TargetReg(kArg2)); 290 } 291 LoadValueDirectWideFixed(arg1, r_tmp); 292 } else { 293 RegStorage r_tmp = RegStorage::MakeRegPair(TargetReg(kArg1), TargetReg(kArg2)); 294 LoadValueDirectWideFixed(arg1, r_tmp); 295 } 296 } 297 } else { 298 RegStorage r_tmp; 299 if (arg0.fp) { 300 r_tmp = RegStorage::MakeRegPair(TargetReg(kFArg0), TargetReg(kFArg1)); 301 } else { 302 r_tmp = RegStorage::MakeRegPair(TargetReg(kArg0), TargetReg(kArg1)); 303 } 304 LoadValueDirectWideFixed(arg0, r_tmp); 305 if (arg1.wide == 0) { 306 LoadValueDirectFixed(arg1, arg1.fp ? TargetReg(kFArg2) : TargetReg(kArg2)); 307 } else { 308 RegStorage r_tmp; 309 if (arg1.fp) { 310 r_tmp = RegStorage::MakeRegPair(TargetReg(kFArg2), TargetReg(kFArg3)); 311 } else { 312 r_tmp = RegStorage::MakeRegPair(TargetReg(kArg2), TargetReg(kArg3)); 313 } 314 LoadValueDirectWideFixed(arg1, r_tmp); 315 } 316 } 317 ClobberCallerSave(); 318 CallHelper<pointer_size>(r_tgt, helper_offset, safepoint_pc); 319} 320INSTANTIATE(void Mir2Lir::CallRuntimeHelperRegLocationRegLocation, RegLocation arg0, 321 RegLocation arg1, bool safepoint_pc) 322 323void Mir2Lir::CopyToArgumentRegs(RegStorage arg0, RegStorage arg1) { 324 if (arg1.GetReg() == TargetReg(kArg0).GetReg()) { 325 if (arg0.GetReg() == TargetReg(kArg1).GetReg()) { 326 // Swap kArg0 and kArg1 with kArg2 as temp. 327 OpRegCopy(TargetReg(kArg2), arg1); 328 OpRegCopy(TargetReg(kArg0), arg0); 329 OpRegCopy(TargetReg(kArg1), TargetReg(kArg2)); 330 } else { 331 OpRegCopy(TargetReg(kArg1), arg1); 332 OpRegCopy(TargetReg(kArg0), arg0); 333 } 334 } else { 335 OpRegCopy(TargetReg(kArg0), arg0); 336 OpRegCopy(TargetReg(kArg1), arg1); 337 } 338} 339 340template <size_t pointer_size> 341void Mir2Lir::CallRuntimeHelperRegReg(ThreadOffset<pointer_size> helper_offset, RegStorage arg0, 342 RegStorage arg1, bool safepoint_pc) { 343 RegStorage r_tgt = CallHelperSetup(helper_offset); 344 CopyToArgumentRegs(arg0, arg1); 345 ClobberCallerSave(); 346 CallHelper<pointer_size>(r_tgt, helper_offset, safepoint_pc); 347} 348INSTANTIATE(void Mir2Lir::CallRuntimeHelperRegReg, RegStorage arg0, RegStorage arg1, 349 bool safepoint_pc) 350 351template <size_t pointer_size> 352void Mir2Lir::CallRuntimeHelperRegRegImm(ThreadOffset<pointer_size> helper_offset, RegStorage arg0, 353 RegStorage arg1, int arg2, bool safepoint_pc) { 354 RegStorage r_tgt = CallHelperSetup(helper_offset); 355 CopyToArgumentRegs(arg0, arg1); 356 LoadConstant(TargetReg(kArg2), arg2); 357 ClobberCallerSave(); 358 CallHelper<pointer_size>(r_tgt, helper_offset, safepoint_pc); 359} 360INSTANTIATE(void Mir2Lir::CallRuntimeHelperRegRegImm, RegStorage arg0, RegStorage arg1, int arg2, 361 bool safepoint_pc) 362 363template <size_t pointer_size> 364void Mir2Lir::CallRuntimeHelperImmMethodRegLocation(ThreadOffset<pointer_size> helper_offset, 365 int arg0, RegLocation arg2, bool safepoint_pc) { 366 RegStorage r_tgt = CallHelperSetup(helper_offset); 367 LoadValueDirectFixed(arg2, TargetReg(kArg2)); 368 LoadCurrMethodDirect(TargetReg(kArg1)); 369 LoadConstant(TargetReg(kArg0), arg0); 370 ClobberCallerSave(); 371 CallHelper<pointer_size>(r_tgt, helper_offset, safepoint_pc); 372} 373INSTANTIATE(void Mir2Lir::CallRuntimeHelperImmMethodRegLocation, int arg0, RegLocation arg2, 374 bool safepoint_pc) 375 376template <size_t pointer_size> 377void Mir2Lir::CallRuntimeHelperImmMethodImm(ThreadOffset<pointer_size> helper_offset, int arg0, 378 int arg2, bool safepoint_pc) { 379 RegStorage r_tgt = CallHelperSetup(helper_offset); 380 LoadCurrMethodDirect(TargetReg(kArg1)); 381 LoadConstant(TargetReg(kArg2), arg2); 382 LoadConstant(TargetReg(kArg0), arg0); 383 ClobberCallerSave(); 384 CallHelper<pointer_size>(r_tgt, helper_offset, safepoint_pc); 385} 386INSTANTIATE(void Mir2Lir::CallRuntimeHelperImmMethodImm, int arg0, int arg2, bool safepoint_pc) 387 388template <size_t pointer_size> 389void Mir2Lir::CallRuntimeHelperImmRegLocationRegLocation(ThreadOffset<pointer_size> helper_offset, 390 int arg0, RegLocation arg1, 391 RegLocation arg2, bool safepoint_pc) { 392 RegStorage r_tgt = CallHelperSetup(helper_offset); 393 DCHECK_EQ(static_cast<unsigned int>(arg1.wide), 0U); // The static_cast works around an 394 // instantiation bug in GCC. 395 LoadValueDirectFixed(arg1, TargetReg(kArg1)); 396 if (arg2.wide == 0) { 397 LoadValueDirectFixed(arg2, TargetReg(kArg2)); 398 } else { 399 RegStorage r_tmp = RegStorage::MakeRegPair(TargetReg(kArg2), TargetReg(kArg3)); 400 LoadValueDirectWideFixed(arg2, r_tmp); 401 } 402 LoadConstant(TargetReg(kArg0), arg0); 403 ClobberCallerSave(); 404 CallHelper<pointer_size>(r_tgt, helper_offset, safepoint_pc); 405} 406INSTANTIATE(void Mir2Lir::CallRuntimeHelperImmRegLocationRegLocation, int arg0, RegLocation arg1, 407 RegLocation arg2, bool safepoint_pc) 408 409template <size_t pointer_size> 410void Mir2Lir::CallRuntimeHelperRegLocationRegLocationRegLocation(ThreadOffset<pointer_size> helper_offset, 411 RegLocation arg0, RegLocation arg1, 412 RegLocation arg2, 413 bool safepoint_pc) { 414 RegStorage r_tgt = CallHelperSetup(helper_offset); 415 DCHECK_EQ(static_cast<unsigned int>(arg0.wide), 0U); 416 LoadValueDirectFixed(arg0, TargetReg(kArg0)); 417 DCHECK_EQ(static_cast<unsigned int>(arg1.wide), 0U); 418 LoadValueDirectFixed(arg1, TargetReg(kArg1)); 419 DCHECK_EQ(static_cast<unsigned int>(arg1.wide), 0U); 420 LoadValueDirectFixed(arg2, TargetReg(kArg2)); 421 ClobberCallerSave(); 422 CallHelper<pointer_size>(r_tgt, helper_offset, safepoint_pc); 423} 424INSTANTIATE(void Mir2Lir::CallRuntimeHelperRegLocationRegLocationRegLocation, RegLocation arg0, 425 RegLocation arg1, RegLocation arg2, bool safepoint_pc) 426 427/* 428 * If there are any ins passed in registers that have not been promoted 429 * to a callee-save register, flush them to the frame. Perform initial 430 * assignment of promoted arguments. 431 * 432 * ArgLocs is an array of location records describing the incoming arguments 433 * with one location record per word of argument. 434 */ 435void Mir2Lir::FlushIns(RegLocation* ArgLocs, RegLocation rl_method) { 436 /* 437 * Dummy up a RegLocation for the incoming Method* 438 * It will attempt to keep kArg0 live (or copy it to home location 439 * if promoted). 440 */ 441 RegLocation rl_src = rl_method; 442 rl_src.location = kLocPhysReg; 443 rl_src.reg = TargetReg(kArg0); 444 rl_src.home = false; 445 MarkLive(rl_src); 446 if (rl_method.wide) { 447 StoreValueWide(rl_method, rl_src); 448 } else { 449 StoreValue(rl_method, rl_src); 450 } 451 // If Method* has been promoted, explicitly flush 452 if (rl_method.location == kLocPhysReg) { 453 StoreWordDisp(TargetReg(kSp), 0, TargetReg(kArg0)); 454 } 455 456 if (cu_->num_ins == 0) { 457 return; 458 } 459 460 int start_vreg = cu_->num_dalvik_registers - cu_->num_ins; 461 /* 462 * Copy incoming arguments to their proper home locations. 463 * NOTE: an older version of dx had an issue in which 464 * it would reuse static method argument registers. 465 * This could result in the same Dalvik virtual register 466 * being promoted to both core and fp regs. To account for this, 467 * we only copy to the corresponding promoted physical register 468 * if it matches the type of the SSA name for the incoming 469 * argument. It is also possible that long and double arguments 470 * end up half-promoted. In those cases, we must flush the promoted 471 * half to memory as well. 472 */ 473 for (int i = 0; i < cu_->num_ins; i++) { 474 PromotionMap* v_map = &promotion_map_[start_vreg + i]; 475 RegStorage reg = GetArgMappingToPhysicalReg(i); 476 477 if (reg.Valid()) { 478 // If arriving in register 479 bool need_flush = true; 480 RegLocation* t_loc = &ArgLocs[i]; 481 if ((v_map->core_location == kLocPhysReg) && !t_loc->fp) { 482 OpRegCopy(RegStorage::Solo32(v_map->core_reg), reg); 483 need_flush = false; 484 } else if ((v_map->fp_location == kLocPhysReg) && t_loc->fp) { 485 OpRegCopy(RegStorage::Solo32(v_map->FpReg), reg); 486 need_flush = false; 487 } else { 488 need_flush = true; 489 } 490 491 // For wide args, force flush if not fully promoted 492 if (t_loc->wide) { 493 PromotionMap* p_map = v_map + (t_loc->high_word ? -1 : +1); 494 // Is only half promoted? 495 need_flush |= (p_map->core_location != v_map->core_location) || 496 (p_map->fp_location != v_map->fp_location); 497 if ((cu_->instruction_set == kThumb2) && t_loc->fp && !need_flush) { 498 /* 499 * In Arm, a double is represented as a pair of consecutive single float 500 * registers starting at an even number. It's possible that both Dalvik vRegs 501 * representing the incoming double were independently promoted as singles - but 502 * not in a form usable as a double. If so, we need to flush - even though the 503 * incoming arg appears fully in register. At this point in the code, both 504 * halves of the double are promoted. Make sure they are in a usable form. 505 */ 506 int lowreg_index = start_vreg + i + (t_loc->high_word ? -1 : 0); 507 int low_reg = promotion_map_[lowreg_index].FpReg; 508 int high_reg = promotion_map_[lowreg_index + 1].FpReg; 509 if (((low_reg & 0x1) != 0) || (high_reg != (low_reg + 1))) { 510 need_flush = true; 511 } 512 } 513 } 514 if (need_flush) { 515 Store32Disp(TargetReg(kSp), SRegOffset(start_vreg + i), reg); 516 } 517 } else { 518 // If arriving in frame & promoted 519 if (v_map->core_location == kLocPhysReg) { 520 Load32Disp(TargetReg(kSp), SRegOffset(start_vreg + i), RegStorage::Solo32(v_map->core_reg)); 521 } 522 if (v_map->fp_location == kLocPhysReg) { 523 Load32Disp(TargetReg(kSp), SRegOffset(start_vreg + i), RegStorage::Solo32(v_map->FpReg)); 524 } 525 } 526 } 527} 528 529/* 530 * Bit of a hack here - in the absence of a real scheduling pass, 531 * emit the next instruction in static & direct invoke sequences. 532 */ 533static int NextSDCallInsn(CompilationUnit* cu, CallInfo* info, 534 int state, const MethodReference& target_method, 535 uint32_t unused, 536 uintptr_t direct_code, uintptr_t direct_method, 537 InvokeType type) { 538 Mir2Lir* cg = static_cast<Mir2Lir*>(cu->cg.get()); 539 if (direct_code != 0 && direct_method != 0) { 540 switch (state) { 541 case 0: // Get the current Method* [sets kArg0] 542 if (direct_code != static_cast<uintptr_t>(-1)) { 543 if (cu->instruction_set != kX86 && cu->instruction_set != kX86_64) { 544 cg->LoadConstant(cg->TargetReg(kInvokeTgt), direct_code); 545 } 546 } else if (cu->instruction_set != kX86 && cu->instruction_set != kX86_64) { 547 cg->LoadCodeAddress(target_method, type, kInvokeTgt); 548 } 549 if (direct_method != static_cast<uintptr_t>(-1)) { 550 cg->LoadConstant(cg->TargetReg(kArg0), direct_method); 551 } else { 552 cg->LoadMethodAddress(target_method, type, kArg0); 553 } 554 break; 555 default: 556 return -1; 557 } 558 } else { 559 switch (state) { 560 case 0: // Get the current Method* [sets kArg0] 561 // TUNING: we can save a reg copy if Method* has been promoted. 562 cg->LoadCurrMethodDirect(cg->TargetReg(kArg0)); 563 break; 564 case 1: // Get method->dex_cache_resolved_methods_ 565 cg->LoadRefDisp(cg->TargetReg(kArg0), 566 mirror::ArtMethod::DexCacheResolvedMethodsOffset().Int32Value(), 567 cg->TargetReg(kArg0)); 568 // Set up direct code if known. 569 if (direct_code != 0) { 570 if (direct_code != static_cast<uintptr_t>(-1)) { 571 cg->LoadConstant(cg->TargetReg(kInvokeTgt), direct_code); 572 } else if (cu->instruction_set != kX86 && cu->instruction_set != kX86_64) { 573 CHECK_LT(target_method.dex_method_index, target_method.dex_file->NumMethodIds()); 574 cg->LoadCodeAddress(target_method, type, kInvokeTgt); 575 } 576 } 577 break; 578 case 2: // Grab target method* 579 CHECK_EQ(cu->dex_file, target_method.dex_file); 580 cg->LoadRefDisp(cg->TargetReg(kArg0), 581 ObjArray::OffsetOfElement(target_method.dex_method_index).Int32Value(), 582 cg->TargetReg(kArg0)); 583 break; 584 case 3: // Grab the code from the method* 585 if (cu->instruction_set != kX86 && cu->instruction_set != kX86_64) { 586 if (direct_code == 0) { 587 cg->LoadWordDisp(cg->TargetReg(kArg0), 588 mirror::ArtMethod::EntryPointFromQuickCompiledCodeOffset().Int32Value(), 589 cg->TargetReg(kInvokeTgt)); 590 } 591 break; 592 } 593 // Intentional fallthrough for x86 594 default: 595 return -1; 596 } 597 } 598 return state + 1; 599} 600 601/* 602 * Bit of a hack here - in the absence of a real scheduling pass, 603 * emit the next instruction in a virtual invoke sequence. 604 * We can use kLr as a temp prior to target address loading 605 * Note also that we'll load the first argument ("this") into 606 * kArg1 here rather than the standard LoadArgRegs. 607 */ 608static int NextVCallInsn(CompilationUnit* cu, CallInfo* info, 609 int state, const MethodReference& target_method, 610 uint32_t method_idx, uintptr_t unused, uintptr_t unused2, 611 InvokeType unused3) { 612 Mir2Lir* cg = static_cast<Mir2Lir*>(cu->cg.get()); 613 /* 614 * This is the fast path in which the target virtual method is 615 * fully resolved at compile time. 616 */ 617 switch (state) { 618 case 0: { // Get "this" [set kArg1] 619 RegLocation rl_arg = info->args[0]; 620 cg->LoadValueDirectFixed(rl_arg, cg->TargetReg(kArg1)); 621 break; 622 } 623 case 1: // Is "this" null? [use kArg1] 624 cg->GenNullCheck(cg->TargetReg(kArg1), info->opt_flags); 625 // get this->klass_ [use kArg1, set kInvokeTgt] 626 cg->LoadRefDisp(cg->TargetReg(kArg1), mirror::Object::ClassOffset().Int32Value(), 627 cg->TargetReg(kInvokeTgt)); 628 cg->MarkPossibleNullPointerException(info->opt_flags); 629 break; 630 case 2: // Get this->klass_->vtable [usr kInvokeTgt, set kInvokeTgt] 631 cg->LoadRefDisp(cg->TargetReg(kInvokeTgt), mirror::Class::VTableOffset().Int32Value(), 632 cg->TargetReg(kInvokeTgt)); 633 break; 634 case 3: // Get target method [use kInvokeTgt, set kArg0] 635 cg->LoadRefDisp(cg->TargetReg(kInvokeTgt), 636 ObjArray::OffsetOfElement(method_idx).Int32Value(), 637 cg->TargetReg(kArg0)); 638 break; 639 case 4: // Get the compiled code address [uses kArg0, sets kInvokeTgt] 640 if (cu->instruction_set != kX86 && cu->instruction_set != kX86_64) { 641 cg->LoadWordDisp(cg->TargetReg(kArg0), 642 mirror::ArtMethod::EntryPointFromQuickCompiledCodeOffset().Int32Value(), 643 cg->TargetReg(kInvokeTgt)); 644 break; 645 } 646 // Intentional fallthrough for X86 647 default: 648 return -1; 649 } 650 return state + 1; 651} 652 653/* 654 * Emit the next instruction in an invoke interface sequence. This will do a lookup in the 655 * class's IMT, calling either the actual method or art_quick_imt_conflict_trampoline if 656 * more than one interface method map to the same index. Note also that we'll load the first 657 * argument ("this") into kArg1 here rather than the standard LoadArgRegs. 658 */ 659static int NextInterfaceCallInsn(CompilationUnit* cu, CallInfo* info, int state, 660 const MethodReference& target_method, 661 uint32_t method_idx, uintptr_t unused, 662 uintptr_t direct_method, InvokeType unused2) { 663 Mir2Lir* cg = static_cast<Mir2Lir*>(cu->cg.get()); 664 665 switch (state) { 666 case 0: // Set target method index in case of conflict [set kHiddenArg, kHiddenFpArg (x86)] 667 CHECK_LT(target_method.dex_method_index, target_method.dex_file->NumMethodIds()); 668 cg->LoadConstant(cg->TargetReg(kHiddenArg), target_method.dex_method_index); 669 if (cu->instruction_set == kX86 || cu->instruction_set == kX86_64) { 670 cg->OpRegCopy(cg->TargetReg(kHiddenFpArg), cg->TargetReg(kHiddenArg)); 671 } 672 break; 673 case 1: { // Get "this" [set kArg1] 674 RegLocation rl_arg = info->args[0]; 675 cg->LoadValueDirectFixed(rl_arg, cg->TargetReg(kArg1)); 676 break; 677 } 678 case 2: // Is "this" null? [use kArg1] 679 cg->GenNullCheck(cg->TargetReg(kArg1), info->opt_flags); 680 // Get this->klass_ [use kArg1, set kInvokeTgt] 681 cg->LoadRefDisp(cg->TargetReg(kArg1), mirror::Object::ClassOffset().Int32Value(), 682 cg->TargetReg(kInvokeTgt)); 683 cg->MarkPossibleNullPointerException(info->opt_flags); 684 break; 685 case 3: // Get this->klass_->imtable [use kInvokeTgt, set kInvokeTgt] 686 // NOTE: native pointer. 687 cg->LoadRefDisp(cg->TargetReg(kInvokeTgt), mirror::Class::ImTableOffset().Int32Value(), 688 cg->TargetReg(kInvokeTgt)); 689 break; 690 case 4: // Get target method [use kInvokeTgt, set kArg0] 691 // NOTE: native pointer. 692 cg->LoadRefDisp(cg->TargetReg(kInvokeTgt), 693 ObjArray::OffsetOfElement(method_idx % ClassLinker::kImtSize).Int32Value(), 694 cg->TargetReg(kArg0)); 695 break; 696 case 5: // Get the compiled code address [use kArg0, set kInvokeTgt] 697 if (cu->instruction_set != kX86 && cu->instruction_set != kX86_64) { 698 cg->LoadWordDisp(cg->TargetReg(kArg0), 699 mirror::ArtMethod::EntryPointFromQuickCompiledCodeOffset().Int32Value(), 700 cg->TargetReg(kInvokeTgt)); 701 break; 702 } 703 // Intentional fallthrough for X86 704 default: 705 return -1; 706 } 707 return state + 1; 708} 709 710template <size_t pointer_size> 711static int NextInvokeInsnSP(CompilationUnit* cu, CallInfo* info, ThreadOffset<pointer_size> trampoline, 712 int state, const MethodReference& target_method, 713 uint32_t method_idx) { 714 Mir2Lir* cg = static_cast<Mir2Lir*>(cu->cg.get()); 715 /* 716 * This handles the case in which the base method is not fully 717 * resolved at compile time, we bail to a runtime helper. 718 */ 719 if (state == 0) { 720 if (cu->instruction_set != kX86 && cu->instruction_set != kX86_64) { 721 // Load trampoline target 722 cg->LoadWordDisp(cg->TargetReg(kSelf), trampoline.Int32Value(), cg->TargetReg(kInvokeTgt)); 723 } 724 // Load kArg0 with method index 725 CHECK_EQ(cu->dex_file, target_method.dex_file); 726 cg->LoadConstant(cg->TargetReg(kArg0), target_method.dex_method_index); 727 return 1; 728 } 729 return -1; 730} 731 732static int NextStaticCallInsnSP(CompilationUnit* cu, CallInfo* info, 733 int state, 734 const MethodReference& target_method, 735 uint32_t unused, uintptr_t unused2, 736 uintptr_t unused3, InvokeType unused4) { 737 if (Is64BitInstructionSet(cu->instruction_set)) { 738 ThreadOffset<8> trampoline = QUICK_ENTRYPOINT_OFFSET(8, pInvokeStaticTrampolineWithAccessCheck); 739 return NextInvokeInsnSP<8>(cu, info, trampoline, state, target_method, 0); 740 } else { 741 ThreadOffset<4> trampoline = QUICK_ENTRYPOINT_OFFSET(4, pInvokeStaticTrampolineWithAccessCheck); 742 return NextInvokeInsnSP<4>(cu, info, trampoline, state, target_method, 0); 743 } 744} 745 746static int NextDirectCallInsnSP(CompilationUnit* cu, CallInfo* info, int state, 747 const MethodReference& target_method, 748 uint32_t unused, uintptr_t unused2, 749 uintptr_t unused3, InvokeType unused4) { 750 if (Is64BitInstructionSet(cu->instruction_set)) { 751 ThreadOffset<8> trampoline = QUICK_ENTRYPOINT_OFFSET(8, pInvokeDirectTrampolineWithAccessCheck); 752 return NextInvokeInsnSP<8>(cu, info, trampoline, state, target_method, 0); 753 } else { 754 ThreadOffset<4> trampoline = QUICK_ENTRYPOINT_OFFSET(4, pInvokeDirectTrampolineWithAccessCheck); 755 return NextInvokeInsnSP<4>(cu, info, trampoline, state, target_method, 0); 756 } 757} 758 759static int NextSuperCallInsnSP(CompilationUnit* cu, CallInfo* info, int state, 760 const MethodReference& target_method, 761 uint32_t unused, uintptr_t unused2, 762 uintptr_t unused3, InvokeType unused4) { 763 if (Is64BitInstructionSet(cu->instruction_set)) { 764 ThreadOffset<8> trampoline = QUICK_ENTRYPOINT_OFFSET(8, pInvokeSuperTrampolineWithAccessCheck); 765 return NextInvokeInsnSP<8>(cu, info, trampoline, state, target_method, 0); 766 } else { 767 ThreadOffset<4> trampoline = QUICK_ENTRYPOINT_OFFSET(4, pInvokeSuperTrampolineWithAccessCheck); 768 return NextInvokeInsnSP<4>(cu, info, trampoline, state, target_method, 0); 769 } 770} 771 772static int NextVCallInsnSP(CompilationUnit* cu, CallInfo* info, int state, 773 const MethodReference& target_method, 774 uint32_t unused, uintptr_t unused2, 775 uintptr_t unused3, InvokeType unused4) { 776 if (Is64BitInstructionSet(cu->instruction_set)) { 777 ThreadOffset<8> trampoline = QUICK_ENTRYPOINT_OFFSET(8, pInvokeVirtualTrampolineWithAccessCheck); 778 return NextInvokeInsnSP<8>(cu, info, trampoline, state, target_method, 0); 779 } else { 780 ThreadOffset<4> trampoline = QUICK_ENTRYPOINT_OFFSET(4, pInvokeVirtualTrampolineWithAccessCheck); 781 return NextInvokeInsnSP<4>(cu, info, trampoline, state, target_method, 0); 782 } 783} 784 785static int NextInterfaceCallInsnWithAccessCheck(CompilationUnit* cu, 786 CallInfo* info, int state, 787 const MethodReference& target_method, 788 uint32_t unused, uintptr_t unused2, 789 uintptr_t unused3, InvokeType unused4) { 790 if (Is64BitInstructionSet(cu->instruction_set)) { 791 ThreadOffset<8> trampoline = QUICK_ENTRYPOINT_OFFSET(8, pInvokeInterfaceTrampolineWithAccessCheck); 792 return NextInvokeInsnSP<8>(cu, info, trampoline, state, target_method, 0); 793 } else { 794 ThreadOffset<4> trampoline = QUICK_ENTRYPOINT_OFFSET(4, pInvokeInterfaceTrampolineWithAccessCheck); 795 return NextInvokeInsnSP<4>(cu, info, trampoline, state, target_method, 0); 796 } 797} 798 799int Mir2Lir::LoadArgRegs(CallInfo* info, int call_state, 800 NextCallInsn next_call_insn, 801 const MethodReference& target_method, 802 uint32_t vtable_idx, uintptr_t direct_code, 803 uintptr_t direct_method, InvokeType type, bool skip_this) { 804 int last_arg_reg = TargetReg(kArg3).GetReg(); 805 int next_reg = TargetReg(kArg1).GetReg(); 806 int next_arg = 0; 807 if (skip_this) { 808 next_reg++; 809 next_arg++; 810 } 811 for (; (next_reg <= last_arg_reg) && (next_arg < info->num_arg_words); next_reg++) { 812 RegLocation rl_arg = info->args[next_arg++]; 813 rl_arg = UpdateRawLoc(rl_arg); 814 if (rl_arg.wide && (next_reg <= TargetReg(kArg2).GetReg())) { 815 RegStorage r_tmp(RegStorage::k64BitPair, next_reg, next_reg + 1); 816 LoadValueDirectWideFixed(rl_arg, r_tmp); 817 next_reg++; 818 next_arg++; 819 } else { 820 if (rl_arg.wide) { 821 rl_arg = NarrowRegLoc(rl_arg); 822 rl_arg.is_const = false; 823 } 824 LoadValueDirectFixed(rl_arg, RegStorage::Solo32(next_reg)); 825 } 826 call_state = next_call_insn(cu_, info, call_state, target_method, vtable_idx, 827 direct_code, direct_method, type); 828 } 829 return call_state; 830} 831 832/* 833 * Load up to 5 arguments, the first three of which will be in 834 * kArg1 .. kArg3. On entry kArg0 contains the current method pointer, 835 * and as part of the load sequence, it must be replaced with 836 * the target method pointer. Note, this may also be called 837 * for "range" variants if the number of arguments is 5 or fewer. 838 */ 839int Mir2Lir::GenDalvikArgsNoRange(CallInfo* info, 840 int call_state, LIR** pcrLabel, NextCallInsn next_call_insn, 841 const MethodReference& target_method, 842 uint32_t vtable_idx, uintptr_t direct_code, 843 uintptr_t direct_method, InvokeType type, bool skip_this) { 844 RegLocation rl_arg; 845 846 /* If no arguments, just return */ 847 if (info->num_arg_words == 0) 848 return call_state; 849 850 call_state = next_call_insn(cu_, info, call_state, target_method, vtable_idx, 851 direct_code, direct_method, type); 852 853 DCHECK_LE(info->num_arg_words, 5); 854 if (info->num_arg_words > 3) { 855 int32_t next_use = 3; 856 // Detect special case of wide arg spanning arg3/arg4 857 RegLocation rl_use0 = info->args[0]; 858 RegLocation rl_use1 = info->args[1]; 859 RegLocation rl_use2 = info->args[2]; 860 if (((!rl_use0.wide && !rl_use1.wide) || rl_use0.wide) && rl_use2.wide) { 861 RegStorage reg; 862 // Wide spans, we need the 2nd half of uses[2]. 863 rl_arg = UpdateLocWide(rl_use2); 864 if (rl_arg.location == kLocPhysReg) { 865 // NOTE: not correct for 64-bit core regs, but this needs rewriting for hard-float. 866 reg = rl_arg.reg.IsPair() ? rl_arg.reg.GetHigh() : rl_arg.reg.DoubleToHighSingle(); 867 } else { 868 // kArg2 & rArg3 can safely be used here 869 reg = TargetReg(kArg3); 870 Load32Disp(TargetReg(kSp), SRegOffset(rl_arg.s_reg_low) + 4, reg); 871 call_state = next_call_insn(cu_, info, call_state, target_method, 872 vtable_idx, direct_code, direct_method, type); 873 } 874 Store32Disp(TargetReg(kSp), (next_use + 1) * 4, reg); 875 call_state = next_call_insn(cu_, info, call_state, target_method, vtable_idx, 876 direct_code, direct_method, type); 877 next_use++; 878 } 879 // Loop through the rest 880 while (next_use < info->num_arg_words) { 881 RegStorage arg_reg; 882 rl_arg = info->args[next_use]; 883 rl_arg = UpdateRawLoc(rl_arg); 884 if (rl_arg.location == kLocPhysReg) { 885 arg_reg = rl_arg.reg; 886 } else { 887 arg_reg = rl_arg.wide ? RegStorage::MakeRegPair(TargetReg(kArg2), TargetReg(kArg3)) : 888 TargetReg(kArg2); 889 if (rl_arg.wide) { 890 LoadValueDirectWideFixed(rl_arg, arg_reg); 891 } else { 892 LoadValueDirectFixed(rl_arg, arg_reg); 893 } 894 call_state = next_call_insn(cu_, info, call_state, target_method, 895 vtable_idx, direct_code, direct_method, type); 896 } 897 int outs_offset = (next_use + 1) * 4; 898 if (rl_arg.wide) { 899 StoreBaseDisp(TargetReg(kSp), outs_offset, arg_reg, k64); 900 next_use += 2; 901 } else { 902 Store32Disp(TargetReg(kSp), outs_offset, arg_reg); 903 next_use++; 904 } 905 call_state = next_call_insn(cu_, info, call_state, target_method, vtable_idx, 906 direct_code, direct_method, type); 907 } 908 } 909 910 call_state = LoadArgRegs(info, call_state, next_call_insn, 911 target_method, vtable_idx, direct_code, direct_method, 912 type, skip_this); 913 914 if (pcrLabel) { 915 if (Runtime::Current()->ExplicitNullChecks()) { 916 *pcrLabel = GenExplicitNullCheck(TargetReg(kArg1), info->opt_flags); 917 } else { 918 *pcrLabel = nullptr; 919 // In lieu of generating a check for kArg1 being null, we need to 920 // perform a load when doing implicit checks. 921 RegStorage tmp = AllocTemp(); 922 Load32Disp(TargetReg(kArg1), 0, tmp); 923 MarkPossibleNullPointerException(info->opt_flags); 924 FreeTemp(tmp); 925 } 926 } 927 return call_state; 928} 929 930/* 931 * May have 0+ arguments (also used for jumbo). Note that 932 * source virtual registers may be in physical registers, so may 933 * need to be flushed to home location before copying. This 934 * applies to arg3 and above (see below). 935 * 936 * Two general strategies: 937 * If < 20 arguments 938 * Pass args 3-18 using vldm/vstm block copy 939 * Pass arg0, arg1 & arg2 in kArg1-kArg3 940 * If 20+ arguments 941 * Pass args arg19+ using memcpy block copy 942 * Pass arg0, arg1 & arg2 in kArg1-kArg3 943 * 944 */ 945int Mir2Lir::GenDalvikArgsRange(CallInfo* info, int call_state, 946 LIR** pcrLabel, NextCallInsn next_call_insn, 947 const MethodReference& target_method, 948 uint32_t vtable_idx, uintptr_t direct_code, uintptr_t direct_method, 949 InvokeType type, bool skip_this) { 950 // If we can treat it as non-range (Jumbo ops will use range form) 951 if (info->num_arg_words <= 5) 952 return GenDalvikArgsNoRange(info, call_state, pcrLabel, 953 next_call_insn, target_method, vtable_idx, 954 direct_code, direct_method, type, skip_this); 955 /* 956 * First load the non-register arguments. Both forms expect all 957 * of the source arguments to be in their home frame location, so 958 * scan the s_reg names and flush any that have been promoted to 959 * frame backing storage. 960 */ 961 // Scan the rest of the args - if in phys_reg flush to memory 962 for (int next_arg = 0; next_arg < info->num_arg_words;) { 963 RegLocation loc = info->args[next_arg]; 964 if (loc.wide) { 965 loc = UpdateLocWide(loc); 966 if ((next_arg >= 2) && (loc.location == kLocPhysReg)) { 967 StoreBaseDisp(TargetReg(kSp), SRegOffset(loc.s_reg_low), loc.reg, k64); 968 } 969 next_arg += 2; 970 } else { 971 loc = UpdateLoc(loc); 972 if ((next_arg >= 3) && (loc.location == kLocPhysReg)) { 973 Store32Disp(TargetReg(kSp), SRegOffset(loc.s_reg_low), loc.reg); 974 } 975 next_arg++; 976 } 977 } 978 979 // Logic below assumes that Method pointer is at offset zero from SP. 980 DCHECK_EQ(VRegOffset(static_cast<int>(kVRegMethodPtrBaseReg)), 0); 981 982 // The first 3 arguments are passed via registers. 983 // TODO: For 64-bit, instead of hardcoding 4 for Method* size, we should either 984 // get size of uintptr_t or size of object reference according to model being used. 985 int outs_offset = 4 /* Method* */ + (3 * sizeof(uint32_t)); 986 int start_offset = SRegOffset(info->args[3].s_reg_low); 987 int regs_left_to_pass_via_stack = info->num_arg_words - 3; 988 DCHECK_GT(regs_left_to_pass_via_stack, 0); 989 990 if (cu_->instruction_set == kThumb2 && regs_left_to_pass_via_stack <= 16) { 991 // Use vldm/vstm pair using kArg3 as a temp 992 call_state = next_call_insn(cu_, info, call_state, target_method, vtable_idx, 993 direct_code, direct_method, type); 994 OpRegRegImm(kOpAdd, TargetReg(kArg3), TargetReg(kSp), start_offset); 995 LIR* ld = OpVldm(TargetReg(kArg3), regs_left_to_pass_via_stack); 996 // TUNING: loosen barrier 997 ld->u.m.def_mask = ENCODE_ALL; 998 SetMemRefType(ld, true /* is_load */, kDalvikReg); 999 call_state = next_call_insn(cu_, info, call_state, target_method, vtable_idx, 1000 direct_code, direct_method, type); 1001 OpRegRegImm(kOpAdd, TargetReg(kArg3), TargetReg(kSp), 4 /* Method* */ + (3 * 4)); 1002 call_state = next_call_insn(cu_, info, call_state, target_method, vtable_idx, 1003 direct_code, direct_method, type); 1004 LIR* st = OpVstm(TargetReg(kArg3), regs_left_to_pass_via_stack); 1005 SetMemRefType(st, false /* is_load */, kDalvikReg); 1006 st->u.m.def_mask = ENCODE_ALL; 1007 call_state = next_call_insn(cu_, info, call_state, target_method, vtable_idx, 1008 direct_code, direct_method, type); 1009 } else if (cu_->instruction_set == kX86 || cu_->instruction_set == kX86_64) { 1010 int current_src_offset = start_offset; 1011 int current_dest_offset = outs_offset; 1012 1013 while (regs_left_to_pass_via_stack > 0) { 1014 // This is based on the knowledge that the stack itself is 16-byte aligned. 1015 bool src_is_16b_aligned = (current_src_offset & 0xF) == 0; 1016 bool dest_is_16b_aligned = (current_dest_offset & 0xF) == 0; 1017 size_t bytes_to_move; 1018 1019 /* 1020 * The amount to move defaults to 32-bit. If there are 4 registers left to move, then do a 1021 * a 128-bit move because we won't get the chance to try to aligned. If there are more than 1022 * 4 registers left to move, consider doing a 128-bit only if either src or dest are aligned. 1023 * We do this because we could potentially do a smaller move to align. 1024 */ 1025 if (regs_left_to_pass_via_stack == 4 || 1026 (regs_left_to_pass_via_stack > 4 && (src_is_16b_aligned || dest_is_16b_aligned))) { 1027 // Moving 128-bits via xmm register. 1028 bytes_to_move = sizeof(uint32_t) * 4; 1029 1030 // Allocate a free xmm temp. Since we are working through the calling sequence, 1031 // we expect to have an xmm temporary available. 1032 RegStorage temp = AllocTempDouble(); 1033 DCHECK(temp.Valid()); 1034 1035 LIR* ld1 = nullptr; 1036 LIR* ld2 = nullptr; 1037 LIR* st1 = nullptr; 1038 LIR* st2 = nullptr; 1039 1040 /* 1041 * The logic is similar for both loads and stores. If we have 16-byte alignment, 1042 * do an aligned move. If we have 8-byte alignment, then do the move in two 1043 * parts. This approach prevents possible cache line splits. Finally, fall back 1044 * to doing an unaligned move. In most cases we likely won't split the cache 1045 * line but we cannot prove it and thus take a conservative approach. 1046 */ 1047 bool src_is_8b_aligned = (current_src_offset & 0x7) == 0; 1048 bool dest_is_8b_aligned = (current_dest_offset & 0x7) == 0; 1049 1050 if (src_is_16b_aligned) { 1051 ld1 = OpMovRegMem(temp, TargetReg(kSp), current_src_offset, kMovA128FP); 1052 } else if (src_is_8b_aligned) { 1053 ld1 = OpMovRegMem(temp, TargetReg(kSp), current_src_offset, kMovLo128FP); 1054 ld2 = OpMovRegMem(temp, TargetReg(kSp), current_src_offset + (bytes_to_move >> 1), 1055 kMovHi128FP); 1056 } else { 1057 ld1 = OpMovRegMem(temp, TargetReg(kSp), current_src_offset, kMovU128FP); 1058 } 1059 1060 if (dest_is_16b_aligned) { 1061 st1 = OpMovMemReg(TargetReg(kSp), current_dest_offset, temp, kMovA128FP); 1062 } else if (dest_is_8b_aligned) { 1063 st1 = OpMovMemReg(TargetReg(kSp), current_dest_offset, temp, kMovLo128FP); 1064 st2 = OpMovMemReg(TargetReg(kSp), current_dest_offset + (bytes_to_move >> 1), 1065 temp, kMovHi128FP); 1066 } else { 1067 st1 = OpMovMemReg(TargetReg(kSp), current_dest_offset, temp, kMovU128FP); 1068 } 1069 1070 // TODO If we could keep track of aliasing information for memory accesses that are wider 1071 // than 64-bit, we wouldn't need to set up a barrier. 1072 if (ld1 != nullptr) { 1073 if (ld2 != nullptr) { 1074 // For 64-bit load we can actually set up the aliasing information. 1075 AnnotateDalvikRegAccess(ld1, current_src_offset >> 2, true, true); 1076 AnnotateDalvikRegAccess(ld2, (current_src_offset + (bytes_to_move >> 1)) >> 2, true, true); 1077 } else { 1078 // Set barrier for 128-bit load. 1079 SetMemRefType(ld1, true /* is_load */, kDalvikReg); 1080 ld1->u.m.def_mask = ENCODE_ALL; 1081 } 1082 } 1083 if (st1 != nullptr) { 1084 if (st2 != nullptr) { 1085 // For 64-bit store we can actually set up the aliasing information. 1086 AnnotateDalvikRegAccess(st1, current_dest_offset >> 2, false, true); 1087 AnnotateDalvikRegAccess(st2, (current_dest_offset + (bytes_to_move >> 1)) >> 2, false, true); 1088 } else { 1089 // Set barrier for 128-bit store. 1090 SetMemRefType(st1, false /* is_load */, kDalvikReg); 1091 st1->u.m.def_mask = ENCODE_ALL; 1092 } 1093 } 1094 1095 // Free the temporary used for the data movement. 1096 FreeTemp(temp); 1097 } else { 1098 // Moving 32-bits via general purpose register. 1099 bytes_to_move = sizeof(uint32_t); 1100 1101 // Instead of allocating a new temp, simply reuse one of the registers being used 1102 // for argument passing. 1103 RegStorage temp = TargetReg(kArg3); 1104 1105 // Now load the argument VR and store to the outs. 1106 Load32Disp(TargetReg(kSp), current_src_offset, temp); 1107 Store32Disp(TargetReg(kSp), current_dest_offset, temp); 1108 } 1109 1110 current_src_offset += bytes_to_move; 1111 current_dest_offset += bytes_to_move; 1112 regs_left_to_pass_via_stack -= (bytes_to_move >> 2); 1113 } 1114 } else { 1115 // Generate memcpy 1116 OpRegRegImm(kOpAdd, TargetReg(kArg0), TargetReg(kSp), outs_offset); 1117 OpRegRegImm(kOpAdd, TargetReg(kArg1), TargetReg(kSp), start_offset); 1118 if (Is64BitInstructionSet(cu_->instruction_set)) { 1119 CallRuntimeHelperRegRegImm(QUICK_ENTRYPOINT_OFFSET(8, pMemcpy), TargetReg(kArg0), 1120 TargetReg(kArg1), (info->num_arg_words - 3) * 4, false); 1121 } else { 1122 CallRuntimeHelperRegRegImm(QUICK_ENTRYPOINT_OFFSET(4, pMemcpy), TargetReg(kArg0), 1123 TargetReg(kArg1), (info->num_arg_words - 3) * 4, false); 1124 } 1125 } 1126 1127 call_state = LoadArgRegs(info, call_state, next_call_insn, 1128 target_method, vtable_idx, direct_code, direct_method, 1129 type, skip_this); 1130 1131 call_state = next_call_insn(cu_, info, call_state, target_method, vtable_idx, 1132 direct_code, direct_method, type); 1133 if (pcrLabel) { 1134 if (Runtime::Current()->ExplicitNullChecks()) { 1135 *pcrLabel = GenExplicitNullCheck(TargetReg(kArg1), info->opt_flags); 1136 } else { 1137 *pcrLabel = nullptr; 1138 // In lieu of generating a check for kArg1 being null, we need to 1139 // perform a load when doing implicit checks. 1140 RegStorage tmp = AllocTemp(); 1141 Load32Disp(TargetReg(kArg1), 0, tmp); 1142 MarkPossibleNullPointerException(info->opt_flags); 1143 FreeTemp(tmp); 1144 } 1145 } 1146 return call_state; 1147} 1148 1149RegLocation Mir2Lir::InlineTarget(CallInfo* info) { 1150 RegLocation res; 1151 if (info->result.location == kLocInvalid) { 1152 res = GetReturn(false); 1153 } else { 1154 res = info->result; 1155 } 1156 return res; 1157} 1158 1159RegLocation Mir2Lir::InlineTargetWide(CallInfo* info) { 1160 RegLocation res; 1161 if (info->result.location == kLocInvalid) { 1162 res = GetReturnWide(false); 1163 } else { 1164 res = info->result; 1165 } 1166 return res; 1167} 1168 1169bool Mir2Lir::GenInlinedCharAt(CallInfo* info) { 1170 if (cu_->instruction_set == kMips) { 1171 // TODO - add Mips implementation 1172 return false; 1173 } 1174 // Location of reference to data array 1175 int value_offset = mirror::String::ValueOffset().Int32Value(); 1176 // Location of count 1177 int count_offset = mirror::String::CountOffset().Int32Value(); 1178 // Starting offset within data array 1179 int offset_offset = mirror::String::OffsetOffset().Int32Value(); 1180 // Start of char data with array_ 1181 int data_offset = mirror::Array::DataOffset(sizeof(uint16_t)).Int32Value(); 1182 1183 RegLocation rl_obj = info->args[0]; 1184 RegLocation rl_idx = info->args[1]; 1185 rl_obj = LoadValue(rl_obj, kCoreReg); 1186 // X86 wants to avoid putting a constant index into a register. 1187 if (!((cu_->instruction_set == kX86 || cu_->instruction_set == kX86_64)&& rl_idx.is_const)) { 1188 rl_idx = LoadValue(rl_idx, kCoreReg); 1189 } 1190 RegStorage reg_max; 1191 GenNullCheck(rl_obj.reg, info->opt_flags); 1192 bool range_check = (!(info->opt_flags & MIR_IGNORE_RANGE_CHECK)); 1193 LIR* range_check_branch = nullptr; 1194 RegStorage reg_off; 1195 RegStorage reg_ptr; 1196 if (cu_->instruction_set != kX86 && cu_->instruction_set != kX86_64) { 1197 reg_off = AllocTemp(); 1198 reg_ptr = AllocTemp(); 1199 if (range_check) { 1200 reg_max = AllocTemp(); 1201 Load32Disp(rl_obj.reg, count_offset, reg_max); 1202 MarkPossibleNullPointerException(info->opt_flags); 1203 } 1204 Load32Disp(rl_obj.reg, offset_offset, reg_off); 1205 MarkPossibleNullPointerException(info->opt_flags); 1206 Load32Disp(rl_obj.reg, value_offset, reg_ptr); 1207 if (range_check) { 1208 // Set up a slow path to allow retry in case of bounds violation */ 1209 OpRegReg(kOpCmp, rl_idx.reg, reg_max); 1210 FreeTemp(reg_max); 1211 range_check_branch = OpCondBranch(kCondUge, nullptr); 1212 } 1213 OpRegImm(kOpAdd, reg_ptr, data_offset); 1214 } else { 1215 if (range_check) { 1216 // On x86, we can compare to memory directly 1217 // Set up a launch pad to allow retry in case of bounds violation */ 1218 if (rl_idx.is_const) { 1219 range_check_branch = OpCmpMemImmBranch( 1220 kCondUlt, RegStorage::InvalidReg(), rl_obj.reg, count_offset, 1221 mir_graph_->ConstantValue(rl_idx.orig_sreg), nullptr); 1222 } else { 1223 OpRegMem(kOpCmp, rl_idx.reg, rl_obj.reg, count_offset); 1224 range_check_branch = OpCondBranch(kCondUge, nullptr); 1225 } 1226 } 1227 reg_off = AllocTemp(); 1228 reg_ptr = AllocTemp(); 1229 Load32Disp(rl_obj.reg, offset_offset, reg_off); 1230 Load32Disp(rl_obj.reg, value_offset, reg_ptr); 1231 } 1232 if (rl_idx.is_const) { 1233 OpRegImm(kOpAdd, reg_off, mir_graph_->ConstantValue(rl_idx.orig_sreg)); 1234 } else { 1235 OpRegReg(kOpAdd, reg_off, rl_idx.reg); 1236 } 1237 FreeTemp(rl_obj.reg); 1238 if (rl_idx.location == kLocPhysReg) { 1239 FreeTemp(rl_idx.reg); 1240 } 1241 RegLocation rl_dest = InlineTarget(info); 1242 RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); 1243 if (cu_->instruction_set != kX86 && cu_->instruction_set != kX86_64) { 1244 LoadBaseIndexed(reg_ptr, reg_off, rl_result.reg, 1, kUnsignedHalf); 1245 } else { 1246 LoadBaseIndexedDisp(reg_ptr, reg_off, 1, data_offset, rl_result.reg, kUnsignedHalf); 1247 } 1248 FreeTemp(reg_off); 1249 FreeTemp(reg_ptr); 1250 StoreValue(rl_dest, rl_result); 1251 if (range_check) { 1252 DCHECK(range_check_branch != nullptr); 1253 info->opt_flags |= MIR_IGNORE_NULL_CHECK; // Record that we've already null checked. 1254 AddIntrinsicSlowPath(info, range_check_branch); 1255 } 1256 return true; 1257} 1258 1259// Generates an inlined String.is_empty or String.length. 1260bool Mir2Lir::GenInlinedStringIsEmptyOrLength(CallInfo* info, bool is_empty) { 1261 if (cu_->instruction_set == kMips) { 1262 // TODO - add Mips implementation 1263 return false; 1264 } 1265 // dst = src.length(); 1266 RegLocation rl_obj = info->args[0]; 1267 rl_obj = LoadValue(rl_obj, kCoreReg); 1268 RegLocation rl_dest = InlineTarget(info); 1269 RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); 1270 GenNullCheck(rl_obj.reg, info->opt_flags); 1271 Load32Disp(rl_obj.reg, mirror::String::CountOffset().Int32Value(), rl_result.reg); 1272 MarkPossibleNullPointerException(info->opt_flags); 1273 if (is_empty) { 1274 // dst = (dst == 0); 1275 if (cu_->instruction_set == kThumb2) { 1276 RegStorage t_reg = AllocTemp(); 1277 OpRegReg(kOpNeg, t_reg, rl_result.reg); 1278 OpRegRegReg(kOpAdc, rl_result.reg, rl_result.reg, t_reg); 1279 } else { 1280 DCHECK(cu_->instruction_set == kX86 || cu_->instruction_set == kX86_64); 1281 OpRegImm(kOpSub, rl_result.reg, 1); 1282 OpRegImm(kOpLsr, rl_result.reg, 31); 1283 } 1284 } 1285 StoreValue(rl_dest, rl_result); 1286 return true; 1287} 1288 1289bool Mir2Lir::GenInlinedReverseBytes(CallInfo* info, OpSize size) { 1290 if (cu_->instruction_set == kMips) { 1291 // TODO - add Mips implementation 1292 return false; 1293 } 1294 RegLocation rl_src_i = info->args[0]; 1295 RegLocation rl_dest = (size == k64) ? InlineTargetWide(info) : InlineTarget(info); // result reg 1296 RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); 1297 if (size == k64) { 1298 RegLocation rl_i = LoadValueWide(rl_src_i, kCoreReg); 1299 RegStorage r_i_low = rl_i.reg.GetLow(); 1300 if (rl_i.reg.GetLowReg() == rl_result.reg.GetLowReg()) { 1301 // First REV shall clobber rl_result.reg.GetReg(), save the value in a temp for the second REV. 1302 r_i_low = AllocTemp(); 1303 OpRegCopy(r_i_low, rl_i.reg); 1304 } 1305 OpRegReg(kOpRev, rl_result.reg.GetLow(), rl_i.reg.GetHigh()); 1306 OpRegReg(kOpRev, rl_result.reg.GetHigh(), r_i_low); 1307 if (rl_i.reg.GetLowReg() == rl_result.reg.GetLowReg()) { 1308 FreeTemp(r_i_low); 1309 } 1310 StoreValueWide(rl_dest, rl_result); 1311 } else { 1312 DCHECK(size == k32 || size == kSignedHalf); 1313 OpKind op = (size == k32) ? kOpRev : kOpRevsh; 1314 RegLocation rl_i = LoadValue(rl_src_i, kCoreReg); 1315 OpRegReg(op, rl_result.reg, rl_i.reg); 1316 StoreValue(rl_dest, rl_result); 1317 } 1318 return true; 1319} 1320 1321bool Mir2Lir::GenInlinedAbsInt(CallInfo* info) { 1322 if (cu_->instruction_set == kMips) { 1323 // TODO - add Mips implementation 1324 return false; 1325 } 1326 RegLocation rl_src = info->args[0]; 1327 rl_src = LoadValue(rl_src, kCoreReg); 1328 RegLocation rl_dest = InlineTarget(info); 1329 RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); 1330 RegStorage sign_reg = AllocTemp(); 1331 // abs(x) = y<=x>>31, (x+y)^y. 1332 OpRegRegImm(kOpAsr, sign_reg, rl_src.reg, 31); 1333 OpRegRegReg(kOpAdd, rl_result.reg, rl_src.reg, sign_reg); 1334 OpRegReg(kOpXor, rl_result.reg, sign_reg); 1335 StoreValue(rl_dest, rl_result); 1336 return true; 1337} 1338 1339bool Mir2Lir::GenInlinedAbsLong(CallInfo* info) { 1340 if (cu_->instruction_set == kMips) { 1341 // TODO - add Mips implementation 1342 return false; 1343 } 1344 RegLocation rl_src = info->args[0]; 1345 rl_src = LoadValueWide(rl_src, kCoreReg); 1346 RegLocation rl_dest = InlineTargetWide(info); 1347 RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); 1348 1349 // If on x86 or if we would clobber a register needed later, just copy the source first. 1350 if (cu_->instruction_set == kX86 || cu_->instruction_set == kX86_64 || rl_result.reg.GetLowReg() == rl_src.reg.GetHighReg()) { 1351 OpRegCopyWide(rl_result.reg, rl_src.reg); 1352 if (rl_result.reg.GetLowReg() != rl_src.reg.GetLowReg() && 1353 rl_result.reg.GetLowReg() != rl_src.reg.GetHighReg() && 1354 rl_result.reg.GetHighReg() != rl_src.reg.GetLowReg() && 1355 rl_result.reg.GetHighReg() != rl_src.reg.GetHighReg()) { 1356 // Reuse source registers to avoid running out of temps. 1357 FreeTemp(rl_src.reg); 1358 } 1359 rl_src = rl_result; 1360 } 1361 1362 // abs(x) = y<=x>>31, (x+y)^y. 1363 RegStorage sign_reg = AllocTemp(); 1364 OpRegRegImm(kOpAsr, sign_reg, rl_src.reg.GetHigh(), 31); 1365 OpRegRegReg(kOpAdd, rl_result.reg.GetLow(), rl_src.reg.GetLow(), sign_reg); 1366 OpRegRegReg(kOpAdc, rl_result.reg.GetHigh(), rl_src.reg.GetHigh(), sign_reg); 1367 OpRegReg(kOpXor, rl_result.reg.GetLow(), sign_reg); 1368 OpRegReg(kOpXor, rl_result.reg.GetHigh(), sign_reg); 1369 StoreValueWide(rl_dest, rl_result); 1370 return true; 1371} 1372 1373bool Mir2Lir::GenInlinedAbsFloat(CallInfo* info) { 1374 if (cu_->instruction_set == kMips) { 1375 // TODO - add Mips implementation 1376 return false; 1377 } 1378 RegLocation rl_src = info->args[0]; 1379 rl_src = LoadValue(rl_src, kCoreReg); 1380 RegLocation rl_dest = InlineTarget(info); 1381 RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); 1382 OpRegRegImm(kOpAnd, rl_result.reg, rl_src.reg, 0x7fffffff); 1383 StoreValue(rl_dest, rl_result); 1384 return true; 1385} 1386 1387bool Mir2Lir::GenInlinedAbsDouble(CallInfo* info) { 1388 if (cu_->instruction_set == kMips) { 1389 // TODO - add Mips implementation 1390 return false; 1391 } 1392 RegLocation rl_src = info->args[0]; 1393 rl_src = LoadValueWide(rl_src, kCoreReg); 1394 RegLocation rl_dest = InlineTargetWide(info); 1395 RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); 1396 OpRegCopyWide(rl_result.reg, rl_src.reg); 1397 OpRegImm(kOpAnd, rl_result.reg.GetHigh(), 0x7fffffff); 1398 StoreValueWide(rl_dest, rl_result); 1399 return true; 1400} 1401 1402bool Mir2Lir::GenInlinedFloatCvt(CallInfo* info) { 1403 if (cu_->instruction_set == kMips) { 1404 // TODO - add Mips implementation 1405 return false; 1406 } 1407 RegLocation rl_src = info->args[0]; 1408 RegLocation rl_dest = InlineTarget(info); 1409 StoreValue(rl_dest, rl_src); 1410 return true; 1411} 1412 1413bool Mir2Lir::GenInlinedDoubleCvt(CallInfo* info) { 1414 if (cu_->instruction_set == kMips) { 1415 // TODO - add Mips implementation 1416 return false; 1417 } 1418 RegLocation rl_src = info->args[0]; 1419 RegLocation rl_dest = InlineTargetWide(info); 1420 StoreValueWide(rl_dest, rl_src); 1421 return true; 1422} 1423 1424/* 1425 * Fast String.indexOf(I) & (II). Tests for simple case of char <= 0xFFFF, 1426 * otherwise bails to standard library code. 1427 */ 1428bool Mir2Lir::GenInlinedIndexOf(CallInfo* info, bool zero_based) { 1429 if (cu_->instruction_set == kMips) { 1430 // TODO - add Mips implementation 1431 return false; 1432 } 1433 RegLocation rl_obj = info->args[0]; 1434 RegLocation rl_char = info->args[1]; 1435 if (rl_char.is_const && (mir_graph_->ConstantValue(rl_char) & ~0xFFFF) != 0) { 1436 // Code point beyond 0xFFFF. Punt to the real String.indexOf(). 1437 return false; 1438 } 1439 1440 ClobberCallerSave(); 1441 LockCallTemps(); // Using fixed registers 1442 RegStorage reg_ptr = TargetReg(kArg0); 1443 RegStorage reg_char = TargetReg(kArg1); 1444 RegStorage reg_start = TargetReg(kArg2); 1445 1446 LoadValueDirectFixed(rl_obj, reg_ptr); 1447 LoadValueDirectFixed(rl_char, reg_char); 1448 if (zero_based) { 1449 LoadConstant(reg_start, 0); 1450 } else { 1451 RegLocation rl_start = info->args[2]; // 3rd arg only present in III flavor of IndexOf. 1452 LoadValueDirectFixed(rl_start, reg_start); 1453 } 1454 RegStorage r_tgt = Is64BitInstructionSet(cu_->instruction_set) ? 1455 LoadHelper(QUICK_ENTRYPOINT_OFFSET(8, pIndexOf)) : 1456 LoadHelper(QUICK_ENTRYPOINT_OFFSET(4, pIndexOf)); 1457 GenExplicitNullCheck(reg_ptr, info->opt_flags); 1458 LIR* high_code_point_branch = 1459 rl_char.is_const ? nullptr : OpCmpImmBranch(kCondGt, reg_char, 0xFFFF, nullptr); 1460 // NOTE: not a safepoint 1461 OpReg(kOpBlx, r_tgt); 1462 if (!rl_char.is_const) { 1463 // Add the slow path for code points beyond 0xFFFF. 1464 DCHECK(high_code_point_branch != nullptr); 1465 LIR* resume_tgt = NewLIR0(kPseudoTargetLabel); 1466 info->opt_flags |= MIR_IGNORE_NULL_CHECK; // Record that we've null checked. 1467 AddIntrinsicSlowPath(info, high_code_point_branch, resume_tgt); 1468 } else { 1469 DCHECK_EQ(mir_graph_->ConstantValue(rl_char) & ~0xFFFF, 0); 1470 DCHECK(high_code_point_branch == nullptr); 1471 } 1472 RegLocation rl_return = GetReturn(false); 1473 RegLocation rl_dest = InlineTarget(info); 1474 StoreValue(rl_dest, rl_return); 1475 return true; 1476} 1477 1478/* Fast string.compareTo(Ljava/lang/string;)I. */ 1479bool Mir2Lir::GenInlinedStringCompareTo(CallInfo* info) { 1480 if (cu_->instruction_set == kMips) { 1481 // TODO - add Mips implementation 1482 return false; 1483 } 1484 ClobberCallerSave(); 1485 LockCallTemps(); // Using fixed registers 1486 RegStorage reg_this = TargetReg(kArg0); 1487 RegStorage reg_cmp = TargetReg(kArg1); 1488 1489 RegLocation rl_this = info->args[0]; 1490 RegLocation rl_cmp = info->args[1]; 1491 LoadValueDirectFixed(rl_this, reg_this); 1492 LoadValueDirectFixed(rl_cmp, reg_cmp); 1493 RegStorage r_tgt; 1494 if (cu_->instruction_set != kX86 && cu_->instruction_set != kX86_64) { 1495 if (Is64BitInstructionSet(cu_->instruction_set)) { 1496 r_tgt = LoadHelper(QUICK_ENTRYPOINT_OFFSET(8, pStringCompareTo)); 1497 } else { 1498 r_tgt = LoadHelper(QUICK_ENTRYPOINT_OFFSET(4, pStringCompareTo)); 1499 } 1500 } else { 1501 r_tgt = RegStorage::InvalidReg(); 1502 } 1503 GenExplicitNullCheck(reg_this, info->opt_flags); 1504 info->opt_flags |= MIR_IGNORE_NULL_CHECK; // Record that we've null checked. 1505 // TUNING: check if rl_cmp.s_reg_low is already null checked 1506 LIR* cmp_null_check_branch = OpCmpImmBranch(kCondEq, reg_cmp, 0, nullptr); 1507 AddIntrinsicSlowPath(info, cmp_null_check_branch); 1508 // NOTE: not a safepoint 1509 if (cu_->instruction_set != kX86 && cu_->instruction_set != kX86_64) { 1510 OpReg(kOpBlx, r_tgt); 1511 } else { 1512 if (Is64BitInstructionSet(cu_->instruction_set)) { 1513 OpThreadMem(kOpBlx, QUICK_ENTRYPOINT_OFFSET(8, pStringCompareTo)); 1514 } else { 1515 OpThreadMem(kOpBlx, QUICK_ENTRYPOINT_OFFSET(4, pStringCompareTo)); 1516 } 1517 } 1518 RegLocation rl_return = GetReturn(false); 1519 RegLocation rl_dest = InlineTarget(info); 1520 StoreValue(rl_dest, rl_return); 1521 return true; 1522} 1523 1524bool Mir2Lir::GenInlinedCurrentThread(CallInfo* info) { 1525 RegLocation rl_dest = InlineTarget(info); 1526 RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); 1527 1528 switch (cu_->instruction_set) { 1529 case kArm: 1530 // Fall-through. 1531 case kThumb2: 1532 // Fall-through. 1533 case kMips: 1534 Load32Disp(TargetReg(kSelf), Thread::PeerOffset<4>().Int32Value(), rl_result.reg); 1535 break; 1536 1537 case kArm64: 1538 Load32Disp(TargetReg(kSelf), Thread::PeerOffset<8>().Int32Value(), rl_result.reg); 1539 break; 1540 1541 case kX86: 1542 reinterpret_cast<X86Mir2Lir*>(this)->OpRegThreadMem(kOpMov, rl_result.reg, 1543 Thread::PeerOffset<4>()); 1544 break; 1545 1546 case kX86_64: 1547 reinterpret_cast<X86Mir2Lir*>(this)->OpRegThreadMem(kOpMov, rl_result.reg, 1548 Thread::PeerOffset<8>()); 1549 break; 1550 1551 default: 1552 LOG(FATAL) << "Unexpected isa " << cu_->instruction_set; 1553 } 1554 StoreValue(rl_dest, rl_result); 1555 return true; 1556} 1557 1558bool Mir2Lir::GenInlinedUnsafeGet(CallInfo* info, 1559 bool is_long, bool is_volatile) { 1560 if (cu_->instruction_set == kMips) { 1561 // TODO - add Mips implementation 1562 return false; 1563 } 1564 // Unused - RegLocation rl_src_unsafe = info->args[0]; 1565 RegLocation rl_src_obj = info->args[1]; // Object 1566 RegLocation rl_src_offset = info->args[2]; // long low 1567 rl_src_offset = NarrowRegLoc(rl_src_offset); // ignore high half in info->args[3] 1568 RegLocation rl_dest = is_long ? InlineTargetWide(info) : InlineTarget(info); // result reg 1569 1570 RegLocation rl_object = LoadValue(rl_src_obj, kCoreReg); 1571 RegLocation rl_offset = LoadValue(rl_src_offset, kCoreReg); 1572 RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); 1573 if (is_long) { 1574 if (cu_->instruction_set == kX86 || cu_->instruction_set == kX86_64) { 1575 LoadBaseIndexedDisp(rl_object.reg, rl_offset.reg, 0, 0, rl_result.reg, k64); 1576 } else { 1577 RegStorage rl_temp_offset = AllocTemp(); 1578 OpRegRegReg(kOpAdd, rl_temp_offset, rl_object.reg, rl_offset.reg); 1579 LoadBaseDisp(rl_temp_offset, 0, rl_result.reg, k64); 1580 FreeTemp(rl_temp_offset); 1581 } 1582 } else { 1583 LoadBaseIndexed(rl_object.reg, rl_offset.reg, rl_result.reg, 0, k32); 1584 } 1585 1586 if (is_volatile) { 1587 // Without context sensitive analysis, we must issue the most conservative barriers. 1588 // In this case, either a load or store may follow so we issue both barriers. 1589 GenMemBarrier(kLoadLoad); 1590 GenMemBarrier(kLoadStore); 1591 } 1592 1593 if (is_long) { 1594 StoreValueWide(rl_dest, rl_result); 1595 } else { 1596 StoreValue(rl_dest, rl_result); 1597 } 1598 return true; 1599} 1600 1601bool Mir2Lir::GenInlinedUnsafePut(CallInfo* info, bool is_long, 1602 bool is_object, bool is_volatile, bool is_ordered) { 1603 if (cu_->instruction_set == kMips) { 1604 // TODO - add Mips implementation 1605 return false; 1606 } 1607 // Unused - RegLocation rl_src_unsafe = info->args[0]; 1608 RegLocation rl_src_obj = info->args[1]; // Object 1609 RegLocation rl_src_offset = info->args[2]; // long low 1610 rl_src_offset = NarrowRegLoc(rl_src_offset); // ignore high half in info->args[3] 1611 RegLocation rl_src_value = info->args[4]; // value to store 1612 if (is_volatile || is_ordered) { 1613 // There might have been a store before this volatile one so insert StoreStore barrier. 1614 GenMemBarrier(kStoreStore); 1615 } 1616 RegLocation rl_object = LoadValue(rl_src_obj, kCoreReg); 1617 RegLocation rl_offset = LoadValue(rl_src_offset, kCoreReg); 1618 RegLocation rl_value; 1619 if (is_long) { 1620 rl_value = LoadValueWide(rl_src_value, kCoreReg); 1621 if (cu_->instruction_set == kX86 || cu_->instruction_set == kX86_64) { 1622 StoreBaseIndexedDisp(rl_object.reg, rl_offset.reg, 0, 0, rl_value.reg, k64); 1623 } else { 1624 RegStorage rl_temp_offset = AllocTemp(); 1625 OpRegRegReg(kOpAdd, rl_temp_offset, rl_object.reg, rl_offset.reg); 1626 StoreBaseDisp(rl_temp_offset, 0, rl_value.reg, k64); 1627 FreeTemp(rl_temp_offset); 1628 } 1629 } else { 1630 rl_value = LoadValue(rl_src_value, kCoreReg); 1631 StoreBaseIndexed(rl_object.reg, rl_offset.reg, rl_value.reg, 0, k32); 1632 } 1633 1634 // Free up the temp early, to ensure x86 doesn't run out of temporaries in MarkGCCard. 1635 FreeTemp(rl_offset.reg); 1636 1637 if (is_volatile) { 1638 // A load might follow the volatile store so insert a StoreLoad barrier. 1639 GenMemBarrier(kStoreLoad); 1640 } 1641 if (is_object) { 1642 MarkGCCard(rl_value.reg, rl_object.reg); 1643 } 1644 return true; 1645} 1646 1647void Mir2Lir::GenInvoke(CallInfo* info) { 1648 if ((info->opt_flags & MIR_INLINED) != 0) { 1649 // Already inlined but we may still need the null check. 1650 if (info->type != kStatic && 1651 ((cu_->disable_opt & (1 << kNullCheckElimination)) != 0 || 1652 (info->opt_flags & MIR_IGNORE_NULL_CHECK) == 0)) { 1653 RegLocation rl_obj = LoadValue(info->args[0], kCoreReg); 1654 GenNullCheck(rl_obj.reg); 1655 } 1656 return; 1657 } 1658 DCHECK(cu_->compiler_driver->GetMethodInlinerMap() != nullptr); 1659 if (cu_->compiler_driver->GetMethodInlinerMap()->GetMethodInliner(cu_->dex_file) 1660 ->GenIntrinsic(this, info)) { 1661 return; 1662 } 1663 GenInvokeNoInline(info); 1664} 1665 1666template <size_t pointer_size> 1667static LIR* GenInvokeNoInlineCall(Mir2Lir* mir_to_lir, InvokeType type) { 1668 ThreadOffset<pointer_size> trampoline(-1); 1669 switch (type) { 1670 case kInterface: 1671 trampoline = QUICK_ENTRYPOINT_OFFSET(pointer_size, pInvokeInterfaceTrampolineWithAccessCheck); 1672 break; 1673 case kDirect: 1674 trampoline = QUICK_ENTRYPOINT_OFFSET(pointer_size, pInvokeDirectTrampolineWithAccessCheck); 1675 break; 1676 case kStatic: 1677 trampoline = QUICK_ENTRYPOINT_OFFSET(pointer_size, pInvokeStaticTrampolineWithAccessCheck); 1678 break; 1679 case kSuper: 1680 trampoline = QUICK_ENTRYPOINT_OFFSET(pointer_size, pInvokeSuperTrampolineWithAccessCheck); 1681 break; 1682 case kVirtual: 1683 trampoline = QUICK_ENTRYPOINT_OFFSET(pointer_size, pInvokeVirtualTrampolineWithAccessCheck); 1684 break; 1685 default: 1686 LOG(FATAL) << "Unexpected invoke type"; 1687 } 1688 return mir_to_lir->OpThreadMem(kOpBlx, trampoline); 1689} 1690 1691void Mir2Lir::GenInvokeNoInline(CallInfo* info) { 1692 int call_state = 0; 1693 LIR* null_ck; 1694 LIR** p_null_ck = NULL; 1695 NextCallInsn next_call_insn; 1696 FlushAllRegs(); /* Everything to home location */ 1697 // Explicit register usage 1698 LockCallTemps(); 1699 1700 const MirMethodLoweringInfo& method_info = mir_graph_->GetMethodLoweringInfo(info->mir); 1701 cu_->compiler_driver->ProcessedInvoke(method_info.GetInvokeType(), method_info.StatsFlags()); 1702 InvokeType original_type = static_cast<InvokeType>(method_info.GetInvokeType()); 1703 info->type = static_cast<InvokeType>(method_info.GetSharpType()); 1704 bool fast_path = method_info.FastPath(); 1705 bool skip_this; 1706 if (info->type == kInterface) { 1707 next_call_insn = fast_path ? NextInterfaceCallInsn : NextInterfaceCallInsnWithAccessCheck; 1708 skip_this = fast_path; 1709 } else if (info->type == kDirect) { 1710 if (fast_path) { 1711 p_null_ck = &null_ck; 1712 } 1713 next_call_insn = fast_path ? NextSDCallInsn : NextDirectCallInsnSP; 1714 skip_this = false; 1715 } else if (info->type == kStatic) { 1716 next_call_insn = fast_path ? NextSDCallInsn : NextStaticCallInsnSP; 1717 skip_this = false; 1718 } else if (info->type == kSuper) { 1719 DCHECK(!fast_path); // Fast path is a direct call. 1720 next_call_insn = NextSuperCallInsnSP; 1721 skip_this = false; 1722 } else { 1723 DCHECK_EQ(info->type, kVirtual); 1724 next_call_insn = fast_path ? NextVCallInsn : NextVCallInsnSP; 1725 skip_this = fast_path; 1726 } 1727 MethodReference target_method = method_info.GetTargetMethod(); 1728 if (!info->is_range) { 1729 call_state = GenDalvikArgsNoRange(info, call_state, p_null_ck, 1730 next_call_insn, target_method, method_info.VTableIndex(), 1731 method_info.DirectCode(), method_info.DirectMethod(), 1732 original_type, skip_this); 1733 } else { 1734 call_state = GenDalvikArgsRange(info, call_state, p_null_ck, 1735 next_call_insn, target_method, method_info.VTableIndex(), 1736 method_info.DirectCode(), method_info.DirectMethod(), 1737 original_type, skip_this); 1738 } 1739 // Finish up any of the call sequence not interleaved in arg loading 1740 while (call_state >= 0) { 1741 call_state = next_call_insn(cu_, info, call_state, target_method, method_info.VTableIndex(), 1742 method_info.DirectCode(), method_info.DirectMethod(), original_type); 1743 } 1744 LIR* call_inst; 1745 if (cu_->instruction_set != kX86 && cu_->instruction_set != kX86_64) { 1746 call_inst = OpReg(kOpBlx, TargetReg(kInvokeTgt)); 1747 } else { 1748 if (fast_path) { 1749 if (method_info.DirectCode() == static_cast<uintptr_t>(-1)) { 1750 // We can have the linker fixup a call relative. 1751 call_inst = 1752 reinterpret_cast<X86Mir2Lir*>(this)->CallWithLinkerFixup(target_method, info->type); 1753 } else { 1754 call_inst = OpMem(kOpBlx, TargetReg(kArg0), 1755 mirror::ArtMethod::EntryPointFromQuickCompiledCodeOffset().Int32Value()); 1756 } 1757 } else { 1758 // TODO: Extract? 1759 if (Is64BitInstructionSet(cu_->instruction_set)) { 1760 call_inst = GenInvokeNoInlineCall<8>(this, info->type); 1761 } else { 1762 call_inst = GenInvokeNoInlineCall<4>(this, info->type); 1763 } 1764 } 1765 } 1766 MarkSafepointPC(call_inst); 1767 1768 ClobberCallerSave(); 1769 if (info->result.location != kLocInvalid) { 1770 // We have a following MOVE_RESULT - do it now. 1771 if (info->result.wide) { 1772 RegLocation ret_loc = GetReturnWide(info->result.fp); 1773 StoreValueWide(info->result, ret_loc); 1774 } else { 1775 RegLocation ret_loc = GetReturn(info->result.fp); 1776 StoreValue(info->result, ret_loc); 1777 } 1778 } 1779} 1780 1781} // namespace art 1782