gen_invoke.cc revision 7c2ad5af0bdd3cc1069038f8e3422d99aeb5f44c 
1/*
2 * Copyright (C) 2012 The Android Open Source Project
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 *      http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16
17#include "arm/codegen_arm.h"
18#include "dex/compiler_ir.h"
19#include "dex/frontend.h"
20#include "dex/quick/dex_file_method_inliner.h"
21#include "dex/quick/dex_file_to_method_inliner_map.h"
22#include "dex_file-inl.h"
23#include "entrypoints/quick/quick_entrypoints.h"
24#include "invoke_type.h"
25#include "mirror/array.h"
26#include "mirror/class-inl.h"
27#include "mirror/dex_cache.h"
28#include "mirror/object_array-inl.h"
29#include "mirror/string.h"
30#include "mir_to_lir-inl.h"
31#include "scoped_thread_state_change.h"
32
33namespace art {
34
35// Shortcuts to repeatedly used long types.
36typedef mirror::ObjectArray<mirror::Object> ObjArray;
37
38/*
39 * This source files contains "gen" codegen routines that should
40 * be applicable to most targets.  Only mid-level support utilities
41 * and "op" calls may be used here.
42 */
43
44void Mir2Lir::AddIntrinsicSlowPath(CallInfo* info, LIR* branch, LIR* resume) {
45  class IntrinsicSlowPathPath : public Mir2Lir::LIRSlowPath {
46   public:
47    IntrinsicSlowPathPath(Mir2Lir* m2l, CallInfo* info, LIR* branch, LIR* resume = nullptr)
48        : LIRSlowPath(m2l, info->offset, branch, resume), info_(info) {
49    }
50
51    void Compile() {
52      m2l_->ResetRegPool();
53      m2l_->ResetDefTracking();
54      GenerateTargetLabel(kPseudoIntrinsicRetry);
55      // NOTE: GenInvokeNoInline() handles MarkSafepointPC.
56      m2l_->GenInvokeNoInline(info_);
57      if (cont_ != nullptr) {
58        m2l_->OpUnconditionalBranch(cont_);
59      }
60    }
61
62   private:
63    CallInfo* const info_;
64  };
65
66  AddSlowPath(new (arena_) IntrinsicSlowPathPath(this, info, branch, resume));
67}
68
69/*
70 * To save scheduling time, helper calls are broken into two parts: generation of
71 * the helper target address, and the actual call to the helper.  Because x86
72 * has a memory call operation, part 1 is a NOP for x86.  For other targets,
73 * load arguments between the two parts.
74 */
75// template <size_t pointer_size>
76RegStorage Mir2Lir::CallHelperSetup(QuickEntrypointEnum trampoline) {
77  if (cu_->instruction_set == kX86 || cu_->instruction_set == kX86_64) {
78    return RegStorage::InvalidReg();
79  } else {
80    return LoadHelper(trampoline);
81  }
82}
83
84LIR* Mir2Lir::CallHelper(RegStorage r_tgt, QuickEntrypointEnum trampoline, bool safepoint_pc,
85                         bool use_link) {
86  LIR* call_inst = InvokeTrampoline(use_link ? kOpBlx : kOpBx, r_tgt, trampoline);
87
88  if (r_tgt.Valid()) {
89    FreeTemp(r_tgt);
90  }
91
92  if (safepoint_pc) {
93    MarkSafepointPC(call_inst);
94  }
95  return call_inst;
96}
97
98void Mir2Lir::CallRuntimeHelper(QuickEntrypointEnum trampoline, bool safepoint_pc) {
99  RegStorage r_tgt = CallHelperSetup(trampoline);
100  ClobberCallerSave();
101  CallHelper(r_tgt, trampoline, safepoint_pc);
102}
103
104void Mir2Lir::CallRuntimeHelperImm(QuickEntrypointEnum trampoline, int arg0, bool safepoint_pc) {
105  RegStorage r_tgt = CallHelperSetup(trampoline);
106  LoadConstant(TargetReg(kArg0, kNotWide), arg0);
107  ClobberCallerSave();
108  CallHelper(r_tgt, trampoline, safepoint_pc);
109}
110
111void Mir2Lir::CallRuntimeHelperReg(QuickEntrypointEnum trampoline, RegStorage arg0,
112                                   bool safepoint_pc) {
113  RegStorage r_tgt = CallHelperSetup(trampoline);
114  OpRegCopy(TargetReg(kArg0, arg0.GetWideKind()), arg0);
115  ClobberCallerSave();
116  CallHelper(r_tgt, trampoline, safepoint_pc);
117}
118
119void Mir2Lir::CallRuntimeHelperRegLocation(QuickEntrypointEnum trampoline, RegLocation arg0,
120                                           bool safepoint_pc) {
121  RegStorage r_tgt = CallHelperSetup(trampoline);
122  if (arg0.wide == 0) {
123    LoadValueDirectFixed(arg0, TargetReg(arg0.fp ? kFArg0 : kArg0, arg0));
124  } else {
125    LoadValueDirectWideFixed(arg0, TargetReg(arg0.fp ? kFArg0 : kArg0, kWide));
126  }
127  ClobberCallerSave();
128  CallHelper(r_tgt, trampoline, safepoint_pc);
129}
130
131void Mir2Lir::CallRuntimeHelperImmImm(QuickEntrypointEnum trampoline, int arg0, int arg1,
132                                      bool safepoint_pc) {
133  RegStorage r_tgt = CallHelperSetup(trampoline);
134  LoadConstant(TargetReg(kArg0, kNotWide), arg0);
135  LoadConstant(TargetReg(kArg1, kNotWide), arg1);
136  ClobberCallerSave();
137  CallHelper(r_tgt, trampoline, safepoint_pc);
138}
139
140void Mir2Lir::CallRuntimeHelperImmRegLocation(QuickEntrypointEnum trampoline, int arg0,
141                                              RegLocation arg1, bool safepoint_pc) {
142  RegStorage r_tgt = CallHelperSetup(trampoline);
143  if (arg1.wide == 0) {
144    LoadValueDirectFixed(arg1, TargetReg(kArg1, arg1));
145  } else {
146    RegStorage r_tmp = TargetReg(cu_->instruction_set == kMips ? kArg2 : kArg1, kWide);
147    LoadValueDirectWideFixed(arg1, r_tmp);
148  }
149  LoadConstant(TargetReg(kArg0, kNotWide), arg0);
150  ClobberCallerSave();
151  CallHelper(r_tgt, trampoline, safepoint_pc);
152}
153
154void Mir2Lir::CallRuntimeHelperRegLocationImm(QuickEntrypointEnum trampoline, RegLocation arg0,
155                                              int arg1, bool safepoint_pc) {
156  RegStorage r_tgt = CallHelperSetup(trampoline);
157  DCHECK(!arg0.wide);
158  LoadValueDirectFixed(arg0, TargetReg(kArg0, arg0));
159  LoadConstant(TargetReg(kArg1, kNotWide), arg1);
160  ClobberCallerSave();
161  CallHelper(r_tgt, trampoline, safepoint_pc);
162}
163
164void Mir2Lir::CallRuntimeHelperImmReg(QuickEntrypointEnum trampoline, int arg0, RegStorage arg1,
165                                      bool safepoint_pc) {
166  RegStorage r_tgt = CallHelperSetup(trampoline);
167  OpRegCopy(TargetReg(kArg1, arg1.GetWideKind()), arg1);
168  LoadConstant(TargetReg(kArg0, kNotWide), arg0);
169  ClobberCallerSave();
170  CallHelper(r_tgt, trampoline, safepoint_pc);
171}
172
173void Mir2Lir::CallRuntimeHelperRegImm(QuickEntrypointEnum trampoline, RegStorage arg0, int arg1,
174                                      bool safepoint_pc) {
175  RegStorage r_tgt = CallHelperSetup(trampoline);
176  OpRegCopy(TargetReg(kArg0, arg0.GetWideKind()), arg0);
177  LoadConstant(TargetReg(kArg1, kNotWide), arg1);
178  ClobberCallerSave();
179  CallHelper(r_tgt, trampoline, safepoint_pc);
180}
181
182void Mir2Lir::CallRuntimeHelperImmMethod(QuickEntrypointEnum trampoline, int arg0,
183                                         bool safepoint_pc) {
184  RegStorage r_tgt = CallHelperSetup(trampoline);
185  LoadCurrMethodDirect(TargetReg(kArg1, kRef));
186  LoadConstant(TargetReg(kArg0, kNotWide), arg0);
187  ClobberCallerSave();
188  CallHelper(r_tgt, trampoline, safepoint_pc);
189}
190
191void Mir2Lir::CallRuntimeHelperRegMethod(QuickEntrypointEnum trampoline, RegStorage arg0,
192                                         bool safepoint_pc) {
193  RegStorage r_tgt = CallHelperSetup(trampoline);
194  DCHECK(!IsSameReg(TargetReg(kArg1, arg0.GetWideKind()), arg0));
195  RegStorage r_tmp = TargetReg(kArg0, arg0.GetWideKind());
196  if (r_tmp.NotExactlyEquals(arg0)) {
197    OpRegCopy(r_tmp, arg0);
198  }
199  LoadCurrMethodDirect(TargetReg(kArg1, kRef));
200  ClobberCallerSave();
201  CallHelper(r_tgt, trampoline, safepoint_pc);
202}
203
204void Mir2Lir::CallRuntimeHelperRegMethodRegLocation(QuickEntrypointEnum trampoline, RegStorage arg0,
205                                                    RegLocation arg2, bool safepoint_pc) {
206  RegStorage r_tgt = CallHelperSetup(trampoline);
207  DCHECK(!IsSameReg(TargetReg(kArg1, arg0.GetWideKind()), arg0));
208  RegStorage r_tmp = TargetReg(kArg0, arg0.GetWideKind());
209  if (r_tmp.NotExactlyEquals(arg0)) {
210    OpRegCopy(r_tmp, arg0);
211  }
212  LoadCurrMethodDirect(TargetReg(kArg1, kRef));
213  LoadValueDirectFixed(arg2, TargetReg(kArg2, arg2));
214  ClobberCallerSave();
215  CallHelper(r_tgt, trampoline, safepoint_pc);
216}
217
218void Mir2Lir::CallRuntimeHelperRegLocationRegLocation(QuickEntrypointEnum trampoline,
219                                                      RegLocation arg0, RegLocation arg1,
220                                                      bool safepoint_pc) {
221  RegStorage r_tgt = CallHelperSetup(trampoline);
222  if (cu_->instruction_set == kArm64 || cu_->instruction_set == kX86_64) {
223    RegStorage arg0_reg = TargetReg((arg0.fp) ? kFArg0 : kArg0, arg0);
224
225    RegStorage arg1_reg;
226    if (arg1.fp == arg0.fp) {
227      arg1_reg = TargetReg((arg1.fp) ? kFArg1 : kArg1, arg1);
228    } else {
229      arg1_reg = TargetReg((arg1.fp) ? kFArg0 : kArg0, arg1);
230    }
231
232    if (arg0.wide == 0) {
233      LoadValueDirectFixed(arg0, arg0_reg);
234    } else {
235      LoadValueDirectWideFixed(arg0, arg0_reg);
236    }
237
238    if (arg1.wide == 0) {
239      LoadValueDirectFixed(arg1, arg1_reg);
240    } else {
241      LoadValueDirectWideFixed(arg1, arg1_reg);
242    }
243  } else {
244    DCHECK(!cu_->target64);
245    if (arg0.wide == 0) {
246      LoadValueDirectFixed(arg0, TargetReg(arg0.fp ? kFArg0 : kArg0, kNotWide));
247      if (arg1.wide == 0) {
248        if (cu_->instruction_set == kMips) {
249          LoadValueDirectFixed(arg1, TargetReg(arg1.fp ? kFArg2 : kArg1, kNotWide));
250        } else {
251          LoadValueDirectFixed(arg1, TargetReg(kArg1, kNotWide));
252        }
253      } else {
254        if (cu_->instruction_set == kMips) {
255          LoadValueDirectWideFixed(arg1, TargetReg(arg1.fp ? kFArg2 : kArg2, kWide));
256        } else {
257          LoadValueDirectWideFixed(arg1, TargetReg(kArg1, kWide));
258        }
259      }
260    } else {
261      LoadValueDirectWideFixed(arg0, TargetReg(arg0.fp ? kFArg0 : kArg0, kWide));
262      if (arg1.wide == 0) {
263        LoadValueDirectFixed(arg1, TargetReg(arg1.fp ? kFArg2 : kArg2, kNotWide));
264      } else {
265        LoadValueDirectWideFixed(arg1, TargetReg(arg1.fp ? kFArg2 : kArg2, kWide));
266      }
267    }
268  }
269  ClobberCallerSave();
270  CallHelper(r_tgt, trampoline, safepoint_pc);
271}
272
273void Mir2Lir::CopyToArgumentRegs(RegStorage arg0, RegStorage arg1) {
274  WideKind arg0_kind = arg0.GetWideKind();
275  WideKind arg1_kind = arg1.GetWideKind();
276  if (IsSameReg(arg1, TargetReg(kArg0, arg1_kind))) {
277    if (IsSameReg(arg0, TargetReg(kArg1, arg0_kind))) {
278      // Swap kArg0 and kArg1 with kArg2 as temp.
279      OpRegCopy(TargetReg(kArg2, arg1_kind), arg1);
280      OpRegCopy(TargetReg(kArg0, arg0_kind), arg0);
281      OpRegCopy(TargetReg(kArg1, arg1_kind), TargetReg(kArg2, arg1_kind));
282    } else {
283      OpRegCopy(TargetReg(kArg1, arg1_kind), arg1);
284      OpRegCopy(TargetReg(kArg0, arg0_kind), arg0);
285    }
286  } else {
287    OpRegCopy(TargetReg(kArg0, arg0_kind), arg0);
288    OpRegCopy(TargetReg(kArg1, arg1_kind), arg1);
289  }
290}
291
292void Mir2Lir::CallRuntimeHelperRegReg(QuickEntrypointEnum trampoline, RegStorage arg0,
293                                      RegStorage arg1, bool safepoint_pc) {
294  RegStorage r_tgt = CallHelperSetup(trampoline);
295  CopyToArgumentRegs(arg0, arg1);
296  ClobberCallerSave();
297  CallHelper(r_tgt, trampoline, safepoint_pc);
298}
299
300void Mir2Lir::CallRuntimeHelperRegRegImm(QuickEntrypointEnum trampoline, RegStorage arg0,
301                                         RegStorage arg1, int arg2, bool safepoint_pc) {
302  RegStorage r_tgt = CallHelperSetup(trampoline);
303  CopyToArgumentRegs(arg0, arg1);
304  LoadConstant(TargetReg(kArg2, kNotWide), arg2);
305  ClobberCallerSave();
306  CallHelper(r_tgt, trampoline, safepoint_pc);
307}
308
309void Mir2Lir::CallRuntimeHelperImmMethodRegLocation(QuickEntrypointEnum trampoline, int arg0,
310                                                    RegLocation arg2, bool safepoint_pc) {
311  RegStorage r_tgt = CallHelperSetup(trampoline);
312  LoadValueDirectFixed(arg2, TargetReg(kArg2, arg2));
313  LoadCurrMethodDirect(TargetReg(kArg1, kRef));
314  LoadConstant(TargetReg(kArg0, kNotWide), arg0);
315  ClobberCallerSave();
316  CallHelper(r_tgt, trampoline, safepoint_pc);
317}
318
319void Mir2Lir::CallRuntimeHelperImmMethodImm(QuickEntrypointEnum trampoline, int arg0, int arg2,
320                                            bool safepoint_pc) {
321  RegStorage r_tgt = CallHelperSetup(trampoline);
322  LoadCurrMethodDirect(TargetReg(kArg1, kRef));
323  LoadConstant(TargetReg(kArg2, kNotWide), arg2);
324  LoadConstant(TargetReg(kArg0, kNotWide), arg0);
325  ClobberCallerSave();
326  CallHelper(r_tgt, trampoline, safepoint_pc);
327}
328
329void Mir2Lir::CallRuntimeHelperImmRegLocationRegLocation(QuickEntrypointEnum trampoline, int arg0,
330                                                         RegLocation arg1,
331                                                         RegLocation arg2, bool safepoint_pc) {
332  RegStorage r_tgt = CallHelperSetup(trampoline);
333  DCHECK_EQ(static_cast<unsigned int>(arg1.wide), 0U);  // The static_cast works around an
334                                                        // instantiation bug in GCC.
335  LoadValueDirectFixed(arg1, TargetReg(kArg1, arg1));
336  if (arg2.wide == 0) {
337    LoadValueDirectFixed(arg2, TargetReg(kArg2, arg2));
338  } else {
339    LoadValueDirectWideFixed(arg2, TargetReg(kArg2, kWide));
340  }
341  LoadConstant(TargetReg(kArg0, kNotWide), arg0);
342  ClobberCallerSave();
343  CallHelper(r_tgt, trampoline, safepoint_pc);
344}
345
346void Mir2Lir::CallRuntimeHelperRegLocationRegLocationRegLocation(
347    QuickEntrypointEnum trampoline,
348    RegLocation arg0,
349    RegLocation arg1,
350    RegLocation arg2,
351    bool safepoint_pc) {
352  RegStorage r_tgt = CallHelperSetup(trampoline);
353  LoadValueDirectFixed(arg0, TargetReg(kArg0, arg0));
354  LoadValueDirectFixed(arg1, TargetReg(kArg1, arg1));
355  LoadValueDirectFixed(arg2, TargetReg(kArg2, arg2));
356  ClobberCallerSave();
357  CallHelper(r_tgt, trampoline, safepoint_pc);
358}
359
360/*
361 * If there are any ins passed in registers that have not been promoted
362 * to a callee-save register, flush them to the frame.  Perform initial
363 * assignment of promoted arguments.
364 *
365 * ArgLocs is an array of location records describing the incoming arguments
366 * with one location record per word of argument.
367 */
368void Mir2Lir::FlushIns(RegLocation* ArgLocs, RegLocation rl_method) {
369  /*
370   * Dummy up a RegLocation for the incoming StackReference<mirror::ArtMethod>
371   * It will attempt to keep kArg0 live (or copy it to home location
372   * if promoted).
373   */
374  RegLocation rl_src = rl_method;
375  rl_src.location = kLocPhysReg;
376  rl_src.reg = TargetReg(kArg0, kRef);
377  rl_src.home = false;
378  MarkLive(rl_src);
379  StoreValue(rl_method, rl_src);
380  // If Method* has been promoted, explicitly flush
381  if (rl_method.location == kLocPhysReg) {
382    StoreRefDisp(TargetPtrReg(kSp), 0, rl_src.reg, kNotVolatile);
383  }
384
385  if (mir_graph_->GetNumOfInVRs() == 0) {
386    return;
387  }
388
389  int start_vreg = mir_graph_->GetFirstInVR();
390  /*
391   * Copy incoming arguments to their proper home locations.
392   * NOTE: an older version of dx had an issue in which
393   * it would reuse static method argument registers.
394   * This could result in the same Dalvik virtual register
395   * being promoted to both core and fp regs. To account for this,
396   * we only copy to the corresponding promoted physical register
397   * if it matches the type of the SSA name for the incoming
398   * argument.  It is also possible that long and double arguments
399   * end up half-promoted.  In those cases, we must flush the promoted
400   * half to memory as well.
401   */
402  ScopedMemRefType mem_ref_type(this, ResourceMask::kDalvikReg);
403  for (uint32_t i = 0; i < mir_graph_->GetNumOfInVRs(); i++) {
404    PromotionMap* v_map = &promotion_map_[start_vreg + i];
405    RegStorage reg = GetArgMappingToPhysicalReg(i);
406
407    if (reg.Valid()) {
408      // If arriving in register
409      bool need_flush = true;
410      RegLocation* t_loc = &ArgLocs[i];
411      if ((v_map->core_location == kLocPhysReg) && !t_loc->fp) {
412        OpRegCopy(RegStorage::Solo32(v_map->core_reg), reg);
413        need_flush = false;
414      } else if ((v_map->fp_location == kLocPhysReg) && t_loc->fp) {
415        OpRegCopy(RegStorage::Solo32(v_map->fp_reg), reg);
416        need_flush = false;
417      } else {
418        need_flush = true;
419      }
420
421      // For wide args, force flush if not fully promoted
422      if (t_loc->wide) {
423        PromotionMap* p_map = v_map + (t_loc->high_word ? -1 : +1);
424        // Is only half promoted?
425        need_flush |= (p_map->core_location != v_map->core_location) ||
426            (p_map->fp_location != v_map->fp_location);
427        if ((cu_->instruction_set == kThumb2) && t_loc->fp && !need_flush) {
428          /*
429           * In Arm, a double is represented as a pair of consecutive single float
430           * registers starting at an even number.  It's possible that both Dalvik vRegs
431           * representing the incoming double were independently promoted as singles - but
432           * not in a form usable as a double.  If so, we need to flush - even though the
433           * incoming arg appears fully in register.  At this point in the code, both
434           * halves of the double are promoted.  Make sure they are in a usable form.
435           */
436          int lowreg_index = start_vreg + i + (t_loc->high_word ? -1 : 0);
437          int low_reg = promotion_map_[lowreg_index].fp_reg;
438          int high_reg = promotion_map_[lowreg_index + 1].fp_reg;
439          if (((low_reg & 0x1) != 0) || (high_reg != (low_reg + 1))) {
440            need_flush = true;
441          }
442        }
443      }
444      if (need_flush) {
445        Store32Disp(TargetPtrReg(kSp), SRegOffset(start_vreg + i), reg);
446      }
447    } else {
448      // If arriving in frame & promoted
449      if (v_map->core_location == kLocPhysReg) {
450        Load32Disp(TargetPtrReg(kSp), SRegOffset(start_vreg + i),
451                   RegStorage::Solo32(v_map->core_reg));
452      }
453      if (v_map->fp_location == kLocPhysReg) {
454        Load32Disp(TargetPtrReg(kSp), SRegOffset(start_vreg + i),
455                   RegStorage::Solo32(v_map->fp_reg));
456      }
457    }
458  }
459}
460
461static void CommonCallCodeLoadThisIntoArg1(const CallInfo* info, Mir2Lir* cg) {
462  RegLocation rl_arg = info->args[0];
463  cg->LoadValueDirectFixed(rl_arg, cg->TargetReg(kArg1, kRef));
464}
465
466static void CommonCallCodeLoadClassIntoArg0(const CallInfo* info, Mir2Lir* cg) {
467  cg->GenNullCheck(cg->TargetReg(kArg1, kRef), info->opt_flags);
468  // get this->klass_ [use kArg1, set kArg0]
469  cg->LoadRefDisp(cg->TargetReg(kArg1, kRef), mirror::Object::ClassOffset().Int32Value(),
470                  cg->TargetReg(kArg0, kRef),
471                  kNotVolatile);
472  cg->MarkPossibleNullPointerException(info->opt_flags);
473}
474
475static bool CommonCallCodeLoadCodePointerIntoInvokeTgt(const CallInfo* info,
476                                                       const RegStorage* alt_from,
477                                                       const CompilationUnit* cu, Mir2Lir* cg) {
478  if (cu->instruction_set != kX86 && cu->instruction_set != kX86_64) {
479    // Get the compiled code address [use *alt_from or kArg0, set kInvokeTgt]
480    cg->LoadWordDisp(alt_from == nullptr ? cg->TargetReg(kArg0, kRef) : *alt_from,
481                     mirror::ArtMethod::EntryPointFromQuickCompiledCodeOffset().Int32Value(),
482                     cg->TargetPtrReg(kInvokeTgt));
483    return true;
484  }
485  return false;
486}
487
488/*
489 * Bit of a hack here - in the absence of a real scheduling pass,
490 * emit the next instruction in static & direct invoke sequences.
491 */
492static int NextSDCallInsn(CompilationUnit* cu, CallInfo* info,
493                          int state, const MethodReference& target_method,
494                          uint32_t unused,
495                          uintptr_t direct_code, uintptr_t direct_method,
496                          InvokeType type) {
497  DCHECK(cu->instruction_set != kX86 && cu->instruction_set != kX86_64 &&
498         cu->instruction_set != kThumb2 && cu->instruction_set != kArm &&
499         cu->instruction_set != kArm64);
500  Mir2Lir* cg = static_cast<Mir2Lir*>(cu->cg.get());
501  if (direct_code != 0 && direct_method != 0) {
502    switch (state) {
503    case 0:  // Get the current Method* [sets kArg0]
504      if (direct_code != static_cast<uintptr_t>(-1)) {
505        cg->LoadConstant(cg->TargetPtrReg(kInvokeTgt), direct_code);
506      } else {
507        cg->LoadCodeAddress(target_method, type, kInvokeTgt);
508      }
509      if (direct_method != static_cast<uintptr_t>(-1)) {
510        cg->LoadConstant(cg->TargetReg(kArg0, kRef), direct_method);
511      } else {
512        cg->LoadMethodAddress(target_method, type, kArg0);
513      }
514      break;
515    default:
516      return -1;
517    }
518  } else {
519    RegStorage arg0_ref = cg->TargetReg(kArg0, kRef);
520    switch (state) {
521    case 0:  // Get the current Method* [sets kArg0]
522      // TUNING: we can save a reg copy if Method* has been promoted.
523      cg->LoadCurrMethodDirect(arg0_ref);
524      break;
525    case 1:  // Get method->dex_cache_resolved_methods_
526      cg->LoadRefDisp(arg0_ref,
527                      mirror::ArtMethod::DexCacheResolvedMethodsOffset().Int32Value(),
528                      arg0_ref,
529                      kNotVolatile);
530      // Set up direct code if known.
531      if (direct_code != 0) {
532        if (direct_code != static_cast<uintptr_t>(-1)) {
533          cg->LoadConstant(cg->TargetPtrReg(kInvokeTgt), direct_code);
534        } else {
535          CHECK_LT(target_method.dex_method_index, target_method.dex_file->NumMethodIds());
536          cg->LoadCodeAddress(target_method, type, kInvokeTgt);
537        }
538      }
539      break;
540    case 2:  // Grab target method*
541      CHECK_EQ(cu->dex_file, target_method.dex_file);
542      cg->LoadRefDisp(arg0_ref,
543                      ObjArray::OffsetOfElement(target_method.dex_method_index).Int32Value(),
544                      arg0_ref,
545                      kNotVolatile);
546      break;
547    case 3:  // Grab the code from the method*
548      if (direct_code == 0) {
549        if (CommonCallCodeLoadCodePointerIntoInvokeTgt(info, &arg0_ref, cu, cg)) {
550          break;                                    // kInvokeTgt := arg0_ref->entrypoint
551        }
552      } else {
553        break;
554      }
555      // Intentional fallthrough for x86
556    default:
557      return -1;
558    }
559  }
560  return state + 1;
561}
562
563/*
564 * Bit of a hack here - in the absence of a real scheduling pass,
565 * emit the next instruction in a virtual invoke sequence.
566 * We can use kLr as a temp prior to target address loading
567 * Note also that we'll load the first argument ("this") into
568 * kArg1 here rather than the standard LoadArgRegs.
569 */
570static int NextVCallInsn(CompilationUnit* cu, CallInfo* info,
571                         int state, const MethodReference& target_method,
572                         uint32_t method_idx, uintptr_t unused, uintptr_t unused2,
573                         InvokeType unused3) {
574  Mir2Lir* cg = static_cast<Mir2Lir*>(cu->cg.get());
575  /*
576   * This is the fast path in which the target virtual method is
577   * fully resolved at compile time.
578   */
579  switch (state) {
580    case 0:
581      CommonCallCodeLoadThisIntoArg1(info, cg);   // kArg1 := this
582      break;
583    case 1:
584      CommonCallCodeLoadClassIntoArg0(info, cg);  // kArg0 := kArg1->class
585                                                  // Includes a null-check.
586      break;
587    case 2: {
588      // Get this->klass_.embedded_vtable[method_idx] [usr kArg0, set kArg0]
589      int32_t offset = mirror::Class::EmbeddedVTableOffset().Uint32Value() +
590          method_idx * sizeof(mirror::Class::VTableEntry);
591      // Load target method from embedded vtable to kArg0 [use kArg0, set kArg0]
592      cg->LoadRefDisp(cg->TargetReg(kArg0, kRef), offset, cg->TargetReg(kArg0, kRef), kNotVolatile);
593      break;
594    }
595    case 3:
596      if (CommonCallCodeLoadCodePointerIntoInvokeTgt(info, nullptr, cu, cg)) {
597        break;                                    // kInvokeTgt := kArg0->entrypoint
598      }
599      // Intentional fallthrough for X86
600    default:
601      return -1;
602  }
603  return state + 1;
604}
605
606/*
607 * Emit the next instruction in an invoke interface sequence. This will do a lookup in the
608 * class's IMT, calling either the actual method or art_quick_imt_conflict_trampoline if
609 * more than one interface method map to the same index. Note also that we'll load the first
610 * argument ("this") into kArg1 here rather than the standard LoadArgRegs.
611 */
612static int NextInterfaceCallInsn(CompilationUnit* cu, CallInfo* info, int state,
613                                 const MethodReference& target_method,
614                                 uint32_t method_idx, uintptr_t unused,
615                                 uintptr_t direct_method, InvokeType unused2) {
616  Mir2Lir* cg = static_cast<Mir2Lir*>(cu->cg.get());
617
618  switch (state) {
619    case 0:  // Set target method index in case of conflict [set kHiddenArg, kHiddenFpArg (x86)]
620      CHECK_LT(target_method.dex_method_index, target_method.dex_file->NumMethodIds());
621      cg->LoadConstant(cg->TargetReg(kHiddenArg, kNotWide), target_method.dex_method_index);
622      if (cu->instruction_set == kX86) {
623        cg->OpRegCopy(cg->TargetReg(kHiddenFpArg, kNotWide), cg->TargetReg(kHiddenArg, kNotWide));
624      }
625      break;
626    case 1:
627      CommonCallCodeLoadThisIntoArg1(info, cg);   // kArg1 := this
628      break;
629    case 2:
630      CommonCallCodeLoadClassIntoArg0(info, cg);  // kArg0 := kArg1->class
631                                                  // Includes a null-check.
632      break;
633    case 3: {  // Get target method [use kInvokeTgt, set kArg0]
634      int32_t offset = mirror::Class::EmbeddedImTableOffset().Uint32Value() +
635          (method_idx % mirror::Class::kImtSize) * sizeof(mirror::Class::ImTableEntry);
636      // Load target method from embedded imtable to kArg0 [use kArg0, set kArg0]
637      cg->LoadRefDisp(cg->TargetReg(kArg0, kRef), offset, cg->TargetReg(kArg0, kRef), kNotVolatile);
638      break;
639    }
640    case 4:
641      if (CommonCallCodeLoadCodePointerIntoInvokeTgt(info, nullptr, cu, cg)) {
642        break;                                    // kInvokeTgt := kArg0->entrypoint
643      }
644      // Intentional fallthrough for X86
645    default:
646      return -1;
647  }
648  return state + 1;
649}
650
651static int NextInvokeInsnSP(CompilationUnit* cu, CallInfo* info,
652                            QuickEntrypointEnum trampoline, int state,
653                            const MethodReference& target_method, uint32_t method_idx) {
654  Mir2Lir* cg = static_cast<Mir2Lir*>(cu->cg.get());
655
656
657  /*
658   * This handles the case in which the base method is not fully
659   * resolved at compile time, we bail to a runtime helper.
660   */
661  if (state == 0) {
662    if (cu->instruction_set != kX86 && cu->instruction_set != kX86_64) {
663      // Load trampoline target
664      int32_t disp;
665      if (cu->target64) {
666        disp = GetThreadOffset<8>(trampoline).Int32Value();
667      } else {
668        disp = GetThreadOffset<4>(trampoline).Int32Value();
669      }
670      cg->LoadWordDisp(cg->TargetPtrReg(kSelf), disp, cg->TargetPtrReg(kInvokeTgt));
671    }
672    // Load kArg0 with method index
673    CHECK_EQ(cu->dex_file, target_method.dex_file);
674    cg->LoadConstant(cg->TargetReg(kArg0, kNotWide), target_method.dex_method_index);
675    return 1;
676  }
677  return -1;
678}
679
680static int NextStaticCallInsnSP(CompilationUnit* cu, CallInfo* info,
681                                int state,
682                                const MethodReference& target_method,
683                                uint32_t unused, uintptr_t unused2,
684                                uintptr_t unused3, InvokeType unused4) {
685  return NextInvokeInsnSP(cu, info, kQuickInvokeStaticTrampolineWithAccessCheck, state,
686                          target_method, 0);
687}
688
689static int NextDirectCallInsnSP(CompilationUnit* cu, CallInfo* info, int state,
690                                const MethodReference& target_method,
691                                uint32_t unused, uintptr_t unused2,
692                                uintptr_t unused3, InvokeType unused4) {
693  return NextInvokeInsnSP(cu, info, kQuickInvokeDirectTrampolineWithAccessCheck, state,
694                          target_method, 0);
695}
696
697static int NextSuperCallInsnSP(CompilationUnit* cu, CallInfo* info, int state,
698                               const MethodReference& target_method,
699                               uint32_t unused, uintptr_t unused2,
700                               uintptr_t unused3, InvokeType unused4) {
701  return NextInvokeInsnSP(cu, info, kQuickInvokeSuperTrampolineWithAccessCheck, state,
702                          target_method, 0);
703}
704
705static int NextVCallInsnSP(CompilationUnit* cu, CallInfo* info, int state,
706                           const MethodReference& target_method,
707                           uint32_t unused, uintptr_t unused2,
708                           uintptr_t unused3, InvokeType unused4) {
709  return NextInvokeInsnSP(cu, info, kQuickInvokeVirtualTrampolineWithAccessCheck, state,
710                          target_method, 0);
711}
712
713static int NextInterfaceCallInsnWithAccessCheck(CompilationUnit* cu,
714                                                CallInfo* info, int state,
715                                                const MethodReference& target_method,
716                                                uint32_t unused, uintptr_t unused2,
717                                                uintptr_t unused3, InvokeType unused4) {
718  return NextInvokeInsnSP(cu, info, kQuickInvokeInterfaceTrampolineWithAccessCheck, state,
719                          target_method, 0);
720}
721
722int Mir2Lir::LoadArgRegs(CallInfo* info, int call_state,
723                         NextCallInsn next_call_insn,
724                         const MethodReference& target_method,
725                         uint32_t vtable_idx, uintptr_t direct_code,
726                         uintptr_t direct_method, InvokeType type, bool skip_this) {
727  int last_arg_reg = 3 - 1;
728  int arg_regs[3] = {TargetReg(kArg1, kNotWide).GetReg(), TargetReg(kArg2, kNotWide).GetReg(),
729                     TargetReg(kArg3, kNotWide).GetReg()};
730
731  int next_reg = 0;
732  int next_arg = 0;
733  if (skip_this) {
734    next_reg++;
735    next_arg++;
736  }
737  for (; (next_reg <= last_arg_reg) && (next_arg < info->num_arg_words); next_reg++) {
738    RegLocation rl_arg = info->args[next_arg++];
739    rl_arg = UpdateRawLoc(rl_arg);
740    if (rl_arg.wide && (next_reg <= last_arg_reg - 1)) {
741      RegStorage r_tmp(RegStorage::k64BitPair, arg_regs[next_reg], arg_regs[next_reg + 1]);
742      LoadValueDirectWideFixed(rl_arg, r_tmp);
743      next_reg++;
744      next_arg++;
745    } else {
746      if (rl_arg.wide) {
747        rl_arg = NarrowRegLoc(rl_arg);
748        rl_arg.is_const = false;
749      }
750      LoadValueDirectFixed(rl_arg, RegStorage::Solo32(arg_regs[next_reg]));
751    }
752    call_state = next_call_insn(cu_, info, call_state, target_method, vtable_idx,
753                                direct_code, direct_method, type);
754  }
755  return call_state;
756}
757
758/*
759 * Load up to 5 arguments, the first three of which will be in
760 * kArg1 .. kArg3.  On entry kArg0 contains the current method pointer,
761 * and as part of the load sequence, it must be replaced with
762 * the target method pointer.  Note, this may also be called
763 * for "range" variants if the number of arguments is 5 or fewer.
764 */
765int Mir2Lir::GenDalvikArgsNoRange(CallInfo* info,
766                                  int call_state, LIR** pcrLabel, NextCallInsn next_call_insn,
767                                  const MethodReference& target_method,
768                                  uint32_t vtable_idx, uintptr_t direct_code,
769                                  uintptr_t direct_method, InvokeType type, bool skip_this) {
770  RegLocation rl_arg;
771
772  /* If no arguments, just return */
773  if (info->num_arg_words == 0)
774    return call_state;
775
776  call_state = next_call_insn(cu_, info, call_state, target_method, vtable_idx,
777                              direct_code, direct_method, type);
778
779  DCHECK_LE(info->num_arg_words, 5);
780  if (info->num_arg_words > 3) {
781    int32_t next_use = 3;
782    // Detect special case of wide arg spanning arg3/arg4
783    RegLocation rl_use0 = info->args[0];
784    RegLocation rl_use1 = info->args[1];
785    RegLocation rl_use2 = info->args[2];
786    if (((!rl_use0.wide && !rl_use1.wide) || rl_use0.wide) && rl_use2.wide) {
787      RegStorage reg;
788      // Wide spans, we need the 2nd half of uses[2].
789      rl_arg = UpdateLocWide(rl_use2);
790      if (rl_arg.location == kLocPhysReg) {
791        if (rl_arg.reg.IsPair()) {
792          reg = rl_arg.reg.GetHigh();
793        } else {
794          RegisterInfo* info = GetRegInfo(rl_arg.reg);
795          info = info->FindMatchingView(RegisterInfo::kHighSingleStorageMask);
796          if (info == nullptr) {
797            // NOTE: For hard float convention we won't split arguments across reg/mem.
798            UNIMPLEMENTED(FATAL) << "Needs hard float api.";
799          }
800          reg = info->GetReg();
801        }
802      } else {
803        // kArg2 & rArg3 can safely be used here
804        reg = TargetReg(kArg3, kNotWide);
805        {
806          ScopedMemRefType mem_ref_type(this, ResourceMask::kDalvikReg);
807          Load32Disp(TargetPtrReg(kSp), SRegOffset(rl_arg.s_reg_low) + 4, reg);
808        }
809        call_state = next_call_insn(cu_, info, call_state, target_method,
810                                    vtable_idx, direct_code, direct_method, type);
811      }
812      {
813        ScopedMemRefType mem_ref_type(this, ResourceMask::kDalvikReg);
814        Store32Disp(TargetPtrReg(kSp), (next_use + 1) * 4, reg);
815      }
816      call_state = next_call_insn(cu_, info, call_state, target_method, vtable_idx,
817                                  direct_code, direct_method, type);
818      next_use++;
819    }
820    // Loop through the rest
821    while (next_use < info->num_arg_words) {
822      RegStorage arg_reg;
823      rl_arg = info->args[next_use];
824      rl_arg = UpdateRawLoc(rl_arg);
825      if (rl_arg.location == kLocPhysReg) {
826        arg_reg = rl_arg.reg;
827      } else {
828        arg_reg = TargetReg(kArg2, rl_arg.wide ? kWide : kNotWide);
829        if (rl_arg.wide) {
830          LoadValueDirectWideFixed(rl_arg, arg_reg);
831        } else {
832          LoadValueDirectFixed(rl_arg, arg_reg);
833        }
834        call_state = next_call_insn(cu_, info, call_state, target_method,
835                                    vtable_idx, direct_code, direct_method, type);
836      }
837      int outs_offset = (next_use + 1) * 4;
838      {
839        ScopedMemRefType mem_ref_type(this, ResourceMask::kDalvikReg);
840        if (rl_arg.wide) {
841          StoreBaseDisp(TargetPtrReg(kSp), outs_offset, arg_reg, k64, kNotVolatile);
842          next_use += 2;
843        } else {
844          Store32Disp(TargetPtrReg(kSp), outs_offset, arg_reg);
845          next_use++;
846        }
847      }
848      call_state = next_call_insn(cu_, info, call_state, target_method, vtable_idx,
849                               direct_code, direct_method, type);
850    }
851  }
852
853  call_state = LoadArgRegs(info, call_state, next_call_insn,
854                           target_method, vtable_idx, direct_code, direct_method,
855                           type, skip_this);
856
857  if (pcrLabel) {
858    if (!cu_->compiler_driver->GetCompilerOptions().GetImplicitNullChecks()) {
859      *pcrLabel = GenExplicitNullCheck(TargetReg(kArg1, kRef), info->opt_flags);
860    } else {
861      *pcrLabel = nullptr;
862      if (!(cu_->disable_opt & (1 << kNullCheckElimination)) &&
863          (info->opt_flags & MIR_IGNORE_NULL_CHECK)) {
864        return call_state;
865      }
866      // In lieu of generating a check for kArg1 being null, we need to
867      // perform a load when doing implicit checks.
868      GenImplicitNullCheck(TargetReg(kArg1, kRef), info->opt_flags);
869    }
870  }
871  return call_state;
872}
873
874// Default implementation of implicit null pointer check.
875// Overridden by arch specific as necessary.
876void Mir2Lir::GenImplicitNullCheck(RegStorage reg, int opt_flags) {
877  if (!(cu_->disable_opt & (1 << kNullCheckElimination)) && (opt_flags & MIR_IGNORE_NULL_CHECK)) {
878    return;
879  }
880  RegStorage tmp = AllocTemp();
881  Load32Disp(reg, 0, tmp);
882  MarkPossibleNullPointerException(opt_flags);
883  FreeTemp(tmp);
884}
885
886
887/*
888 * May have 0+ arguments (also used for jumbo).  Note that
889 * source virtual registers may be in physical registers, so may
890 * need to be flushed to home location before copying.  This
891 * applies to arg3 and above (see below).
892 *
893 * Two general strategies:
894 *    If < 20 arguments
895 *       Pass args 3-18 using vldm/vstm block copy
896 *       Pass arg0, arg1 & arg2 in kArg1-kArg3
897 *    If 20+ arguments
898 *       Pass args arg19+ using memcpy block copy
899 *       Pass arg0, arg1 & arg2 in kArg1-kArg3
900 *
901 */
902int Mir2Lir::GenDalvikArgsRange(CallInfo* info, int call_state,
903                                LIR** pcrLabel, NextCallInsn next_call_insn,
904                                const MethodReference& target_method,
905                                uint32_t vtable_idx, uintptr_t direct_code, uintptr_t direct_method,
906                                InvokeType type, bool skip_this) {
907  // If we can treat it as non-range (Jumbo ops will use range form)
908  if (info->num_arg_words <= 5)
909    return GenDalvikArgsNoRange(info, call_state, pcrLabel,
910                                next_call_insn, target_method, vtable_idx,
911                                direct_code, direct_method, type, skip_this);
912  /*
913   * First load the non-register arguments.  Both forms expect all
914   * of the source arguments to be in their home frame location, so
915   * scan the s_reg names and flush any that have been promoted to
916   * frame backing storage.
917   */
918  // Scan the rest of the args - if in phys_reg flush to memory
919  for (int next_arg = 0; next_arg < info->num_arg_words;) {
920    RegLocation loc = info->args[next_arg];
921    if (loc.wide) {
922      loc = UpdateLocWide(loc);
923      if ((next_arg >= 2) && (loc.location == kLocPhysReg)) {
924        ScopedMemRefType mem_ref_type(this, ResourceMask::kDalvikReg);
925        StoreBaseDisp(TargetPtrReg(kSp), SRegOffset(loc.s_reg_low), loc.reg, k64, kNotVolatile);
926      }
927      next_arg += 2;
928    } else {
929      loc = UpdateLoc(loc);
930      if ((next_arg >= 3) && (loc.location == kLocPhysReg)) {
931        ScopedMemRefType mem_ref_type(this, ResourceMask::kDalvikReg);
932        Store32Disp(TargetPtrReg(kSp), SRegOffset(loc.s_reg_low), loc.reg);
933      }
934      next_arg++;
935    }
936  }
937
938  // The first 3 arguments are passed via registers.
939  // TODO: For 64-bit, instead of hardcoding 4 for Method* size, we should either
940  // get size of uintptr_t or size of object reference according to model being used.
941  int outs_offset = 4 /* Method* */ + (3 * sizeof(uint32_t));
942  int start_offset = SRegOffset(info->args[3].s_reg_low);
943  int regs_left_to_pass_via_stack = info->num_arg_words - 3;
944  DCHECK_GT(regs_left_to_pass_via_stack, 0);
945
946  if (cu_->instruction_set == kThumb2 && regs_left_to_pass_via_stack <= 16) {
947    // Use vldm/vstm pair using kArg3 as a temp
948    call_state = next_call_insn(cu_, info, call_state, target_method, vtable_idx,
949                             direct_code, direct_method, type);
950    OpRegRegImm(kOpAdd, TargetReg(kArg3, kRef), TargetPtrReg(kSp), start_offset);
951    LIR* ld = nullptr;
952    {
953      ScopedMemRefType mem_ref_type(this, ResourceMask::kDalvikReg);
954      ld = OpVldm(TargetReg(kArg3, kRef), regs_left_to_pass_via_stack);
955    }
956    // TUNING: loosen barrier
957    ld->u.m.def_mask = &kEncodeAll;
958    call_state = next_call_insn(cu_, info, call_state, target_method, vtable_idx,
959                             direct_code, direct_method, type);
960    OpRegRegImm(kOpAdd, TargetReg(kArg3, kRef), TargetPtrReg(kSp), 4 /* Method* */ + (3 * 4));
961    call_state = next_call_insn(cu_, info, call_state, target_method, vtable_idx,
962                             direct_code, direct_method, type);
963    LIR* st = nullptr;
964    {
965      ScopedMemRefType mem_ref_type(this, ResourceMask::kDalvikReg);
966      st = OpVstm(TargetReg(kArg3, kRef), regs_left_to_pass_via_stack);
967    }
968    st->u.m.def_mask = &kEncodeAll;
969    call_state = next_call_insn(cu_, info, call_state, target_method, vtable_idx,
970                             direct_code, direct_method, type);
971  } else if (cu_->instruction_set == kX86 || cu_->instruction_set == kX86_64) {
972    int current_src_offset = start_offset;
973    int current_dest_offset = outs_offset;
974
975    // Only davik regs are accessed in this loop; no next_call_insn() calls.
976    ScopedMemRefType mem_ref_type(this, ResourceMask::kDalvikReg);
977    while (regs_left_to_pass_via_stack > 0) {
978      // This is based on the knowledge that the stack itself is 16-byte aligned.
979      bool src_is_16b_aligned = (current_src_offset & 0xF) == 0;
980      bool dest_is_16b_aligned = (current_dest_offset & 0xF) == 0;
981      size_t bytes_to_move;
982
983      /*
984       * The amount to move defaults to 32-bit. If there are 4 registers left to move, then do a
985       * a 128-bit move because we won't get the chance to try to aligned. If there are more than
986       * 4 registers left to move, consider doing a 128-bit only if either src or dest are aligned.
987       * We do this because we could potentially do a smaller move to align.
988       */
989      if (regs_left_to_pass_via_stack == 4 ||
990          (regs_left_to_pass_via_stack > 4 && (src_is_16b_aligned || dest_is_16b_aligned))) {
991        // Moving 128-bits via xmm register.
992        bytes_to_move = sizeof(uint32_t) * 4;
993
994        // Allocate a free xmm temp. Since we are working through the calling sequence,
995        // we expect to have an xmm temporary available.  AllocTempDouble will abort if
996        // there are no free registers.
997        RegStorage temp = AllocTempDouble();
998
999        LIR* ld1 = nullptr;
1000        LIR* ld2 = nullptr;
1001        LIR* st1 = nullptr;
1002        LIR* st2 = nullptr;
1003
1004        /*
1005         * The logic is similar for both loads and stores. If we have 16-byte alignment,
1006         * do an aligned move. If we have 8-byte alignment, then do the move in two
1007         * parts. This approach prevents possible cache line splits. Finally, fall back
1008         * to doing an unaligned move. In most cases we likely won't split the cache
1009         * line but we cannot prove it and thus take a conservative approach.
1010         */
1011        bool src_is_8b_aligned = (current_src_offset & 0x7) == 0;
1012        bool dest_is_8b_aligned = (current_dest_offset & 0x7) == 0;
1013
1014        if (src_is_16b_aligned) {
1015          ld1 = OpMovRegMem(temp, TargetPtrReg(kSp), current_src_offset, kMovA128FP);
1016        } else if (src_is_8b_aligned) {
1017          ld1 = OpMovRegMem(temp, TargetPtrReg(kSp), current_src_offset, kMovLo128FP);
1018          ld2 = OpMovRegMem(temp, TargetPtrReg(kSp), current_src_offset + (bytes_to_move >> 1),
1019                            kMovHi128FP);
1020        } else {
1021          ld1 = OpMovRegMem(temp, TargetPtrReg(kSp), current_src_offset, kMovU128FP);
1022        }
1023
1024        if (dest_is_16b_aligned) {
1025          st1 = OpMovMemReg(TargetPtrReg(kSp), current_dest_offset, temp, kMovA128FP);
1026        } else if (dest_is_8b_aligned) {
1027          st1 = OpMovMemReg(TargetPtrReg(kSp), current_dest_offset, temp, kMovLo128FP);
1028          st2 = OpMovMemReg(TargetPtrReg(kSp), current_dest_offset + (bytes_to_move >> 1),
1029                            temp, kMovHi128FP);
1030        } else {
1031          st1 = OpMovMemReg(TargetPtrReg(kSp), current_dest_offset, temp, kMovU128FP);
1032        }
1033
1034        // TODO If we could keep track of aliasing information for memory accesses that are wider
1035        // than 64-bit, we wouldn't need to set up a barrier.
1036        if (ld1 != nullptr) {
1037          if (ld2 != nullptr) {
1038            // For 64-bit load we can actually set up the aliasing information.
1039            AnnotateDalvikRegAccess(ld1, current_src_offset >> 2, true, true);
1040            AnnotateDalvikRegAccess(ld2, (current_src_offset + (bytes_to_move >> 1)) >> 2, true,
1041                                    true);
1042          } else {
1043            // Set barrier for 128-bit load.
1044            ld1->u.m.def_mask = &kEncodeAll;
1045          }
1046        }
1047        if (st1 != nullptr) {
1048          if (st2 != nullptr) {
1049            // For 64-bit store we can actually set up the aliasing information.
1050            AnnotateDalvikRegAccess(st1, current_dest_offset >> 2, false, true);
1051            AnnotateDalvikRegAccess(st2, (current_dest_offset + (bytes_to_move >> 1)) >> 2, false,
1052                                    true);
1053          } else {
1054            // Set barrier for 128-bit store.
1055            st1->u.m.def_mask = &kEncodeAll;
1056          }
1057        }
1058
1059        // Free the temporary used for the data movement.
1060        FreeTemp(temp);
1061      } else {
1062        // Moving 32-bits via general purpose register.
1063        bytes_to_move = sizeof(uint32_t);
1064
1065        // Instead of allocating a new temp, simply reuse one of the registers being used
1066        // for argument passing.
1067        RegStorage temp = TargetReg(kArg3, kNotWide);
1068
1069        // Now load the argument VR and store to the outs.
1070        Load32Disp(TargetPtrReg(kSp), current_src_offset, temp);
1071        Store32Disp(TargetPtrReg(kSp), current_dest_offset, temp);
1072      }
1073
1074      current_src_offset += bytes_to_move;
1075      current_dest_offset += bytes_to_move;
1076      regs_left_to_pass_via_stack -= (bytes_to_move >> 2);
1077    }
1078  } else {
1079    // Generate memcpy
1080    OpRegRegImm(kOpAdd, TargetReg(kArg0, kRef), TargetPtrReg(kSp), outs_offset);
1081    OpRegRegImm(kOpAdd, TargetReg(kArg1, kRef), TargetPtrReg(kSp), start_offset);
1082    CallRuntimeHelperRegRegImm(kQuickMemcpy, TargetReg(kArg0, kRef), TargetReg(kArg1, kRef),
1083                               (info->num_arg_words - 3) * 4, false);
1084  }
1085
1086  call_state = LoadArgRegs(info, call_state, next_call_insn,
1087                           target_method, vtable_idx, direct_code, direct_method,
1088                           type, skip_this);
1089
1090  call_state = next_call_insn(cu_, info, call_state, target_method, vtable_idx,
1091                           direct_code, direct_method, type);
1092  if (pcrLabel) {
1093    if (!cu_->compiler_driver->GetCompilerOptions().GetImplicitNullChecks()) {
1094      *pcrLabel = GenExplicitNullCheck(TargetReg(kArg1, kRef), info->opt_flags);
1095    } else {
1096      *pcrLabel = nullptr;
1097      if (!(cu_->disable_opt & (1 << kNullCheckElimination)) &&
1098          (info->opt_flags & MIR_IGNORE_NULL_CHECK)) {
1099        return call_state;
1100      }
1101      // In lieu of generating a check for kArg1 being null, we need to
1102      // perform a load when doing implicit checks.
1103      GenImplicitNullCheck(TargetReg(kArg1, kRef), info->opt_flags);
1104    }
1105  }
1106  return call_state;
1107}
1108
1109RegLocation Mir2Lir::InlineTarget(CallInfo* info) {
1110  RegLocation res;
1111  if (info->result.location == kLocInvalid) {
1112    // If result is unused, return a sink target based on type of invoke target.
1113    res = GetReturn(ShortyToRegClass(mir_graph_->GetShortyFromTargetIdx(info->index)[0]));
1114  } else {
1115    res = info->result;
1116    DCHECK_EQ(LocToRegClass(res),
1117              ShortyToRegClass(mir_graph_->GetShortyFromTargetIdx(info->index)[0]));
1118  }
1119  return res;
1120}
1121
1122RegLocation Mir2Lir::InlineTargetWide(CallInfo* info) {
1123  RegLocation res;
1124  if (info->result.location == kLocInvalid) {
1125    // If result is unused, return a sink target based on type of invoke target.
1126    res = GetReturnWide(ShortyToRegClass(mir_graph_->GetShortyFromTargetIdx(info->index)[0]));
1127  } else {
1128    res = info->result;
1129    DCHECK_EQ(LocToRegClass(res),
1130              ShortyToRegClass(mir_graph_->GetShortyFromTargetIdx(info->index)[0]));
1131  }
1132  return res;
1133}
1134
1135bool Mir2Lir::GenInlinedReferenceGetReferent(CallInfo* info) {
1136  if (cu_->instruction_set == kMips) {
1137    // TODO - add Mips implementation
1138    return false;
1139  }
1140
1141  bool use_direct_type_ptr;
1142  uintptr_t direct_type_ptr;
1143  ClassReference ref;
1144  if (!cu_->compiler_driver->CanEmbedReferenceTypeInCode(&ref,
1145        &use_direct_type_ptr, &direct_type_ptr)) {
1146    return false;
1147  }
1148
1149  RegStorage reg_class = TargetReg(kArg1, kRef);
1150  Clobber(reg_class);
1151  LockTemp(reg_class);
1152  if (use_direct_type_ptr) {
1153    LoadConstant(reg_class, direct_type_ptr);
1154  } else {
1155    uint16_t type_idx = ref.first->GetClassDef(ref.second).class_idx_;
1156    LoadClassType(*ref.first, type_idx, kArg1);
1157  }
1158
1159  uint32_t slow_path_flag_offset = cu_->compiler_driver->GetReferenceSlowFlagOffset();
1160  uint32_t disable_flag_offset = cu_->compiler_driver->GetReferenceDisableFlagOffset();
1161  CHECK(slow_path_flag_offset && disable_flag_offset &&
1162        (slow_path_flag_offset != disable_flag_offset));
1163
1164  // intrinsic logic start.
1165  RegLocation rl_obj = info->args[0];
1166  rl_obj = LoadValue(rl_obj, kRefReg);
1167
1168  RegStorage reg_slow_path = AllocTemp();
1169  RegStorage reg_disabled = AllocTemp();
1170  Load8Disp(reg_class, slow_path_flag_offset, reg_slow_path);
1171  Load8Disp(reg_class, disable_flag_offset, reg_disabled);
1172  FreeTemp(reg_class);
1173  LIR* or_inst = OpRegRegReg(kOpOr, reg_slow_path, reg_slow_path, reg_disabled);
1174  FreeTemp(reg_disabled);
1175
1176  // if slow path, jump to JNI path target
1177  LIR* slow_path_branch;
1178  if (or_inst->u.m.def_mask->HasBit(ResourceMask::kCCode)) {
1179    // Generate conditional branch only, as the OR set a condition state (we are interested in a 'Z' flag).
1180    slow_path_branch = OpCondBranch(kCondNe, nullptr);
1181  } else {
1182    // Generate compare and branch.
1183    slow_path_branch = OpCmpImmBranch(kCondNe, reg_slow_path, 0, nullptr);
1184  }
1185  FreeTemp(reg_slow_path);
1186
1187  // slow path not enabled, simply load the referent of the reference object
1188  RegLocation rl_dest = InlineTarget(info);
1189  RegLocation rl_result = EvalLoc(rl_dest, kRefReg, true);
1190  GenNullCheck(rl_obj.reg, info->opt_flags);
1191  LoadRefDisp(rl_obj.reg, mirror::Reference::ReferentOffset().Int32Value(), rl_result.reg,
1192      kNotVolatile);
1193  MarkPossibleNullPointerException(info->opt_flags);
1194  StoreValue(rl_dest, rl_result);
1195
1196  LIR* intrinsic_finish = NewLIR0(kPseudoTargetLabel);
1197  AddIntrinsicSlowPath(info, slow_path_branch, intrinsic_finish);
1198  ClobberCallerSave();  // We must clobber everything because slow path will return here
1199  return true;
1200}
1201
1202bool Mir2Lir::GenInlinedCharAt(CallInfo* info) {
1203  if (cu_->instruction_set == kMips) {
1204    // TODO - add Mips implementation
1205    return false;
1206  }
1207  // Location of reference to data array
1208  int value_offset = mirror::String::ValueOffset().Int32Value();
1209  // Location of count
1210  int count_offset = mirror::String::CountOffset().Int32Value();
1211  // Starting offset within data array
1212  int offset_offset = mirror::String::OffsetOffset().Int32Value();
1213  // Start of char data with array_
1214  int data_offset = mirror::Array::DataOffset(sizeof(uint16_t)).Int32Value();
1215
1216  RegLocation rl_obj = info->args[0];
1217  RegLocation rl_idx = info->args[1];
1218  rl_obj = LoadValue(rl_obj, kRefReg);
1219  rl_idx = LoadValue(rl_idx, kCoreReg);
1220  RegStorage reg_max;
1221  GenNullCheck(rl_obj.reg, info->opt_flags);
1222  bool range_check = (!(info->opt_flags & MIR_IGNORE_RANGE_CHECK));
1223  LIR* range_check_branch = nullptr;
1224  RegStorage reg_off;
1225  RegStorage reg_ptr;
1226  reg_off = AllocTemp();
1227  reg_ptr = AllocTempRef();
1228  if (range_check) {
1229    reg_max = AllocTemp();
1230    Load32Disp(rl_obj.reg, count_offset, reg_max);
1231    MarkPossibleNullPointerException(info->opt_flags);
1232  }
1233  Load32Disp(rl_obj.reg, offset_offset, reg_off);
1234  MarkPossibleNullPointerException(info->opt_flags);
1235  LoadRefDisp(rl_obj.reg, value_offset, reg_ptr, kNotVolatile);
1236  if (range_check) {
1237    // Set up a slow path to allow retry in case of bounds violation */
1238    OpRegReg(kOpCmp, rl_idx.reg, reg_max);
1239    FreeTemp(reg_max);
1240    range_check_branch = OpCondBranch(kCondUge, nullptr);
1241  }
1242  OpRegImm(kOpAdd, reg_ptr, data_offset);
1243  if (rl_idx.is_const) {
1244    OpRegImm(kOpAdd, reg_off, mir_graph_->ConstantValue(rl_idx.orig_sreg));
1245  } else {
1246    OpRegReg(kOpAdd, reg_off, rl_idx.reg);
1247  }
1248  FreeTemp(rl_obj.reg);
1249  if (rl_idx.location == kLocPhysReg) {
1250    FreeTemp(rl_idx.reg);
1251  }
1252  RegLocation rl_dest = InlineTarget(info);
1253  RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true);
1254  LoadBaseIndexed(reg_ptr, reg_off, rl_result.reg, 1, kUnsignedHalf);
1255  FreeTemp(reg_off);
1256  FreeTemp(reg_ptr);
1257  StoreValue(rl_dest, rl_result);
1258  if (range_check) {
1259    DCHECK(range_check_branch != nullptr);
1260    info->opt_flags |= MIR_IGNORE_NULL_CHECK;  // Record that we've already null checked.
1261    AddIntrinsicSlowPath(info, range_check_branch);
1262  }
1263  return true;
1264}
1265
1266// Generates an inlined String.is_empty or String.length.
1267bool Mir2Lir::GenInlinedStringIsEmptyOrLength(CallInfo* info, bool is_empty) {
1268  if (cu_->instruction_set == kMips) {
1269    // TODO - add Mips implementation
1270    return false;
1271  }
1272  // dst = src.length();
1273  RegLocation rl_obj = info->args[0];
1274  rl_obj = LoadValue(rl_obj, kRefReg);
1275  RegLocation rl_dest = InlineTarget(info);
1276  RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true);
1277  GenNullCheck(rl_obj.reg, info->opt_flags);
1278  Load32Disp(rl_obj.reg, mirror::String::CountOffset().Int32Value(), rl_result.reg);
1279  MarkPossibleNullPointerException(info->opt_flags);
1280  if (is_empty) {
1281    // dst = (dst == 0);
1282    if (cu_->instruction_set == kThumb2) {
1283      RegStorage t_reg = AllocTemp();
1284      OpRegReg(kOpNeg, t_reg, rl_result.reg);
1285      OpRegRegReg(kOpAdc, rl_result.reg, rl_result.reg, t_reg);
1286    } else if (cu_->instruction_set == kArm64) {
1287      OpRegImm(kOpSub, rl_result.reg, 1);
1288      OpRegRegImm(kOpLsr, rl_result.reg, rl_result.reg, 31);
1289    } else {
1290      DCHECK(cu_->instruction_set == kX86 || cu_->instruction_set == kX86_64);
1291      OpRegImm(kOpSub, rl_result.reg, 1);
1292      OpRegImm(kOpLsr, rl_result.reg, 31);
1293    }
1294  }
1295  StoreValue(rl_dest, rl_result);
1296  return true;
1297}
1298
1299bool Mir2Lir::GenInlinedReverseBytes(CallInfo* info, OpSize size) {
1300  if (cu_->instruction_set == kMips) {
1301    // TODO - add Mips implementation.
1302    return false;
1303  }
1304  RegLocation rl_src_i = info->args[0];
1305  RegLocation rl_i = IsWide(size) ? LoadValueWide(rl_src_i, kCoreReg) : LoadValue(rl_src_i, kCoreReg);
1306  RegLocation rl_dest = IsWide(size) ? InlineTargetWide(info) : InlineTarget(info);  // result reg
1307  RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true);
1308  if (IsWide(size)) {
1309    if (cu_->instruction_set == kArm64 || cu_->instruction_set == kX86_64) {
1310      OpRegReg(kOpRev, rl_result.reg, rl_i.reg);
1311      StoreValueWide(rl_dest, rl_result);
1312      return true;
1313    }
1314    RegStorage r_i_low = rl_i.reg.GetLow();
1315    if (rl_i.reg.GetLowReg() == rl_result.reg.GetLowReg()) {
1316      // First REV shall clobber rl_result.reg.GetReg(), save the value in a temp for the second REV.
1317      r_i_low = AllocTemp();
1318      OpRegCopy(r_i_low, rl_i.reg);
1319    }
1320    OpRegReg(kOpRev, rl_result.reg.GetLow(), rl_i.reg.GetHigh());
1321    OpRegReg(kOpRev, rl_result.reg.GetHigh(), r_i_low);
1322    if (rl_i.reg.GetLowReg() == rl_result.reg.GetLowReg()) {
1323      FreeTemp(r_i_low);
1324    }
1325    StoreValueWide(rl_dest, rl_result);
1326  } else {
1327    DCHECK(size == k32 || size == kSignedHalf);
1328    OpKind op = (size == k32) ? kOpRev : kOpRevsh;
1329    OpRegReg(op, rl_result.reg, rl_i.reg);
1330    StoreValue(rl_dest, rl_result);
1331  }
1332  return true;
1333}
1334
1335bool Mir2Lir::GenInlinedAbsInt(CallInfo* info) {
1336  if (cu_->instruction_set == kMips) {
1337    // TODO - add Mips implementation
1338    return false;
1339  }
1340  RegLocation rl_src = info->args[0];
1341  rl_src = LoadValue(rl_src, kCoreReg);
1342  RegLocation rl_dest = InlineTarget(info);
1343  RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true);
1344  RegStorage sign_reg = AllocTemp();
1345  // abs(x) = y<=x>>31, (x+y)^y.
1346  OpRegRegImm(kOpAsr, sign_reg, rl_src.reg, 31);
1347  OpRegRegReg(kOpAdd, rl_result.reg, rl_src.reg, sign_reg);
1348  OpRegReg(kOpXor, rl_result.reg, sign_reg);
1349  StoreValue(rl_dest, rl_result);
1350  return true;
1351}
1352
1353bool Mir2Lir::GenInlinedAbsLong(CallInfo* info) {
1354  if (cu_->instruction_set == kMips) {
1355    // TODO - add Mips implementation
1356    return false;
1357  }
1358  RegLocation rl_src = info->args[0];
1359  rl_src = LoadValueWide(rl_src, kCoreReg);
1360  RegLocation rl_dest = InlineTargetWide(info);
1361  RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true);
1362
1363  // If on x86 or if we would clobber a register needed later, just copy the source first.
1364  if (cu_->instruction_set != kX86_64 &&
1365      (cu_->instruction_set == kX86 ||
1366       rl_result.reg.GetLowReg() == rl_src.reg.GetHighReg())) {
1367    OpRegCopyWide(rl_result.reg, rl_src.reg);
1368    if (rl_result.reg.GetLowReg() != rl_src.reg.GetLowReg() &&
1369        rl_result.reg.GetLowReg() != rl_src.reg.GetHighReg() &&
1370        rl_result.reg.GetHighReg() != rl_src.reg.GetLowReg() &&
1371        rl_result.reg.GetHighReg() != rl_src.reg.GetHighReg()) {
1372      // Reuse source registers to avoid running out of temps.
1373      FreeTemp(rl_src.reg);
1374    }
1375    rl_src = rl_result;
1376  }
1377
1378  // abs(x) = y<=x>>31, (x+y)^y.
1379  RegStorage sign_reg;
1380  if (cu_->instruction_set == kX86_64) {
1381    sign_reg = AllocTempWide();
1382    OpRegRegImm(kOpAsr, sign_reg, rl_src.reg, 63);
1383    OpRegRegReg(kOpAdd, rl_result.reg, rl_src.reg, sign_reg);
1384    OpRegReg(kOpXor, rl_result.reg, sign_reg);
1385  } else {
1386    sign_reg = AllocTemp();
1387    OpRegRegImm(kOpAsr, sign_reg, rl_src.reg.GetHigh(), 31);
1388    OpRegRegReg(kOpAdd, rl_result.reg.GetLow(), rl_src.reg.GetLow(), sign_reg);
1389    OpRegRegReg(kOpAdc, rl_result.reg.GetHigh(), rl_src.reg.GetHigh(), sign_reg);
1390    OpRegReg(kOpXor, rl_result.reg.GetLow(), sign_reg);
1391    OpRegReg(kOpXor, rl_result.reg.GetHigh(), sign_reg);
1392  }
1393  FreeTemp(sign_reg);
1394  StoreValueWide(rl_dest, rl_result);
1395  return true;
1396}
1397
1398bool Mir2Lir::GenInlinedReverseBits(CallInfo* info, OpSize size) {
1399  // Currently implemented only for ARM64
1400  return false;
1401}
1402
1403bool Mir2Lir::GenInlinedMinMaxFP(CallInfo* info, bool is_min, bool is_double) {
1404  // Currently implemented only for ARM64
1405  return false;
1406}
1407
1408bool Mir2Lir::GenInlinedCeil(CallInfo* info) {
1409  return false;
1410}
1411
1412bool Mir2Lir::GenInlinedFloor(CallInfo* info) {
1413  return false;
1414}
1415
1416bool Mir2Lir::GenInlinedRint(CallInfo* info) {
1417  return false;
1418}
1419
1420bool Mir2Lir::GenInlinedRound(CallInfo* info, bool is_double) {
1421  return false;
1422}
1423
1424bool Mir2Lir::GenInlinedFloatCvt(CallInfo* info) {
1425  if (cu_->instruction_set == kMips) {
1426    // TODO - add Mips implementation
1427    return false;
1428  }
1429  RegLocation rl_src = info->args[0];
1430  RegLocation rl_dest = InlineTarget(info);
1431  StoreValue(rl_dest, rl_src);
1432  return true;
1433}
1434
1435bool Mir2Lir::GenInlinedDoubleCvt(CallInfo* info) {
1436  if (cu_->instruction_set == kMips) {
1437    // TODO - add Mips implementation
1438    return false;
1439  }
1440  RegLocation rl_src = info->args[0];
1441  RegLocation rl_dest = InlineTargetWide(info);
1442  StoreValueWide(rl_dest, rl_src);
1443  return true;
1444}
1445
1446bool Mir2Lir::GenInlinedArrayCopyCharArray(CallInfo* info) {
1447  return false;
1448}
1449
1450
1451/*
1452 * Fast String.indexOf(I) & (II).  Tests for simple case of char <= 0xFFFF,
1453 * otherwise bails to standard library code.
1454 */
1455bool Mir2Lir::GenInlinedIndexOf(CallInfo* info, bool zero_based) {
1456  if (cu_->instruction_set == kMips) {
1457    // TODO - add Mips implementation
1458    return false;
1459  }
1460  if (cu_->instruction_set == kX86_64) {
1461    // TODO - add kX86_64 implementation
1462    return false;
1463  }
1464  RegLocation rl_obj = info->args[0];
1465  RegLocation rl_char = info->args[1];
1466  if (rl_char.is_const && (mir_graph_->ConstantValue(rl_char) & ~0xFFFF) != 0) {
1467    // Code point beyond 0xFFFF. Punt to the real String.indexOf().
1468    return false;
1469  }
1470
1471  ClobberCallerSave();
1472  LockCallTemps();  // Using fixed registers
1473  RegStorage reg_ptr = TargetReg(kArg0, kRef);
1474  RegStorage reg_char = TargetReg(kArg1, kNotWide);
1475  RegStorage reg_start = TargetReg(kArg2, kNotWide);
1476
1477  LoadValueDirectFixed(rl_obj, reg_ptr);
1478  LoadValueDirectFixed(rl_char, reg_char);
1479  if (zero_based) {
1480    LoadConstant(reg_start, 0);
1481  } else {
1482    RegLocation rl_start = info->args[2];     // 3rd arg only present in III flavor of IndexOf.
1483    LoadValueDirectFixed(rl_start, reg_start);
1484  }
1485  RegStorage r_tgt = LoadHelper(kQuickIndexOf);
1486  GenExplicitNullCheck(reg_ptr, info->opt_flags);
1487  LIR* high_code_point_branch =
1488      rl_char.is_const ? nullptr : OpCmpImmBranch(kCondGt, reg_char, 0xFFFF, nullptr);
1489  // NOTE: not a safepoint
1490  OpReg(kOpBlx, r_tgt);
1491  if (!rl_char.is_const) {
1492    // Add the slow path for code points beyond 0xFFFF.
1493    DCHECK(high_code_point_branch != nullptr);
1494    LIR* resume_tgt = NewLIR0(kPseudoTargetLabel);
1495    info->opt_flags |= MIR_IGNORE_NULL_CHECK;  // Record that we've null checked.
1496    AddIntrinsicSlowPath(info, high_code_point_branch, resume_tgt);
1497    ClobberCallerSave();  // We must clobber everything because slow path will return here
1498  } else {
1499    DCHECK_EQ(mir_graph_->ConstantValue(rl_char) & ~0xFFFF, 0);
1500    DCHECK(high_code_point_branch == nullptr);
1501  }
1502  RegLocation rl_return = GetReturn(kCoreReg);
1503  RegLocation rl_dest = InlineTarget(info);
1504  StoreValue(rl_dest, rl_return);
1505  return true;
1506}
1507
1508/* Fast string.compareTo(Ljava/lang/string;)I. */
1509bool Mir2Lir::GenInlinedStringCompareTo(CallInfo* info) {
1510  if (cu_->instruction_set == kMips) {
1511    // TODO - add Mips implementation
1512    return false;
1513  }
1514  ClobberCallerSave();
1515  LockCallTemps();  // Using fixed registers
1516  RegStorage reg_this = TargetReg(kArg0, kRef);
1517  RegStorage reg_cmp = TargetReg(kArg1, kRef);
1518
1519  RegLocation rl_this = info->args[0];
1520  RegLocation rl_cmp = info->args[1];
1521  LoadValueDirectFixed(rl_this, reg_this);
1522  LoadValueDirectFixed(rl_cmp, reg_cmp);
1523  RegStorage r_tgt;
1524  if (cu_->instruction_set != kX86 && cu_->instruction_set != kX86_64) {
1525    r_tgt = LoadHelper(kQuickStringCompareTo);
1526  } else {
1527    r_tgt = RegStorage::InvalidReg();
1528  }
1529  GenExplicitNullCheck(reg_this, info->opt_flags);
1530  info->opt_flags |= MIR_IGNORE_NULL_CHECK;  // Record that we've null checked.
1531  // TUNING: check if rl_cmp.s_reg_low is already null checked
1532  LIR* cmp_null_check_branch = OpCmpImmBranch(kCondEq, reg_cmp, 0, nullptr);
1533  AddIntrinsicSlowPath(info, cmp_null_check_branch);
1534  // NOTE: not a safepoint
1535  CallHelper(r_tgt, kQuickStringCompareTo, false, true);
1536  RegLocation rl_return = GetReturn(kCoreReg);
1537  RegLocation rl_dest = InlineTarget(info);
1538  StoreValue(rl_dest, rl_return);
1539  return true;
1540}
1541
1542bool Mir2Lir::GenInlinedCurrentThread(CallInfo* info) {
1543  RegLocation rl_dest = InlineTarget(info);
1544
1545  // Early exit if the result is unused.
1546  if (rl_dest.orig_sreg < 0) {
1547    return true;
1548  }
1549
1550  RegLocation rl_result = EvalLoc(rl_dest, kRefReg, true);
1551
1552  switch (cu_->instruction_set) {
1553    case kArm:
1554      // Fall-through.
1555    case kThumb2:
1556      // Fall-through.
1557    case kMips:
1558      Load32Disp(TargetPtrReg(kSelf), Thread::PeerOffset<4>().Int32Value(), rl_result.reg);
1559      break;
1560
1561    case kArm64:
1562      LoadRefDisp(TargetPtrReg(kSelf), Thread::PeerOffset<8>().Int32Value(), rl_result.reg,
1563                  kNotVolatile);
1564      break;
1565
1566    default:
1567      LOG(FATAL) << "Unexpected isa " << cu_->instruction_set;
1568  }
1569  StoreValue(rl_dest, rl_result);
1570  return true;
1571}
1572
1573bool Mir2Lir::GenInlinedUnsafeGet(CallInfo* info,
1574                                  bool is_long, bool is_volatile) {
1575  if (cu_->instruction_set == kMips) {
1576    // TODO - add Mips implementation
1577    return false;
1578  }
1579  // Unused - RegLocation rl_src_unsafe = info->args[0];
1580  RegLocation rl_src_obj = info->args[1];  // Object
1581  RegLocation rl_src_offset = info->args[2];  // long low
1582  rl_src_offset = NarrowRegLoc(rl_src_offset);  // ignore high half in info->args[3]
1583  RegLocation rl_dest = is_long ? InlineTargetWide(info) : InlineTarget(info);  // result reg
1584
1585  RegLocation rl_object = LoadValue(rl_src_obj, kRefReg);
1586  RegLocation rl_offset = LoadValue(rl_src_offset, kCoreReg);
1587  RegLocation rl_result = EvalLoc(rl_dest, LocToRegClass(rl_dest), true);
1588  if (is_long) {
1589    if (cu_->instruction_set == kX86 || cu_->instruction_set == kX86_64
1590        || cu_->instruction_set == kArm64) {
1591      LoadBaseIndexed(rl_object.reg, rl_offset.reg, rl_result.reg, 0, k64);
1592    } else {
1593      RegStorage rl_temp_offset = AllocTemp();
1594      OpRegRegReg(kOpAdd, rl_temp_offset, rl_object.reg, rl_offset.reg);
1595      LoadBaseDisp(rl_temp_offset, 0, rl_result.reg, k64, kNotVolatile);
1596      FreeTemp(rl_temp_offset);
1597    }
1598  } else {
1599    if (rl_result.ref) {
1600      LoadRefIndexed(rl_object.reg, rl_offset.reg, rl_result.reg, 0);
1601    } else {
1602      LoadBaseIndexed(rl_object.reg, rl_offset.reg, rl_result.reg, 0, k32);
1603    }
1604  }
1605
1606  if (is_volatile) {
1607    GenMemBarrier(kLoadAny);
1608  }
1609
1610  if (is_long) {
1611    StoreValueWide(rl_dest, rl_result);
1612  } else {
1613    StoreValue(rl_dest, rl_result);
1614  }
1615  return true;
1616}
1617
1618bool Mir2Lir::GenInlinedUnsafePut(CallInfo* info, bool is_long,
1619                                  bool is_object, bool is_volatile, bool is_ordered) {
1620  if (cu_->instruction_set == kMips) {
1621    // TODO - add Mips implementation
1622    return false;
1623  }
1624  // Unused - RegLocation rl_src_unsafe = info->args[0];
1625  RegLocation rl_src_obj = info->args[1];  // Object
1626  RegLocation rl_src_offset = info->args[2];  // long low
1627  rl_src_offset = NarrowRegLoc(rl_src_offset);  // ignore high half in info->args[3]
1628  RegLocation rl_src_value = info->args[4];  // value to store
1629  if (is_volatile || is_ordered) {
1630    GenMemBarrier(kAnyStore);
1631  }
1632  RegLocation rl_object = LoadValue(rl_src_obj, kRefReg);
1633  RegLocation rl_offset = LoadValue(rl_src_offset, kCoreReg);
1634  RegLocation rl_value;
1635  if (is_long) {
1636    rl_value = LoadValueWide(rl_src_value, kCoreReg);
1637    if (cu_->instruction_set == kX86 || cu_->instruction_set == kX86_64
1638        || cu_->instruction_set == kArm64) {
1639      StoreBaseIndexed(rl_object.reg, rl_offset.reg, rl_value.reg, 0, k64);
1640    } else {
1641      RegStorage rl_temp_offset = AllocTemp();
1642      OpRegRegReg(kOpAdd, rl_temp_offset, rl_object.reg, rl_offset.reg);
1643      StoreBaseDisp(rl_temp_offset, 0, rl_value.reg, k64, kNotVolatile);
1644      FreeTemp(rl_temp_offset);
1645    }
1646  } else {
1647    rl_value = LoadValue(rl_src_value);
1648    if (rl_value.ref) {
1649      StoreRefIndexed(rl_object.reg, rl_offset.reg, rl_value.reg, 0);
1650    } else {
1651      StoreBaseIndexed(rl_object.reg, rl_offset.reg, rl_value.reg, 0, k32);
1652    }
1653  }
1654
1655  // Free up the temp early, to ensure x86 doesn't run out of temporaries in MarkGCCard.
1656  FreeTemp(rl_offset.reg);
1657
1658  if (is_volatile) {
1659    // Prevent reordering with a subsequent volatile load.
1660    // May also be needed to address store atomicity issues.
1661    GenMemBarrier(kAnyAny);
1662  }
1663  if (is_object) {
1664    MarkGCCard(rl_value.reg, rl_object.reg);
1665  }
1666  return true;
1667}
1668
1669void Mir2Lir::GenInvoke(CallInfo* info) {
1670  DCHECK(cu_->compiler_driver->GetMethodInlinerMap() != nullptr);
1671  if (cu_->compiler_driver->GetMethodInlinerMap()->GetMethodInliner(cu_->dex_file)
1672      ->GenIntrinsic(this, info)) {
1673    return;
1674  }
1675  GenInvokeNoInline(info);
1676}
1677
1678void Mir2Lir::GenInvokeNoInline(CallInfo* info) {
1679  int call_state = 0;
1680  LIR* null_ck;
1681  LIR** p_null_ck = NULL;
1682  NextCallInsn next_call_insn;
1683  FlushAllRegs();  /* Everything to home location */
1684  // Explicit register usage
1685  LockCallTemps();
1686
1687  const MirMethodLoweringInfo& method_info = mir_graph_->GetMethodLoweringInfo(info->mir);
1688  cu_->compiler_driver->ProcessedInvoke(method_info.GetInvokeType(), method_info.StatsFlags());
1689  BeginInvoke(info);
1690  InvokeType original_type = static_cast<InvokeType>(method_info.GetInvokeType());
1691  info->type = method_info.GetSharpType();
1692  bool fast_path = method_info.FastPath();
1693  bool skip_this;
1694  if (info->type == kInterface) {
1695    next_call_insn = fast_path ? NextInterfaceCallInsn : NextInterfaceCallInsnWithAccessCheck;
1696    skip_this = fast_path;
1697  } else if (info->type == kDirect) {
1698    if (fast_path) {
1699      p_null_ck = &null_ck;
1700    }
1701    next_call_insn = fast_path ? GetNextSDCallInsn() : NextDirectCallInsnSP;
1702    skip_this = false;
1703  } else if (info->type == kStatic) {
1704    next_call_insn = fast_path ? GetNextSDCallInsn() : NextStaticCallInsnSP;
1705    skip_this = false;
1706  } else if (info->type == kSuper) {
1707    DCHECK(!fast_path);  // Fast path is a direct call.
1708    next_call_insn = NextSuperCallInsnSP;
1709    skip_this = false;
1710  } else {
1711    DCHECK_EQ(info->type, kVirtual);
1712    next_call_insn = fast_path ? NextVCallInsn : NextVCallInsnSP;
1713    skip_this = fast_path;
1714  }
1715  MethodReference target_method = method_info.GetTargetMethod();
1716  if (!info->is_range) {
1717    call_state = GenDalvikArgsNoRange(info, call_state, p_null_ck,
1718                                      next_call_insn, target_method, method_info.VTableIndex(),
1719                                      method_info.DirectCode(), method_info.DirectMethod(),
1720                                      original_type, skip_this);
1721  } else {
1722    call_state = GenDalvikArgsRange(info, call_state, p_null_ck,
1723                                    next_call_insn, target_method, method_info.VTableIndex(),
1724                                    method_info.DirectCode(), method_info.DirectMethod(),
1725                                    original_type, skip_this);
1726  }
1727  // Finish up any of the call sequence not interleaved in arg loading
1728  while (call_state >= 0) {
1729    call_state = next_call_insn(cu_, info, call_state, target_method, method_info.VTableIndex(),
1730                                method_info.DirectCode(), method_info.DirectMethod(), original_type);
1731  }
1732  LIR* call_insn = GenCallInsn(method_info);
1733  EndInvoke(info);
1734  MarkSafepointPC(call_insn);
1735
1736  ClobberCallerSave();
1737  if (info->result.location != kLocInvalid) {
1738    // We have a following MOVE_RESULT - do it now.
1739    if (info->result.wide) {
1740      RegLocation ret_loc = GetReturnWide(LocToRegClass(info->result));
1741      StoreValueWide(info->result, ret_loc);
1742    } else {
1743      RegLocation ret_loc = GetReturn(LocToRegClass(info->result));
1744      StoreValue(info->result, ret_loc);
1745    }
1746  }
1747}
1748
1749NextCallInsn Mir2Lir::GetNextSDCallInsn() {
1750  return NextSDCallInsn;
1751}
1752
1753LIR* Mir2Lir::GenCallInsn(const MirMethodLoweringInfo& method_info) {
1754  DCHECK(cu_->instruction_set != kX86 && cu_->instruction_set != kX86_64 &&
1755         cu_->instruction_set != kThumb2 && cu_->instruction_set != kArm &&
1756         cu_->instruction_set != kArm64);
1757  return OpReg(kOpBlx, TargetPtrReg(kInvokeTgt));
1758}
1759
1760}  // namespace art
1761