1/*
2 * Copyright © 2011 Red Hat All Rights Reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining
5 * a copy of this software and associated documentation files (the
6 * "Software"), to deal in the Software without restriction, including
7 * without limitation the rights to use, copy, modify, merge, publish,
8 * distribute, sub license, and/or sell copies of the Software, and to
9 * permit persons to whom the Software is furnished to do so, subject to
10 * the following conditions:
11 *
12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
13 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
14 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
15 * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
16 * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
17 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
18 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
20 *
21 * The above copyright notice and this permission notice (including the
22 * next paragraph) shall be included in all copies or substantial portions
23 * of the Software.
24 */
25/*
26 * Authors:
27 *      Jérôme Glisse <jglisse@redhat.com>
28 */
29#ifndef RADEON_SURFACE_H
30#define RADEON_SURFACE_H
31
32/* Note :
33 *
34 * For texture array, the n layer are stored one after the other within each
35 * mipmap level. 0 value for field than can be hint is always valid.
36 */
37
38#define RADEON_SURF_MAX_LEVEL                   32
39
40#define RADEON_SURF_TYPE_MASK                   0xFF
41#define RADEON_SURF_TYPE_SHIFT                  0
42#define     RADEON_SURF_TYPE_1D                     0
43#define     RADEON_SURF_TYPE_2D                     1
44#define     RADEON_SURF_TYPE_3D                     2
45#define     RADEON_SURF_TYPE_CUBEMAP                3
46#define     RADEON_SURF_TYPE_1D_ARRAY               4
47#define     RADEON_SURF_TYPE_2D_ARRAY               5
48#define RADEON_SURF_MODE_MASK                   0xFF
49#define RADEON_SURF_MODE_SHIFT                  8
50#define     RADEON_SURF_MODE_LINEAR                 0
51#define     RADEON_SURF_MODE_LINEAR_ALIGNED         1
52#define     RADEON_SURF_MODE_1D                     2
53#define     RADEON_SURF_MODE_2D                     3
54#define RADEON_SURF_SCANOUT                     (1 << 16)
55#define RADEON_SURF_ZBUFFER                     (1 << 17)
56#define RADEON_SURF_SBUFFER                     (1 << 18)
57#define RADEON_SURF_Z_OR_SBUFFER                (RADEON_SURF_ZBUFFER | RADEON_SURF_SBUFFER)
58#define RADEON_SURF_HAS_SBUFFER_MIPTREE         (1 << 19)
59#define RADEON_SURF_HAS_TILE_MODE_INDEX         (1 << 20)
60#define RADEON_SURF_FMASK                       (1 << 21)
61
62#define RADEON_SURF_GET(v, field)   (((v) >> RADEON_SURF_ ## field ## _SHIFT) & RADEON_SURF_ ## field ## _MASK)
63#define RADEON_SURF_SET(v, field)   (((v) & RADEON_SURF_ ## field ## _MASK) << RADEON_SURF_ ## field ## _SHIFT)
64#define RADEON_SURF_CLR(v, field)   ((v) & ~(RADEON_SURF_ ## field ## _MASK << RADEON_SURF_ ## field ## _SHIFT))
65
66/* first field up to mode need to match r6 struct so that we can reuse
67 * same function for linear & linear aligned
68 */
69struct radeon_surface_level {
70    uint64_t                    offset;
71    uint64_t                    slice_size;
72    uint32_t                    npix_x;
73    uint32_t                    npix_y;
74    uint32_t                    npix_z;
75    uint32_t                    nblk_x;
76    uint32_t                    nblk_y;
77    uint32_t                    nblk_z;
78    uint32_t                    pitch_bytes;
79    uint32_t                    mode;
80};
81
82enum si_tiling_mode {
83    SI_TILING_AUTO = 0,
84
85    SI_TILING_COLOR_1D,
86    SI_TILING_COLOR_1D_SCANOUT,
87    SI_TILING_COLOR_2D_8BPP,
88    SI_TILING_COLOR_2D_16BPP,
89    SI_TILING_COLOR_2D_32BPP,
90    SI_TILING_COLOR_2D_64BPP,
91    SI_TILING_COLOR_2D_SCANOUT_16BPP,
92    SI_TILING_COLOR_2D_SCANOUT_32BPP,
93    SI_TILING_COLOR_LINEAR,
94
95    SI_TILING_STENCIL_1D,
96    SI_TILING_STENCIL_2D,
97    SI_TILING_STENCIL_2D_2AA,
98    SI_TILING_STENCIL_2D_4AA,
99    SI_TILING_STENCIL_2D_8AA,
100
101    SI_TILING_DEPTH_1D,
102    SI_TILING_DEPTH_2D,
103    SI_TILING_DEPTH_2D_2AA,
104    SI_TILING_DEPTH_2D_4AA,
105    SI_TILING_DEPTH_2D_8AA,
106
107    SI_TILING_LAST_MODE,
108};
109
110struct radeon_surface {
111    uint32_t                    npix_x;
112    uint32_t                    npix_y;
113    uint32_t                    npix_z;
114    uint32_t                    blk_w;
115    uint32_t                    blk_h;
116    uint32_t                    blk_d;
117    uint32_t                    array_size;
118    uint32_t                    last_level;
119    uint32_t                    bpe;
120    uint32_t                    nsamples;
121    uint32_t                    flags;
122    /* Following is updated/fill by the allocator. It's allowed to
123     * set some of the value but they are use as hint and can be
124     * overridden (things lile bankw/bankh on evergreen for
125     * instance).
126     */
127    uint64_t                    bo_size;
128    uint64_t                    bo_alignment;
129    /* apply to eg */
130    uint32_t                    bankw;
131    uint32_t                    bankh;
132    uint32_t                    mtilea;
133    uint32_t                    tile_split;
134    uint32_t                    stencil_tile_split;
135    uint64_t                    stencil_offset;
136    struct radeon_surface_level level[RADEON_SURF_MAX_LEVEL];
137    struct radeon_surface_level stencil_level[RADEON_SURF_MAX_LEVEL];
138    uint32_t                    tiling_index[RADEON_SURF_MAX_LEVEL];
139    uint32_t                    stencil_tiling_index[RADEON_SURF_MAX_LEVEL];
140};
141
142struct radeon_surface_manager *radeon_surface_manager_new(int fd);
143void radeon_surface_manager_free(struct radeon_surface_manager *surf_man);
144int radeon_surface_init(struct radeon_surface_manager *surf_man,
145                        struct radeon_surface *surf);
146int radeon_surface_best(struct radeon_surface_manager *surf_man,
147                        struct radeon_surface *surf);
148
149#endif
150