1//==-- AArch64InstPrinter.cpp - Convert AArch64 MCInst to assembly syntax --==// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This class prints an AArch64 MCInst to a .s file. 11// 12//===----------------------------------------------------------------------===// 13 14#include "AArch64InstPrinter.h" 15#include "MCTargetDesc/AArch64AddressingModes.h" 16#include "Utils/AArch64BaseInfo.h" 17#include "llvm/ADT/STLExtras.h" 18#include "llvm/ADT/StringExtras.h" 19#include "llvm/MC/MCExpr.h" 20#include "llvm/MC/MCInst.h" 21#include "llvm/MC/MCRegisterInfo.h" 22#include "llvm/Support/Format.h" 23#include "llvm/Support/raw_ostream.h" 24using namespace llvm; 25 26#define DEBUG_TYPE "asm-printer" 27 28#define GET_INSTRUCTION_NAME 29#define PRINT_ALIAS_INSTR 30#include "AArch64GenAsmWriter.inc" 31#define GET_INSTRUCTION_NAME 32#define PRINT_ALIAS_INSTR 33#include "AArch64GenAsmWriter1.inc" 34 35AArch64InstPrinter::AArch64InstPrinter(const MCAsmInfo &MAI, 36 const MCInstrInfo &MII, 37 const MCRegisterInfo &MRI) 38 : MCInstPrinter(MAI, MII, MRI) {} 39 40AArch64AppleInstPrinter::AArch64AppleInstPrinter(const MCAsmInfo &MAI, 41 const MCInstrInfo &MII, 42 const MCRegisterInfo &MRI) 43 : AArch64InstPrinter(MAI, MII, MRI) {} 44 45void AArch64InstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const { 46 // This is for .cfi directives. 47 OS << getRegisterName(RegNo); 48} 49 50void AArch64InstPrinter::printInst(const MCInst *MI, raw_ostream &O, 51 StringRef Annot, 52 const MCSubtargetInfo &STI) { 53 // Check for special encodings and print the canonical alias instead. 54 55 unsigned Opcode = MI->getOpcode(); 56 57 if (Opcode == AArch64::SYSxt) 58 if (printSysAlias(MI, O)) { 59 printAnnotation(O, Annot); 60 return; 61 } 62 63 // SBFM/UBFM should print to a nicer aliased form if possible. 64 if (Opcode == AArch64::SBFMXri || Opcode == AArch64::SBFMWri || 65 Opcode == AArch64::UBFMXri || Opcode == AArch64::UBFMWri) { 66 const MCOperand &Op0 = MI->getOperand(0); 67 const MCOperand &Op1 = MI->getOperand(1); 68 const MCOperand &Op2 = MI->getOperand(2); 69 const MCOperand &Op3 = MI->getOperand(3); 70 71 bool IsSigned = (Opcode == AArch64::SBFMXri || Opcode == AArch64::SBFMWri); 72 bool Is64Bit = (Opcode == AArch64::SBFMXri || Opcode == AArch64::UBFMXri); 73 if (Op2.isImm() && Op2.getImm() == 0 && Op3.isImm()) { 74 const char *AsmMnemonic = nullptr; 75 76 switch (Op3.getImm()) { 77 default: 78 break; 79 case 7: 80 if (IsSigned) 81 AsmMnemonic = "sxtb"; 82 else if (!Is64Bit) 83 AsmMnemonic = "uxtb"; 84 break; 85 case 15: 86 if (IsSigned) 87 AsmMnemonic = "sxth"; 88 else if (!Is64Bit) 89 AsmMnemonic = "uxth"; 90 break; 91 case 31: 92 // *xtw is only valid for signed 64-bit operations. 93 if (Is64Bit && IsSigned) 94 AsmMnemonic = "sxtw"; 95 break; 96 } 97 98 if (AsmMnemonic) { 99 O << '\t' << AsmMnemonic << '\t' << getRegisterName(Op0.getReg()) 100 << ", " << getRegisterName(getWRegFromXReg(Op1.getReg())); 101 printAnnotation(O, Annot); 102 return; 103 } 104 } 105 106 // All immediate shifts are aliases, implemented using the Bitfield 107 // instruction. In all cases the immediate shift amount shift must be in 108 // the range 0 to (reg.size -1). 109 if (Op2.isImm() && Op3.isImm()) { 110 const char *AsmMnemonic = nullptr; 111 int shift = 0; 112 int64_t immr = Op2.getImm(); 113 int64_t imms = Op3.getImm(); 114 if (Opcode == AArch64::UBFMWri && imms != 0x1F && ((imms + 1) == immr)) { 115 AsmMnemonic = "lsl"; 116 shift = 31 - imms; 117 } else if (Opcode == AArch64::UBFMXri && imms != 0x3f && 118 ((imms + 1 == immr))) { 119 AsmMnemonic = "lsl"; 120 shift = 63 - imms; 121 } else if (Opcode == AArch64::UBFMWri && imms == 0x1f) { 122 AsmMnemonic = "lsr"; 123 shift = immr; 124 } else if (Opcode == AArch64::UBFMXri && imms == 0x3f) { 125 AsmMnemonic = "lsr"; 126 shift = immr; 127 } else if (Opcode == AArch64::SBFMWri && imms == 0x1f) { 128 AsmMnemonic = "asr"; 129 shift = immr; 130 } else if (Opcode == AArch64::SBFMXri && imms == 0x3f) { 131 AsmMnemonic = "asr"; 132 shift = immr; 133 } 134 if (AsmMnemonic) { 135 O << '\t' << AsmMnemonic << '\t' << getRegisterName(Op0.getReg()) 136 << ", " << getRegisterName(Op1.getReg()) << ", #" << shift; 137 printAnnotation(O, Annot); 138 return; 139 } 140 } 141 142 // SBFIZ/UBFIZ aliases 143 if (Op2.getImm() > Op3.getImm()) { 144 O << '\t' << (IsSigned ? "sbfiz" : "ubfiz") << '\t' 145 << getRegisterName(Op0.getReg()) << ", " << getRegisterName(Op1.getReg()) 146 << ", #" << (Is64Bit ? 64 : 32) - Op2.getImm() << ", #" << Op3.getImm() + 1; 147 printAnnotation(O, Annot); 148 return; 149 } 150 151 // Otherwise SBFX/UBFX is the preferred form 152 O << '\t' << (IsSigned ? "sbfx" : "ubfx") << '\t' 153 << getRegisterName(Op0.getReg()) << ", " << getRegisterName(Op1.getReg()) 154 << ", #" << Op2.getImm() << ", #" << Op3.getImm() - Op2.getImm() + 1; 155 printAnnotation(O, Annot); 156 return; 157 } 158 159 if (Opcode == AArch64::BFMXri || Opcode == AArch64::BFMWri) { 160 const MCOperand &Op0 = MI->getOperand(0); // Op1 == Op0 161 const MCOperand &Op2 = MI->getOperand(2); 162 int ImmR = MI->getOperand(3).getImm(); 163 int ImmS = MI->getOperand(4).getImm(); 164 165 // BFI alias 166 if (ImmS < ImmR) { 167 int BitWidth = Opcode == AArch64::BFMXri ? 64 : 32; 168 int LSB = (BitWidth - ImmR) % BitWidth; 169 int Width = ImmS + 1; 170 O << "\tbfi\t" << getRegisterName(Op0.getReg()) << ", " 171 << getRegisterName(Op2.getReg()) << ", #" << LSB << ", #" << Width; 172 printAnnotation(O, Annot); 173 return; 174 } 175 176 int LSB = ImmR; 177 int Width = ImmS - ImmR + 1; 178 // Otherwise BFXIL the preferred form 179 O << "\tbfxil\t" 180 << getRegisterName(Op0.getReg()) << ", " << getRegisterName(Op2.getReg()) 181 << ", #" << LSB << ", #" << Width; 182 printAnnotation(O, Annot); 183 return; 184 } 185 186 // Symbolic operands for MOVZ, MOVN and MOVK already imply a shift 187 // (e.g. :gottprel_g1: is always going to be "lsl #16") so it should not be 188 // printed. 189 if ((Opcode == AArch64::MOVZXi || Opcode == AArch64::MOVZWi || 190 Opcode == AArch64::MOVNXi || Opcode == AArch64::MOVNWi) && 191 MI->getOperand(1).isExpr()) { 192 if (Opcode == AArch64::MOVZXi || Opcode == AArch64::MOVZWi) 193 O << "\tmovz\t"; 194 else 195 O << "\tmovn\t"; 196 197 O << getRegisterName(MI->getOperand(0).getReg()) << ", #" 198 << *MI->getOperand(1).getExpr(); 199 return; 200 } 201 202 if ((Opcode == AArch64::MOVKXi || Opcode == AArch64::MOVKWi) && 203 MI->getOperand(2).isExpr()) { 204 O << "\tmovk\t" << getRegisterName(MI->getOperand(0).getReg()) << ", #" 205 << *MI->getOperand(2).getExpr(); 206 return; 207 } 208 209 if (!printAliasInstr(MI, STI, O)) 210 printInstruction(MI, STI, O); 211 212 printAnnotation(O, Annot); 213} 214 215static bool isTblTbxInstruction(unsigned Opcode, StringRef &Layout, 216 bool &IsTbx) { 217 switch (Opcode) { 218 case AArch64::TBXv8i8One: 219 case AArch64::TBXv8i8Two: 220 case AArch64::TBXv8i8Three: 221 case AArch64::TBXv8i8Four: 222 IsTbx = true; 223 Layout = ".8b"; 224 return true; 225 case AArch64::TBLv8i8One: 226 case AArch64::TBLv8i8Two: 227 case AArch64::TBLv8i8Three: 228 case AArch64::TBLv8i8Four: 229 IsTbx = false; 230 Layout = ".8b"; 231 return true; 232 case AArch64::TBXv16i8One: 233 case AArch64::TBXv16i8Two: 234 case AArch64::TBXv16i8Three: 235 case AArch64::TBXv16i8Four: 236 IsTbx = true; 237 Layout = ".16b"; 238 return true; 239 case AArch64::TBLv16i8One: 240 case AArch64::TBLv16i8Two: 241 case AArch64::TBLv16i8Three: 242 case AArch64::TBLv16i8Four: 243 IsTbx = false; 244 Layout = ".16b"; 245 return true; 246 default: 247 return false; 248 } 249} 250 251struct LdStNInstrDesc { 252 unsigned Opcode; 253 const char *Mnemonic; 254 const char *Layout; 255 int ListOperand; 256 bool HasLane; 257 int NaturalOffset; 258}; 259 260static LdStNInstrDesc LdStNInstInfo[] = { 261 { AArch64::LD1i8, "ld1", ".b", 1, true, 0 }, 262 { AArch64::LD1i16, "ld1", ".h", 1, true, 0 }, 263 { AArch64::LD1i32, "ld1", ".s", 1, true, 0 }, 264 { AArch64::LD1i64, "ld1", ".d", 1, true, 0 }, 265 { AArch64::LD1i8_POST, "ld1", ".b", 2, true, 1 }, 266 { AArch64::LD1i16_POST, "ld1", ".h", 2, true, 2 }, 267 { AArch64::LD1i32_POST, "ld1", ".s", 2, true, 4 }, 268 { AArch64::LD1i64_POST, "ld1", ".d", 2, true, 8 }, 269 { AArch64::LD1Rv16b, "ld1r", ".16b", 0, false, 0 }, 270 { AArch64::LD1Rv8h, "ld1r", ".8h", 0, false, 0 }, 271 { AArch64::LD1Rv4s, "ld1r", ".4s", 0, false, 0 }, 272 { AArch64::LD1Rv2d, "ld1r", ".2d", 0, false, 0 }, 273 { AArch64::LD1Rv8b, "ld1r", ".8b", 0, false, 0 }, 274 { AArch64::LD1Rv4h, "ld1r", ".4h", 0, false, 0 }, 275 { AArch64::LD1Rv2s, "ld1r", ".2s", 0, false, 0 }, 276 { AArch64::LD1Rv1d, "ld1r", ".1d", 0, false, 0 }, 277 { AArch64::LD1Rv16b_POST, "ld1r", ".16b", 1, false, 1 }, 278 { AArch64::LD1Rv8h_POST, "ld1r", ".8h", 1, false, 2 }, 279 { AArch64::LD1Rv4s_POST, "ld1r", ".4s", 1, false, 4 }, 280 { AArch64::LD1Rv2d_POST, "ld1r", ".2d", 1, false, 8 }, 281 { AArch64::LD1Rv8b_POST, "ld1r", ".8b", 1, false, 1 }, 282 { AArch64::LD1Rv4h_POST, "ld1r", ".4h", 1, false, 2 }, 283 { AArch64::LD1Rv2s_POST, "ld1r", ".2s", 1, false, 4 }, 284 { AArch64::LD1Rv1d_POST, "ld1r", ".1d", 1, false, 8 }, 285 { AArch64::LD1Onev16b, "ld1", ".16b", 0, false, 0 }, 286 { AArch64::LD1Onev8h, "ld1", ".8h", 0, false, 0 }, 287 { AArch64::LD1Onev4s, "ld1", ".4s", 0, false, 0 }, 288 { AArch64::LD1Onev2d, "ld1", ".2d", 0, false, 0 }, 289 { AArch64::LD1Onev8b, "ld1", ".8b", 0, false, 0 }, 290 { AArch64::LD1Onev4h, "ld1", ".4h", 0, false, 0 }, 291 { AArch64::LD1Onev2s, "ld1", ".2s", 0, false, 0 }, 292 { AArch64::LD1Onev1d, "ld1", ".1d", 0, false, 0 }, 293 { AArch64::LD1Onev16b_POST, "ld1", ".16b", 1, false, 16 }, 294 { AArch64::LD1Onev8h_POST, "ld1", ".8h", 1, false, 16 }, 295 { AArch64::LD1Onev4s_POST, "ld1", ".4s", 1, false, 16 }, 296 { AArch64::LD1Onev2d_POST, "ld1", ".2d", 1, false, 16 }, 297 { AArch64::LD1Onev8b_POST, "ld1", ".8b", 1, false, 8 }, 298 { AArch64::LD1Onev4h_POST, "ld1", ".4h", 1, false, 8 }, 299 { AArch64::LD1Onev2s_POST, "ld1", ".2s", 1, false, 8 }, 300 { AArch64::LD1Onev1d_POST, "ld1", ".1d", 1, false, 8 }, 301 { AArch64::LD1Twov16b, "ld1", ".16b", 0, false, 0 }, 302 { AArch64::LD1Twov8h, "ld1", ".8h", 0, false, 0 }, 303 { AArch64::LD1Twov4s, "ld1", ".4s", 0, false, 0 }, 304 { AArch64::LD1Twov2d, "ld1", ".2d", 0, false, 0 }, 305 { AArch64::LD1Twov8b, "ld1", ".8b", 0, false, 0 }, 306 { AArch64::LD1Twov4h, "ld1", ".4h", 0, false, 0 }, 307 { AArch64::LD1Twov2s, "ld1", ".2s", 0, false, 0 }, 308 { AArch64::LD1Twov1d, "ld1", ".1d", 0, false, 0 }, 309 { AArch64::LD1Twov16b_POST, "ld1", ".16b", 1, false, 32 }, 310 { AArch64::LD1Twov8h_POST, "ld1", ".8h", 1, false, 32 }, 311 { AArch64::LD1Twov4s_POST, "ld1", ".4s", 1, false, 32 }, 312 { AArch64::LD1Twov2d_POST, "ld1", ".2d", 1, false, 32 }, 313 { AArch64::LD1Twov8b_POST, "ld1", ".8b", 1, false, 16 }, 314 { AArch64::LD1Twov4h_POST, "ld1", ".4h", 1, false, 16 }, 315 { AArch64::LD1Twov2s_POST, "ld1", ".2s", 1, false, 16 }, 316 { AArch64::LD1Twov1d_POST, "ld1", ".1d", 1, false, 16 }, 317 { AArch64::LD1Threev16b, "ld1", ".16b", 0, false, 0 }, 318 { AArch64::LD1Threev8h, "ld1", ".8h", 0, false, 0 }, 319 { AArch64::LD1Threev4s, "ld1", ".4s", 0, false, 0 }, 320 { AArch64::LD1Threev2d, "ld1", ".2d", 0, false, 0 }, 321 { AArch64::LD1Threev8b, "ld1", ".8b", 0, false, 0 }, 322 { AArch64::LD1Threev4h, "ld1", ".4h", 0, false, 0 }, 323 { AArch64::LD1Threev2s, "ld1", ".2s", 0, false, 0 }, 324 { AArch64::LD1Threev1d, "ld1", ".1d", 0, false, 0 }, 325 { AArch64::LD1Threev16b_POST, "ld1", ".16b", 1, false, 48 }, 326 { AArch64::LD1Threev8h_POST, "ld1", ".8h", 1, false, 48 }, 327 { AArch64::LD1Threev4s_POST, "ld1", ".4s", 1, false, 48 }, 328 { AArch64::LD1Threev2d_POST, "ld1", ".2d", 1, false, 48 }, 329 { AArch64::LD1Threev8b_POST, "ld1", ".8b", 1, false, 24 }, 330 { AArch64::LD1Threev4h_POST, "ld1", ".4h", 1, false, 24 }, 331 { AArch64::LD1Threev2s_POST, "ld1", ".2s", 1, false, 24 }, 332 { AArch64::LD1Threev1d_POST, "ld1", ".1d", 1, false, 24 }, 333 { AArch64::LD1Fourv16b, "ld1", ".16b", 0, false, 0 }, 334 { AArch64::LD1Fourv8h, "ld1", ".8h", 0, false, 0 }, 335 { AArch64::LD1Fourv4s, "ld1", ".4s", 0, false, 0 }, 336 { AArch64::LD1Fourv2d, "ld1", ".2d", 0, false, 0 }, 337 { AArch64::LD1Fourv8b, "ld1", ".8b", 0, false, 0 }, 338 { AArch64::LD1Fourv4h, "ld1", ".4h", 0, false, 0 }, 339 { AArch64::LD1Fourv2s, "ld1", ".2s", 0, false, 0 }, 340 { AArch64::LD1Fourv1d, "ld1", ".1d", 0, false, 0 }, 341 { AArch64::LD1Fourv16b_POST, "ld1", ".16b", 1, false, 64 }, 342 { AArch64::LD1Fourv8h_POST, "ld1", ".8h", 1, false, 64 }, 343 { AArch64::LD1Fourv4s_POST, "ld1", ".4s", 1, false, 64 }, 344 { AArch64::LD1Fourv2d_POST, "ld1", ".2d", 1, false, 64 }, 345 { AArch64::LD1Fourv8b_POST, "ld1", ".8b", 1, false, 32 }, 346 { AArch64::LD1Fourv4h_POST, "ld1", ".4h", 1, false, 32 }, 347 { AArch64::LD1Fourv2s_POST, "ld1", ".2s", 1, false, 32 }, 348 { AArch64::LD1Fourv1d_POST, "ld1", ".1d", 1, false, 32 }, 349 { AArch64::LD2i8, "ld2", ".b", 1, true, 0 }, 350 { AArch64::LD2i16, "ld2", ".h", 1, true, 0 }, 351 { AArch64::LD2i32, "ld2", ".s", 1, true, 0 }, 352 { AArch64::LD2i64, "ld2", ".d", 1, true, 0 }, 353 { AArch64::LD2i8_POST, "ld2", ".b", 2, true, 2 }, 354 { AArch64::LD2i16_POST, "ld2", ".h", 2, true, 4 }, 355 { AArch64::LD2i32_POST, "ld2", ".s", 2, true, 8 }, 356 { AArch64::LD2i64_POST, "ld2", ".d", 2, true, 16 }, 357 { AArch64::LD2Rv16b, "ld2r", ".16b", 0, false, 0 }, 358 { AArch64::LD2Rv8h, "ld2r", ".8h", 0, false, 0 }, 359 { AArch64::LD2Rv4s, "ld2r", ".4s", 0, false, 0 }, 360 { AArch64::LD2Rv2d, "ld2r", ".2d", 0, false, 0 }, 361 { AArch64::LD2Rv8b, "ld2r", ".8b", 0, false, 0 }, 362 { AArch64::LD2Rv4h, "ld2r", ".4h", 0, false, 0 }, 363 { AArch64::LD2Rv2s, "ld2r", ".2s", 0, false, 0 }, 364 { AArch64::LD2Rv1d, "ld2r", ".1d", 0, false, 0 }, 365 { AArch64::LD2Rv16b_POST, "ld2r", ".16b", 1, false, 2 }, 366 { AArch64::LD2Rv8h_POST, "ld2r", ".8h", 1, false, 4 }, 367 { AArch64::LD2Rv4s_POST, "ld2r", ".4s", 1, false, 8 }, 368 { AArch64::LD2Rv2d_POST, "ld2r", ".2d", 1, false, 16 }, 369 { AArch64::LD2Rv8b_POST, "ld2r", ".8b", 1, false, 2 }, 370 { AArch64::LD2Rv4h_POST, "ld2r", ".4h", 1, false, 4 }, 371 { AArch64::LD2Rv2s_POST, "ld2r", ".2s", 1, false, 8 }, 372 { AArch64::LD2Rv1d_POST, "ld2r", ".1d", 1, false, 16 }, 373 { AArch64::LD2Twov16b, "ld2", ".16b", 0, false, 0 }, 374 { AArch64::LD2Twov8h, "ld2", ".8h", 0, false, 0 }, 375 { AArch64::LD2Twov4s, "ld2", ".4s", 0, false, 0 }, 376 { AArch64::LD2Twov2d, "ld2", ".2d", 0, false, 0 }, 377 { AArch64::LD2Twov8b, "ld2", ".8b", 0, false, 0 }, 378 { AArch64::LD2Twov4h, "ld2", ".4h", 0, false, 0 }, 379 { AArch64::LD2Twov2s, "ld2", ".2s", 0, false, 0 }, 380 { AArch64::LD2Twov16b_POST, "ld2", ".16b", 1, false, 32 }, 381 { AArch64::LD2Twov8h_POST, "ld2", ".8h", 1, false, 32 }, 382 { AArch64::LD2Twov4s_POST, "ld2", ".4s", 1, false, 32 }, 383 { AArch64::LD2Twov2d_POST, "ld2", ".2d", 1, false, 32 }, 384 { AArch64::LD2Twov8b_POST, "ld2", ".8b", 1, false, 16 }, 385 { AArch64::LD2Twov4h_POST, "ld2", ".4h", 1, false, 16 }, 386 { AArch64::LD2Twov2s_POST, "ld2", ".2s", 1, false, 16 }, 387 { AArch64::LD3i8, "ld3", ".b", 1, true, 0 }, 388 { AArch64::LD3i16, "ld3", ".h", 1, true, 0 }, 389 { AArch64::LD3i32, "ld3", ".s", 1, true, 0 }, 390 { AArch64::LD3i64, "ld3", ".d", 1, true, 0 }, 391 { AArch64::LD3i8_POST, "ld3", ".b", 2, true, 3 }, 392 { AArch64::LD3i16_POST, "ld3", ".h", 2, true, 6 }, 393 { AArch64::LD3i32_POST, "ld3", ".s", 2, true, 12 }, 394 { AArch64::LD3i64_POST, "ld3", ".d", 2, true, 24 }, 395 { AArch64::LD3Rv16b, "ld3r", ".16b", 0, false, 0 }, 396 { AArch64::LD3Rv8h, "ld3r", ".8h", 0, false, 0 }, 397 { AArch64::LD3Rv4s, "ld3r", ".4s", 0, false, 0 }, 398 { AArch64::LD3Rv2d, "ld3r", ".2d", 0, false, 0 }, 399 { AArch64::LD3Rv8b, "ld3r", ".8b", 0, false, 0 }, 400 { AArch64::LD3Rv4h, "ld3r", ".4h", 0, false, 0 }, 401 { AArch64::LD3Rv2s, "ld3r", ".2s", 0, false, 0 }, 402 { AArch64::LD3Rv1d, "ld3r", ".1d", 0, false, 0 }, 403 { AArch64::LD3Rv16b_POST, "ld3r", ".16b", 1, false, 3 }, 404 { AArch64::LD3Rv8h_POST, "ld3r", ".8h", 1, false, 6 }, 405 { AArch64::LD3Rv4s_POST, "ld3r", ".4s", 1, false, 12 }, 406 { AArch64::LD3Rv2d_POST, "ld3r", ".2d", 1, false, 24 }, 407 { AArch64::LD3Rv8b_POST, "ld3r", ".8b", 1, false, 3 }, 408 { AArch64::LD3Rv4h_POST, "ld3r", ".4h", 1, false, 6 }, 409 { AArch64::LD3Rv2s_POST, "ld3r", ".2s", 1, false, 12 }, 410 { AArch64::LD3Rv1d_POST, "ld3r", ".1d", 1, false, 24 }, 411 { AArch64::LD3Threev16b, "ld3", ".16b", 0, false, 0 }, 412 { AArch64::LD3Threev8h, "ld3", ".8h", 0, false, 0 }, 413 { AArch64::LD3Threev4s, "ld3", ".4s", 0, false, 0 }, 414 { AArch64::LD3Threev2d, "ld3", ".2d", 0, false, 0 }, 415 { AArch64::LD3Threev8b, "ld3", ".8b", 0, false, 0 }, 416 { AArch64::LD3Threev4h, "ld3", ".4h", 0, false, 0 }, 417 { AArch64::LD3Threev2s, "ld3", ".2s", 0, false, 0 }, 418 { AArch64::LD3Threev16b_POST, "ld3", ".16b", 1, false, 48 }, 419 { AArch64::LD3Threev8h_POST, "ld3", ".8h", 1, false, 48 }, 420 { AArch64::LD3Threev4s_POST, "ld3", ".4s", 1, false, 48 }, 421 { AArch64::LD3Threev2d_POST, "ld3", ".2d", 1, false, 48 }, 422 { AArch64::LD3Threev8b_POST, "ld3", ".8b", 1, false, 24 }, 423 { AArch64::LD3Threev4h_POST, "ld3", ".4h", 1, false, 24 }, 424 { AArch64::LD3Threev2s_POST, "ld3", ".2s", 1, false, 24 }, 425 { AArch64::LD4i8, "ld4", ".b", 1, true, 0 }, 426 { AArch64::LD4i16, "ld4", ".h", 1, true, 0 }, 427 { AArch64::LD4i32, "ld4", ".s", 1, true, 0 }, 428 { AArch64::LD4i64, "ld4", ".d", 1, true, 0 }, 429 { AArch64::LD4i8_POST, "ld4", ".b", 2, true, 4 }, 430 { AArch64::LD4i16_POST, "ld4", ".h", 2, true, 8 }, 431 { AArch64::LD4i32_POST, "ld4", ".s", 2, true, 16 }, 432 { AArch64::LD4i64_POST, "ld4", ".d", 2, true, 32 }, 433 { AArch64::LD4Rv16b, "ld4r", ".16b", 0, false, 0 }, 434 { AArch64::LD4Rv8h, "ld4r", ".8h", 0, false, 0 }, 435 { AArch64::LD4Rv4s, "ld4r", ".4s", 0, false, 0 }, 436 { AArch64::LD4Rv2d, "ld4r", ".2d", 0, false, 0 }, 437 { AArch64::LD4Rv8b, "ld4r", ".8b", 0, false, 0 }, 438 { AArch64::LD4Rv4h, "ld4r", ".4h", 0, false, 0 }, 439 { AArch64::LD4Rv2s, "ld4r", ".2s", 0, false, 0 }, 440 { AArch64::LD4Rv1d, "ld4r", ".1d", 0, false, 0 }, 441 { AArch64::LD4Rv16b_POST, "ld4r", ".16b", 1, false, 4 }, 442 { AArch64::LD4Rv8h_POST, "ld4r", ".8h", 1, false, 8 }, 443 { AArch64::LD4Rv4s_POST, "ld4r", ".4s", 1, false, 16 }, 444 { AArch64::LD4Rv2d_POST, "ld4r", ".2d", 1, false, 32 }, 445 { AArch64::LD4Rv8b_POST, "ld4r", ".8b", 1, false, 4 }, 446 { AArch64::LD4Rv4h_POST, "ld4r", ".4h", 1, false, 8 }, 447 { AArch64::LD4Rv2s_POST, "ld4r", ".2s", 1, false, 16 }, 448 { AArch64::LD4Rv1d_POST, "ld4r", ".1d", 1, false, 32 }, 449 { AArch64::LD4Fourv16b, "ld4", ".16b", 0, false, 0 }, 450 { AArch64::LD4Fourv8h, "ld4", ".8h", 0, false, 0 }, 451 { AArch64::LD4Fourv4s, "ld4", ".4s", 0, false, 0 }, 452 { AArch64::LD4Fourv2d, "ld4", ".2d", 0, false, 0 }, 453 { AArch64::LD4Fourv8b, "ld4", ".8b", 0, false, 0 }, 454 { AArch64::LD4Fourv4h, "ld4", ".4h", 0, false, 0 }, 455 { AArch64::LD4Fourv2s, "ld4", ".2s", 0, false, 0 }, 456 { AArch64::LD4Fourv16b_POST, "ld4", ".16b", 1, false, 64 }, 457 { AArch64::LD4Fourv8h_POST, "ld4", ".8h", 1, false, 64 }, 458 { AArch64::LD4Fourv4s_POST, "ld4", ".4s", 1, false, 64 }, 459 { AArch64::LD4Fourv2d_POST, "ld4", ".2d", 1, false, 64 }, 460 { AArch64::LD4Fourv8b_POST, "ld4", ".8b", 1, false, 32 }, 461 { AArch64::LD4Fourv4h_POST, "ld4", ".4h", 1, false, 32 }, 462 { AArch64::LD4Fourv2s_POST, "ld4", ".2s", 1, false, 32 }, 463 { AArch64::ST1i8, "st1", ".b", 0, true, 0 }, 464 { AArch64::ST1i16, "st1", ".h", 0, true, 0 }, 465 { AArch64::ST1i32, "st1", ".s", 0, true, 0 }, 466 { AArch64::ST1i64, "st1", ".d", 0, true, 0 }, 467 { AArch64::ST1i8_POST, "st1", ".b", 1, true, 1 }, 468 { AArch64::ST1i16_POST, "st1", ".h", 1, true, 2 }, 469 { AArch64::ST1i32_POST, "st1", ".s", 1, true, 4 }, 470 { AArch64::ST1i64_POST, "st1", ".d", 1, true, 8 }, 471 { AArch64::ST1Onev16b, "st1", ".16b", 0, false, 0 }, 472 { AArch64::ST1Onev8h, "st1", ".8h", 0, false, 0 }, 473 { AArch64::ST1Onev4s, "st1", ".4s", 0, false, 0 }, 474 { AArch64::ST1Onev2d, "st1", ".2d", 0, false, 0 }, 475 { AArch64::ST1Onev8b, "st1", ".8b", 0, false, 0 }, 476 { AArch64::ST1Onev4h, "st1", ".4h", 0, false, 0 }, 477 { AArch64::ST1Onev2s, "st1", ".2s", 0, false, 0 }, 478 { AArch64::ST1Onev1d, "st1", ".1d", 0, false, 0 }, 479 { AArch64::ST1Onev16b_POST, "st1", ".16b", 1, false, 16 }, 480 { AArch64::ST1Onev8h_POST, "st1", ".8h", 1, false, 16 }, 481 { AArch64::ST1Onev4s_POST, "st1", ".4s", 1, false, 16 }, 482 { AArch64::ST1Onev2d_POST, "st1", ".2d", 1, false, 16 }, 483 { AArch64::ST1Onev8b_POST, "st1", ".8b", 1, false, 8 }, 484 { AArch64::ST1Onev4h_POST, "st1", ".4h", 1, false, 8 }, 485 { AArch64::ST1Onev2s_POST, "st1", ".2s", 1, false, 8 }, 486 { AArch64::ST1Onev1d_POST, "st1", ".1d", 1, false, 8 }, 487 { AArch64::ST1Twov16b, "st1", ".16b", 0, false, 0 }, 488 { AArch64::ST1Twov8h, "st1", ".8h", 0, false, 0 }, 489 { AArch64::ST1Twov4s, "st1", ".4s", 0, false, 0 }, 490 { AArch64::ST1Twov2d, "st1", ".2d", 0, false, 0 }, 491 { AArch64::ST1Twov8b, "st1", ".8b", 0, false, 0 }, 492 { AArch64::ST1Twov4h, "st1", ".4h", 0, false, 0 }, 493 { AArch64::ST1Twov2s, "st1", ".2s", 0, false, 0 }, 494 { AArch64::ST1Twov1d, "st1", ".1d", 0, false, 0 }, 495 { AArch64::ST1Twov16b_POST, "st1", ".16b", 1, false, 32 }, 496 { AArch64::ST1Twov8h_POST, "st1", ".8h", 1, false, 32 }, 497 { AArch64::ST1Twov4s_POST, "st1", ".4s", 1, false, 32 }, 498 { AArch64::ST1Twov2d_POST, "st1", ".2d", 1, false, 32 }, 499 { AArch64::ST1Twov8b_POST, "st1", ".8b", 1, false, 16 }, 500 { AArch64::ST1Twov4h_POST, "st1", ".4h", 1, false, 16 }, 501 { AArch64::ST1Twov2s_POST, "st1", ".2s", 1, false, 16 }, 502 { AArch64::ST1Twov1d_POST, "st1", ".1d", 1, false, 16 }, 503 { AArch64::ST1Threev16b, "st1", ".16b", 0, false, 0 }, 504 { AArch64::ST1Threev8h, "st1", ".8h", 0, false, 0 }, 505 { AArch64::ST1Threev4s, "st1", ".4s", 0, false, 0 }, 506 { AArch64::ST1Threev2d, "st1", ".2d", 0, false, 0 }, 507 { AArch64::ST1Threev8b, "st1", ".8b", 0, false, 0 }, 508 { AArch64::ST1Threev4h, "st1", ".4h", 0, false, 0 }, 509 { AArch64::ST1Threev2s, "st1", ".2s", 0, false, 0 }, 510 { AArch64::ST1Threev1d, "st1", ".1d", 0, false, 0 }, 511 { AArch64::ST1Threev16b_POST, "st1", ".16b", 1, false, 48 }, 512 { AArch64::ST1Threev8h_POST, "st1", ".8h", 1, false, 48 }, 513 { AArch64::ST1Threev4s_POST, "st1", ".4s", 1, false, 48 }, 514 { AArch64::ST1Threev2d_POST, "st1", ".2d", 1, false, 48 }, 515 { AArch64::ST1Threev8b_POST, "st1", ".8b", 1, false, 24 }, 516 { AArch64::ST1Threev4h_POST, "st1", ".4h", 1, false, 24 }, 517 { AArch64::ST1Threev2s_POST, "st1", ".2s", 1, false, 24 }, 518 { AArch64::ST1Threev1d_POST, "st1", ".1d", 1, false, 24 }, 519 { AArch64::ST1Fourv16b, "st1", ".16b", 0, false, 0 }, 520 { AArch64::ST1Fourv8h, "st1", ".8h", 0, false, 0 }, 521 { AArch64::ST1Fourv4s, "st1", ".4s", 0, false, 0 }, 522 { AArch64::ST1Fourv2d, "st1", ".2d", 0, false, 0 }, 523 { AArch64::ST1Fourv8b, "st1", ".8b", 0, false, 0 }, 524 { AArch64::ST1Fourv4h, "st1", ".4h", 0, false, 0 }, 525 { AArch64::ST1Fourv2s, "st1", ".2s", 0, false, 0 }, 526 { AArch64::ST1Fourv1d, "st1", ".1d", 0, false, 0 }, 527 { AArch64::ST1Fourv16b_POST, "st1", ".16b", 1, false, 64 }, 528 { AArch64::ST1Fourv8h_POST, "st1", ".8h", 1, false, 64 }, 529 { AArch64::ST1Fourv4s_POST, "st1", ".4s", 1, false, 64 }, 530 { AArch64::ST1Fourv2d_POST, "st1", ".2d", 1, false, 64 }, 531 { AArch64::ST1Fourv8b_POST, "st1", ".8b", 1, false, 32 }, 532 { AArch64::ST1Fourv4h_POST, "st1", ".4h", 1, false, 32 }, 533 { AArch64::ST1Fourv2s_POST, "st1", ".2s", 1, false, 32 }, 534 { AArch64::ST1Fourv1d_POST, "st1", ".1d", 1, false, 32 }, 535 { AArch64::ST2i8, "st2", ".b", 0, true, 0 }, 536 { AArch64::ST2i16, "st2", ".h", 0, true, 0 }, 537 { AArch64::ST2i32, "st2", ".s", 0, true, 0 }, 538 { AArch64::ST2i64, "st2", ".d", 0, true, 0 }, 539 { AArch64::ST2i8_POST, "st2", ".b", 1, true, 2 }, 540 { AArch64::ST2i16_POST, "st2", ".h", 1, true, 4 }, 541 { AArch64::ST2i32_POST, "st2", ".s", 1, true, 8 }, 542 { AArch64::ST2i64_POST, "st2", ".d", 1, true, 16 }, 543 { AArch64::ST2Twov16b, "st2", ".16b", 0, false, 0 }, 544 { AArch64::ST2Twov8h, "st2", ".8h", 0, false, 0 }, 545 { AArch64::ST2Twov4s, "st2", ".4s", 0, false, 0 }, 546 { AArch64::ST2Twov2d, "st2", ".2d", 0, false, 0 }, 547 { AArch64::ST2Twov8b, "st2", ".8b", 0, false, 0 }, 548 { AArch64::ST2Twov4h, "st2", ".4h", 0, false, 0 }, 549 { AArch64::ST2Twov2s, "st2", ".2s", 0, false, 0 }, 550 { AArch64::ST2Twov16b_POST, "st2", ".16b", 1, false, 32 }, 551 { AArch64::ST2Twov8h_POST, "st2", ".8h", 1, false, 32 }, 552 { AArch64::ST2Twov4s_POST, "st2", ".4s", 1, false, 32 }, 553 { AArch64::ST2Twov2d_POST, "st2", ".2d", 1, false, 32 }, 554 { AArch64::ST2Twov8b_POST, "st2", ".8b", 1, false, 16 }, 555 { AArch64::ST2Twov4h_POST, "st2", ".4h", 1, false, 16 }, 556 { AArch64::ST2Twov2s_POST, "st2", ".2s", 1, false, 16 }, 557 { AArch64::ST3i8, "st3", ".b", 0, true, 0 }, 558 { AArch64::ST3i16, "st3", ".h", 0, true, 0 }, 559 { AArch64::ST3i32, "st3", ".s", 0, true, 0 }, 560 { AArch64::ST3i64, "st3", ".d", 0, true, 0 }, 561 { AArch64::ST3i8_POST, "st3", ".b", 1, true, 3 }, 562 { AArch64::ST3i16_POST, "st3", ".h", 1, true, 6 }, 563 { AArch64::ST3i32_POST, "st3", ".s", 1, true, 12 }, 564 { AArch64::ST3i64_POST, "st3", ".d", 1, true, 24 }, 565 { AArch64::ST3Threev16b, "st3", ".16b", 0, false, 0 }, 566 { AArch64::ST3Threev8h, "st3", ".8h", 0, false, 0 }, 567 { AArch64::ST3Threev4s, "st3", ".4s", 0, false, 0 }, 568 { AArch64::ST3Threev2d, "st3", ".2d", 0, false, 0 }, 569 { AArch64::ST3Threev8b, "st3", ".8b", 0, false, 0 }, 570 { AArch64::ST3Threev4h, "st3", ".4h", 0, false, 0 }, 571 { AArch64::ST3Threev2s, "st3", ".2s", 0, false, 0 }, 572 { AArch64::ST3Threev16b_POST, "st3", ".16b", 1, false, 48 }, 573 { AArch64::ST3Threev8h_POST, "st3", ".8h", 1, false, 48 }, 574 { AArch64::ST3Threev4s_POST, "st3", ".4s", 1, false, 48 }, 575 { AArch64::ST3Threev2d_POST, "st3", ".2d", 1, false, 48 }, 576 { AArch64::ST3Threev8b_POST, "st3", ".8b", 1, false, 24 }, 577 { AArch64::ST3Threev4h_POST, "st3", ".4h", 1, false, 24 }, 578 { AArch64::ST3Threev2s_POST, "st3", ".2s", 1, false, 24 }, 579 { AArch64::ST4i8, "st4", ".b", 0, true, 0 }, 580 { AArch64::ST4i16, "st4", ".h", 0, true, 0 }, 581 { AArch64::ST4i32, "st4", ".s", 0, true, 0 }, 582 { AArch64::ST4i64, "st4", ".d", 0, true, 0 }, 583 { AArch64::ST4i8_POST, "st4", ".b", 1, true, 4 }, 584 { AArch64::ST4i16_POST, "st4", ".h", 1, true, 8 }, 585 { AArch64::ST4i32_POST, "st4", ".s", 1, true, 16 }, 586 { AArch64::ST4i64_POST, "st4", ".d", 1, true, 32 }, 587 { AArch64::ST4Fourv16b, "st4", ".16b", 0, false, 0 }, 588 { AArch64::ST4Fourv8h, "st4", ".8h", 0, false, 0 }, 589 { AArch64::ST4Fourv4s, "st4", ".4s", 0, false, 0 }, 590 { AArch64::ST4Fourv2d, "st4", ".2d", 0, false, 0 }, 591 { AArch64::ST4Fourv8b, "st4", ".8b", 0, false, 0 }, 592 { AArch64::ST4Fourv4h, "st4", ".4h", 0, false, 0 }, 593 { AArch64::ST4Fourv2s, "st4", ".2s", 0, false, 0 }, 594 { AArch64::ST4Fourv16b_POST, "st4", ".16b", 1, false, 64 }, 595 { AArch64::ST4Fourv8h_POST, "st4", ".8h", 1, false, 64 }, 596 { AArch64::ST4Fourv4s_POST, "st4", ".4s", 1, false, 64 }, 597 { AArch64::ST4Fourv2d_POST, "st4", ".2d", 1, false, 64 }, 598 { AArch64::ST4Fourv8b_POST, "st4", ".8b", 1, false, 32 }, 599 { AArch64::ST4Fourv4h_POST, "st4", ".4h", 1, false, 32 }, 600 { AArch64::ST4Fourv2s_POST, "st4", ".2s", 1, false, 32 }, 601}; 602 603static LdStNInstrDesc *getLdStNInstrDesc(unsigned Opcode) { 604 unsigned Idx; 605 for (Idx = 0; Idx != array_lengthof(LdStNInstInfo); ++Idx) 606 if (LdStNInstInfo[Idx].Opcode == Opcode) 607 return &LdStNInstInfo[Idx]; 608 609 return nullptr; 610} 611 612void AArch64AppleInstPrinter::printInst(const MCInst *MI, raw_ostream &O, 613 StringRef Annot, 614 const MCSubtargetInfo &STI) { 615 unsigned Opcode = MI->getOpcode(); 616 StringRef Layout, Mnemonic; 617 618 bool IsTbx; 619 if (isTblTbxInstruction(MI->getOpcode(), Layout, IsTbx)) { 620 O << "\t" << (IsTbx ? "tbx" : "tbl") << Layout << '\t' 621 << getRegisterName(MI->getOperand(0).getReg(), AArch64::vreg) << ", "; 622 623 unsigned ListOpNum = IsTbx ? 2 : 1; 624 printVectorList(MI, ListOpNum, STI, O, ""); 625 626 O << ", " 627 << getRegisterName(MI->getOperand(ListOpNum + 1).getReg(), AArch64::vreg); 628 printAnnotation(O, Annot); 629 return; 630 } 631 632 if (LdStNInstrDesc *LdStDesc = getLdStNInstrDesc(Opcode)) { 633 O << "\t" << LdStDesc->Mnemonic << LdStDesc->Layout << '\t'; 634 635 // Now onto the operands: first a vector list with possible lane 636 // specifier. E.g. { v0 }[2] 637 int OpNum = LdStDesc->ListOperand; 638 printVectorList(MI, OpNum++, STI, O, ""); 639 640 if (LdStDesc->HasLane) 641 O << '[' << MI->getOperand(OpNum++).getImm() << ']'; 642 643 // Next the address: [xN] 644 unsigned AddrReg = MI->getOperand(OpNum++).getReg(); 645 O << ", [" << getRegisterName(AddrReg) << ']'; 646 647 // Finally, there might be a post-indexed offset. 648 if (LdStDesc->NaturalOffset != 0) { 649 unsigned Reg = MI->getOperand(OpNum++).getReg(); 650 if (Reg != AArch64::XZR) 651 O << ", " << getRegisterName(Reg); 652 else { 653 assert(LdStDesc->NaturalOffset && "no offset on post-inc instruction?"); 654 O << ", #" << LdStDesc->NaturalOffset; 655 } 656 } 657 658 printAnnotation(O, Annot); 659 return; 660 } 661 662 AArch64InstPrinter::printInst(MI, O, Annot, STI); 663} 664 665bool AArch64InstPrinter::printSysAlias(const MCInst *MI, raw_ostream &O) { 666#ifndef NDEBUG 667 unsigned Opcode = MI->getOpcode(); 668 assert(Opcode == AArch64::SYSxt && "Invalid opcode for SYS alias!"); 669#endif 670 671 const char *Asm = nullptr; 672 const MCOperand &Op1 = MI->getOperand(0); 673 const MCOperand &Cn = MI->getOperand(1); 674 const MCOperand &Cm = MI->getOperand(2); 675 const MCOperand &Op2 = MI->getOperand(3); 676 677 unsigned Op1Val = Op1.getImm(); 678 unsigned CnVal = Cn.getImm(); 679 unsigned CmVal = Cm.getImm(); 680 unsigned Op2Val = Op2.getImm(); 681 682 if (CnVal == 7) { 683 switch (CmVal) { 684 default: 685 break; 686 687 // IC aliases 688 case 1: 689 if (Op1Val == 0 && Op2Val == 0) 690 Asm = "ic\tialluis"; 691 break; 692 case 5: 693 if (Op1Val == 0 && Op2Val == 0) 694 Asm = "ic\tiallu"; 695 else if (Op1Val == 3 && Op2Val == 1) 696 Asm = "ic\tivau"; 697 break; 698 699 // DC aliases 700 case 4: 701 if (Op1Val == 3 && Op2Val == 1) 702 Asm = "dc\tzva"; 703 break; 704 case 6: 705 if (Op1Val == 0 && Op2Val == 1) 706 Asm = "dc\tivac"; 707 if (Op1Val == 0 && Op2Val == 2) 708 Asm = "dc\tisw"; 709 break; 710 case 10: 711 if (Op1Val == 3 && Op2Val == 1) 712 Asm = "dc\tcvac"; 713 else if (Op1Val == 0 && Op2Val == 2) 714 Asm = "dc\tcsw"; 715 break; 716 case 11: 717 if (Op1Val == 3 && Op2Val == 1) 718 Asm = "dc\tcvau"; 719 break; 720 case 14: 721 if (Op1Val == 3 && Op2Val == 1) 722 Asm = "dc\tcivac"; 723 else if (Op1Val == 0 && Op2Val == 2) 724 Asm = "dc\tcisw"; 725 break; 726 727 // AT aliases 728 case 8: 729 switch (Op1Val) { 730 default: 731 break; 732 case 0: 733 switch (Op2Val) { 734 default: 735 break; 736 case 0: Asm = "at\ts1e1r"; break; 737 case 1: Asm = "at\ts1e1w"; break; 738 case 2: Asm = "at\ts1e0r"; break; 739 case 3: Asm = "at\ts1e0w"; break; 740 } 741 break; 742 case 4: 743 switch (Op2Val) { 744 default: 745 break; 746 case 0: Asm = "at\ts1e2r"; break; 747 case 1: Asm = "at\ts1e2w"; break; 748 case 4: Asm = "at\ts12e1r"; break; 749 case 5: Asm = "at\ts12e1w"; break; 750 case 6: Asm = "at\ts12e0r"; break; 751 case 7: Asm = "at\ts12e0w"; break; 752 } 753 break; 754 case 6: 755 switch (Op2Val) { 756 default: 757 break; 758 case 0: Asm = "at\ts1e3r"; break; 759 case 1: Asm = "at\ts1e3w"; break; 760 } 761 break; 762 } 763 break; 764 } 765 } else if (CnVal == 8) { 766 // TLBI aliases 767 switch (CmVal) { 768 default: 769 break; 770 case 3: 771 switch (Op1Val) { 772 default: 773 break; 774 case 0: 775 switch (Op2Val) { 776 default: 777 break; 778 case 0: Asm = "tlbi\tvmalle1is"; break; 779 case 1: Asm = "tlbi\tvae1is"; break; 780 case 2: Asm = "tlbi\taside1is"; break; 781 case 3: Asm = "tlbi\tvaae1is"; break; 782 case 5: Asm = "tlbi\tvale1is"; break; 783 case 7: Asm = "tlbi\tvaale1is"; break; 784 } 785 break; 786 case 4: 787 switch (Op2Val) { 788 default: 789 break; 790 case 0: Asm = "tlbi\talle2is"; break; 791 case 1: Asm = "tlbi\tvae2is"; break; 792 case 4: Asm = "tlbi\talle1is"; break; 793 case 5: Asm = "tlbi\tvale2is"; break; 794 case 6: Asm = "tlbi\tvmalls12e1is"; break; 795 } 796 break; 797 case 6: 798 switch (Op2Val) { 799 default: 800 break; 801 case 0: Asm = "tlbi\talle3is"; break; 802 case 1: Asm = "tlbi\tvae3is"; break; 803 case 5: Asm = "tlbi\tvale3is"; break; 804 } 805 break; 806 } 807 break; 808 case 0: 809 switch (Op1Val) { 810 default: 811 break; 812 case 4: 813 switch (Op2Val) { 814 default: 815 break; 816 case 1: Asm = "tlbi\tipas2e1is"; break; 817 case 5: Asm = "tlbi\tipas2le1is"; break; 818 } 819 break; 820 } 821 break; 822 case 4: 823 switch (Op1Val) { 824 default: 825 break; 826 case 4: 827 switch (Op2Val) { 828 default: 829 break; 830 case 1: Asm = "tlbi\tipas2e1"; break; 831 case 5: Asm = "tlbi\tipas2le1"; break; 832 } 833 break; 834 } 835 break; 836 case 7: 837 switch (Op1Val) { 838 default: 839 break; 840 case 0: 841 switch (Op2Val) { 842 default: 843 break; 844 case 0: Asm = "tlbi\tvmalle1"; break; 845 case 1: Asm = "tlbi\tvae1"; break; 846 case 2: Asm = "tlbi\taside1"; break; 847 case 3: Asm = "tlbi\tvaae1"; break; 848 case 5: Asm = "tlbi\tvale1"; break; 849 case 7: Asm = "tlbi\tvaale1"; break; 850 } 851 break; 852 case 4: 853 switch (Op2Val) { 854 default: 855 break; 856 case 0: Asm = "tlbi\talle2"; break; 857 case 1: Asm = "tlbi\tvae2"; break; 858 case 4: Asm = "tlbi\talle1"; break; 859 case 5: Asm = "tlbi\tvale2"; break; 860 case 6: Asm = "tlbi\tvmalls12e1"; break; 861 } 862 break; 863 case 6: 864 switch (Op2Val) { 865 default: 866 break; 867 case 0: Asm = "tlbi\talle3"; break; 868 case 1: Asm = "tlbi\tvae3"; break; 869 case 5: Asm = "tlbi\tvale3"; break; 870 } 871 break; 872 } 873 break; 874 } 875 } 876 877 if (Asm) { 878 unsigned Reg = MI->getOperand(4).getReg(); 879 880 O << '\t' << Asm; 881 if (StringRef(Asm).lower().find("all") == StringRef::npos) 882 O << ", " << getRegisterName(Reg); 883 } 884 885 return Asm != nullptr; 886} 887 888void AArch64InstPrinter::printOperand(const MCInst *MI, unsigned OpNo, 889 const MCSubtargetInfo &STI, 890 raw_ostream &O) { 891 const MCOperand &Op = MI->getOperand(OpNo); 892 if (Op.isReg()) { 893 unsigned Reg = Op.getReg(); 894 O << getRegisterName(Reg); 895 } else if (Op.isImm()) { 896 O << '#' << Op.getImm(); 897 } else { 898 assert(Op.isExpr() && "unknown operand kind in printOperand"); 899 O << *Op.getExpr(); 900 } 901} 902 903void AArch64InstPrinter::printHexImm(const MCInst *MI, unsigned OpNo, 904 const MCSubtargetInfo &STI, 905 raw_ostream &O) { 906 const MCOperand &Op = MI->getOperand(OpNo); 907 O << format("#%#llx", Op.getImm()); 908} 909 910void AArch64InstPrinter::printPostIncOperand(const MCInst *MI, unsigned OpNo, 911 unsigned Imm, raw_ostream &O) { 912 const MCOperand &Op = MI->getOperand(OpNo); 913 if (Op.isReg()) { 914 unsigned Reg = Op.getReg(); 915 if (Reg == AArch64::XZR) 916 O << "#" << Imm; 917 else 918 O << getRegisterName(Reg); 919 } else 920 llvm_unreachable("unknown operand kind in printPostIncOperand64"); 921} 922 923void AArch64InstPrinter::printVRegOperand(const MCInst *MI, unsigned OpNo, 924 const MCSubtargetInfo &STI, 925 raw_ostream &O) { 926 const MCOperand &Op = MI->getOperand(OpNo); 927 assert(Op.isReg() && "Non-register vreg operand!"); 928 unsigned Reg = Op.getReg(); 929 O << getRegisterName(Reg, AArch64::vreg); 930} 931 932void AArch64InstPrinter::printSysCROperand(const MCInst *MI, unsigned OpNo, 933 const MCSubtargetInfo &STI, 934 raw_ostream &O) { 935 const MCOperand &Op = MI->getOperand(OpNo); 936 assert(Op.isImm() && "System instruction C[nm] operands must be immediates!"); 937 O << "c" << Op.getImm(); 938} 939 940void AArch64InstPrinter::printAddSubImm(const MCInst *MI, unsigned OpNum, 941 const MCSubtargetInfo &STI, 942 raw_ostream &O) { 943 const MCOperand &MO = MI->getOperand(OpNum); 944 if (MO.isImm()) { 945 unsigned Val = (MO.getImm() & 0xfff); 946 assert(Val == MO.getImm() && "Add/sub immediate out of range!"); 947 unsigned Shift = 948 AArch64_AM::getShiftValue(MI->getOperand(OpNum + 1).getImm()); 949 O << '#' << Val; 950 if (Shift != 0) 951 printShifter(MI, OpNum + 1, STI, O); 952 953 if (CommentStream) 954 *CommentStream << '=' << (Val << Shift) << '\n'; 955 } else { 956 assert(MO.isExpr() && "Unexpected operand type!"); 957 O << *MO.getExpr(); 958 printShifter(MI, OpNum + 1, STI, O); 959 } 960} 961 962void AArch64InstPrinter::printLogicalImm32(const MCInst *MI, unsigned OpNum, 963 const MCSubtargetInfo &STI, 964 raw_ostream &O) { 965 uint64_t Val = MI->getOperand(OpNum).getImm(); 966 O << "#0x"; 967 O.write_hex(AArch64_AM::decodeLogicalImmediate(Val, 32)); 968} 969 970void AArch64InstPrinter::printLogicalImm64(const MCInst *MI, unsigned OpNum, 971 const MCSubtargetInfo &STI, 972 raw_ostream &O) { 973 uint64_t Val = MI->getOperand(OpNum).getImm(); 974 O << "#0x"; 975 O.write_hex(AArch64_AM::decodeLogicalImmediate(Val, 64)); 976} 977 978void AArch64InstPrinter::printShifter(const MCInst *MI, unsigned OpNum, 979 const MCSubtargetInfo &STI, 980 raw_ostream &O) { 981 unsigned Val = MI->getOperand(OpNum).getImm(); 982 // LSL #0 should not be printed. 983 if (AArch64_AM::getShiftType(Val) == AArch64_AM::LSL && 984 AArch64_AM::getShiftValue(Val) == 0) 985 return; 986 O << ", " << AArch64_AM::getShiftExtendName(AArch64_AM::getShiftType(Val)) 987 << " #" << AArch64_AM::getShiftValue(Val); 988} 989 990void AArch64InstPrinter::printShiftedRegister(const MCInst *MI, unsigned OpNum, 991 const MCSubtargetInfo &STI, 992 raw_ostream &O) { 993 O << getRegisterName(MI->getOperand(OpNum).getReg()); 994 printShifter(MI, OpNum + 1, STI, O); 995} 996 997void AArch64InstPrinter::printExtendedRegister(const MCInst *MI, unsigned OpNum, 998 const MCSubtargetInfo &STI, 999 raw_ostream &O) { 1000 O << getRegisterName(MI->getOperand(OpNum).getReg()); 1001 printArithExtend(MI, OpNum + 1, STI, O); 1002} 1003 1004void AArch64InstPrinter::printArithExtend(const MCInst *MI, unsigned OpNum, 1005 const MCSubtargetInfo &STI, 1006 raw_ostream &O) { 1007 unsigned Val = MI->getOperand(OpNum).getImm(); 1008 AArch64_AM::ShiftExtendType ExtType = AArch64_AM::getArithExtendType(Val); 1009 unsigned ShiftVal = AArch64_AM::getArithShiftValue(Val); 1010 1011 // If the destination or first source register operand is [W]SP, print 1012 // UXTW/UXTX as LSL, and if the shift amount is also zero, print nothing at 1013 // all. 1014 if (ExtType == AArch64_AM::UXTW || ExtType == AArch64_AM::UXTX) { 1015 unsigned Dest = MI->getOperand(0).getReg(); 1016 unsigned Src1 = MI->getOperand(1).getReg(); 1017 if ( ((Dest == AArch64::SP || Src1 == AArch64::SP) && 1018 ExtType == AArch64_AM::UXTX) || 1019 ((Dest == AArch64::WSP || Src1 == AArch64::WSP) && 1020 ExtType == AArch64_AM::UXTW) ) { 1021 if (ShiftVal != 0) 1022 O << ", lsl #" << ShiftVal; 1023 return; 1024 } 1025 } 1026 O << ", " << AArch64_AM::getShiftExtendName(ExtType); 1027 if (ShiftVal != 0) 1028 O << " #" << ShiftVal; 1029} 1030 1031void AArch64InstPrinter::printMemExtend(const MCInst *MI, unsigned OpNum, 1032 raw_ostream &O, char SrcRegKind, 1033 unsigned Width) { 1034 unsigned SignExtend = MI->getOperand(OpNum).getImm(); 1035 unsigned DoShift = MI->getOperand(OpNum + 1).getImm(); 1036 1037 // sxtw, sxtx, uxtw or lsl (== uxtx) 1038 bool IsLSL = !SignExtend && SrcRegKind == 'x'; 1039 if (IsLSL) 1040 O << "lsl"; 1041 else 1042 O << (SignExtend ? 's' : 'u') << "xt" << SrcRegKind; 1043 1044 if (DoShift || IsLSL) 1045 O << " #" << Log2_32(Width / 8); 1046} 1047 1048void AArch64InstPrinter::printCondCode(const MCInst *MI, unsigned OpNum, 1049 const MCSubtargetInfo &STI, 1050 raw_ostream &O) { 1051 AArch64CC::CondCode CC = (AArch64CC::CondCode)MI->getOperand(OpNum).getImm(); 1052 O << AArch64CC::getCondCodeName(CC); 1053} 1054 1055void AArch64InstPrinter::printInverseCondCode(const MCInst *MI, unsigned OpNum, 1056 const MCSubtargetInfo &STI, 1057 raw_ostream &O) { 1058 AArch64CC::CondCode CC = (AArch64CC::CondCode)MI->getOperand(OpNum).getImm(); 1059 O << AArch64CC::getCondCodeName(AArch64CC::getInvertedCondCode(CC)); 1060} 1061 1062void AArch64InstPrinter::printAMNoIndex(const MCInst *MI, unsigned OpNum, 1063 const MCSubtargetInfo &STI, 1064 raw_ostream &O) { 1065 O << '[' << getRegisterName(MI->getOperand(OpNum).getReg()) << ']'; 1066} 1067 1068template<int Scale> 1069void AArch64InstPrinter::printImmScale(const MCInst *MI, unsigned OpNum, 1070 const MCSubtargetInfo &STI, 1071 raw_ostream &O) { 1072 O << '#' << Scale * MI->getOperand(OpNum).getImm(); 1073} 1074 1075void AArch64InstPrinter::printUImm12Offset(const MCInst *MI, unsigned OpNum, 1076 unsigned Scale, raw_ostream &O) { 1077 const MCOperand MO = MI->getOperand(OpNum); 1078 if (MO.isImm()) { 1079 O << "#" << (MO.getImm() * Scale); 1080 } else { 1081 assert(MO.isExpr() && "Unexpected operand type!"); 1082 O << *MO.getExpr(); 1083 } 1084} 1085 1086void AArch64InstPrinter::printAMIndexedWB(const MCInst *MI, unsigned OpNum, 1087 unsigned Scale, raw_ostream &O) { 1088 const MCOperand MO1 = MI->getOperand(OpNum + 1); 1089 O << '[' << getRegisterName(MI->getOperand(OpNum).getReg()); 1090 if (MO1.isImm()) { 1091 O << ", #" << (MO1.getImm() * Scale); 1092 } else { 1093 assert(MO1.isExpr() && "Unexpected operand type!"); 1094 O << ", " << *MO1.getExpr(); 1095 } 1096 O << ']'; 1097} 1098 1099void AArch64InstPrinter::printPrefetchOp(const MCInst *MI, unsigned OpNum, 1100 const MCSubtargetInfo &STI, 1101 raw_ostream &O) { 1102 unsigned prfop = MI->getOperand(OpNum).getImm(); 1103 bool Valid; 1104 StringRef Name = 1105 AArch64PRFM::PRFMMapper().toString(prfop, STI.getFeatureBits(), Valid); 1106 if (Valid) 1107 O << Name; 1108 else 1109 O << '#' << prfop; 1110} 1111 1112void AArch64InstPrinter::printFPImmOperand(const MCInst *MI, unsigned OpNum, 1113 const MCSubtargetInfo &STI, 1114 raw_ostream &O) { 1115 const MCOperand &MO = MI->getOperand(OpNum); 1116 float FPImm = 1117 MO.isFPImm() ? MO.getFPImm() : AArch64_AM::getFPImmFloat(MO.getImm()); 1118 1119 // 8 decimal places are enough to perfectly represent permitted floats. 1120 O << format("#%.8f", FPImm); 1121} 1122 1123static unsigned getNextVectorRegister(unsigned Reg, unsigned Stride = 1) { 1124 while (Stride--) { 1125 switch (Reg) { 1126 default: 1127 llvm_unreachable("Vector register expected!"); 1128 case AArch64::Q0: Reg = AArch64::Q1; break; 1129 case AArch64::Q1: Reg = AArch64::Q2; break; 1130 case AArch64::Q2: Reg = AArch64::Q3; break; 1131 case AArch64::Q3: Reg = AArch64::Q4; break; 1132 case AArch64::Q4: Reg = AArch64::Q5; break; 1133 case AArch64::Q5: Reg = AArch64::Q6; break; 1134 case AArch64::Q6: Reg = AArch64::Q7; break; 1135 case AArch64::Q7: Reg = AArch64::Q8; break; 1136 case AArch64::Q8: Reg = AArch64::Q9; break; 1137 case AArch64::Q9: Reg = AArch64::Q10; break; 1138 case AArch64::Q10: Reg = AArch64::Q11; break; 1139 case AArch64::Q11: Reg = AArch64::Q12; break; 1140 case AArch64::Q12: Reg = AArch64::Q13; break; 1141 case AArch64::Q13: Reg = AArch64::Q14; break; 1142 case AArch64::Q14: Reg = AArch64::Q15; break; 1143 case AArch64::Q15: Reg = AArch64::Q16; break; 1144 case AArch64::Q16: Reg = AArch64::Q17; break; 1145 case AArch64::Q17: Reg = AArch64::Q18; break; 1146 case AArch64::Q18: Reg = AArch64::Q19; break; 1147 case AArch64::Q19: Reg = AArch64::Q20; break; 1148 case AArch64::Q20: Reg = AArch64::Q21; break; 1149 case AArch64::Q21: Reg = AArch64::Q22; break; 1150 case AArch64::Q22: Reg = AArch64::Q23; break; 1151 case AArch64::Q23: Reg = AArch64::Q24; break; 1152 case AArch64::Q24: Reg = AArch64::Q25; break; 1153 case AArch64::Q25: Reg = AArch64::Q26; break; 1154 case AArch64::Q26: Reg = AArch64::Q27; break; 1155 case AArch64::Q27: Reg = AArch64::Q28; break; 1156 case AArch64::Q28: Reg = AArch64::Q29; break; 1157 case AArch64::Q29: Reg = AArch64::Q30; break; 1158 case AArch64::Q30: Reg = AArch64::Q31; break; 1159 // Vector lists can wrap around. 1160 case AArch64::Q31: 1161 Reg = AArch64::Q0; 1162 break; 1163 } 1164 } 1165 return Reg; 1166} 1167 1168void AArch64InstPrinter::printVectorList(const MCInst *MI, unsigned OpNum, 1169 const MCSubtargetInfo &STI, 1170 raw_ostream &O, 1171 StringRef LayoutSuffix) { 1172 unsigned Reg = MI->getOperand(OpNum).getReg(); 1173 1174 O << "{ "; 1175 1176 // Work out how many registers there are in the list (if there is an actual 1177 // list). 1178 unsigned NumRegs = 1; 1179 if (MRI.getRegClass(AArch64::DDRegClassID).contains(Reg) || 1180 MRI.getRegClass(AArch64::QQRegClassID).contains(Reg)) 1181 NumRegs = 2; 1182 else if (MRI.getRegClass(AArch64::DDDRegClassID).contains(Reg) || 1183 MRI.getRegClass(AArch64::QQQRegClassID).contains(Reg)) 1184 NumRegs = 3; 1185 else if (MRI.getRegClass(AArch64::DDDDRegClassID).contains(Reg) || 1186 MRI.getRegClass(AArch64::QQQQRegClassID).contains(Reg)) 1187 NumRegs = 4; 1188 1189 // Now forget about the list and find out what the first register is. 1190 if (unsigned FirstReg = MRI.getSubReg(Reg, AArch64::dsub0)) 1191 Reg = FirstReg; 1192 else if (unsigned FirstReg = MRI.getSubReg(Reg, AArch64::qsub0)) 1193 Reg = FirstReg; 1194 1195 // If it's a D-reg, we need to promote it to the equivalent Q-reg before 1196 // printing (otherwise getRegisterName fails). 1197 if (MRI.getRegClass(AArch64::FPR64RegClassID).contains(Reg)) { 1198 const MCRegisterClass &FPR128RC = 1199 MRI.getRegClass(AArch64::FPR128RegClassID); 1200 Reg = MRI.getMatchingSuperReg(Reg, AArch64::dsub, &FPR128RC); 1201 } 1202 1203 for (unsigned i = 0; i < NumRegs; ++i, Reg = getNextVectorRegister(Reg)) { 1204 O << getRegisterName(Reg, AArch64::vreg) << LayoutSuffix; 1205 if (i + 1 != NumRegs) 1206 O << ", "; 1207 } 1208 1209 O << " }"; 1210} 1211 1212void 1213AArch64InstPrinter::printImplicitlyTypedVectorList(const MCInst *MI, 1214 unsigned OpNum, 1215 const MCSubtargetInfo &STI, 1216 raw_ostream &O) { 1217 printVectorList(MI, OpNum, STI, O, ""); 1218} 1219 1220template <unsigned NumLanes, char LaneKind> 1221void AArch64InstPrinter::printTypedVectorList(const MCInst *MI, unsigned OpNum, 1222 const MCSubtargetInfo &STI, 1223 raw_ostream &O) { 1224 std::string Suffix("."); 1225 if (NumLanes) 1226 Suffix += itostr(NumLanes) + LaneKind; 1227 else 1228 Suffix += LaneKind; 1229 1230 printVectorList(MI, OpNum, STI, O, Suffix); 1231} 1232 1233void AArch64InstPrinter::printVectorIndex(const MCInst *MI, unsigned OpNum, 1234 const MCSubtargetInfo &STI, 1235 raw_ostream &O) { 1236 O << "[" << MI->getOperand(OpNum).getImm() << "]"; 1237} 1238 1239void AArch64InstPrinter::printAlignedLabel(const MCInst *MI, unsigned OpNum, 1240 const MCSubtargetInfo &STI, 1241 raw_ostream &O) { 1242 const MCOperand &Op = MI->getOperand(OpNum); 1243 1244 // If the label has already been resolved to an immediate offset (say, when 1245 // we're running the disassembler), just print the immediate. 1246 if (Op.isImm()) { 1247 O << "#" << (Op.getImm() * 4); 1248 return; 1249 } 1250 1251 // If the branch target is simply an address then print it in hex. 1252 const MCConstantExpr *BranchTarget = 1253 dyn_cast<MCConstantExpr>(MI->getOperand(OpNum).getExpr()); 1254 int64_t Address; 1255 if (BranchTarget && BranchTarget->EvaluateAsAbsolute(Address)) { 1256 O << "0x"; 1257 O.write_hex(Address); 1258 } else { 1259 // Otherwise, just print the expression. 1260 O << *MI->getOperand(OpNum).getExpr(); 1261 } 1262} 1263 1264void AArch64InstPrinter::printAdrpLabel(const MCInst *MI, unsigned OpNum, 1265 const MCSubtargetInfo &STI, 1266 raw_ostream &O) { 1267 const MCOperand &Op = MI->getOperand(OpNum); 1268 1269 // If the label has already been resolved to an immediate offset (say, when 1270 // we're running the disassembler), just print the immediate. 1271 if (Op.isImm()) { 1272 O << "#" << (Op.getImm() * (1 << 12)); 1273 return; 1274 } 1275 1276 // Otherwise, just print the expression. 1277 O << *MI->getOperand(OpNum).getExpr(); 1278} 1279 1280void AArch64InstPrinter::printBarrierOption(const MCInst *MI, unsigned OpNo, 1281 const MCSubtargetInfo &STI, 1282 raw_ostream &O) { 1283 unsigned Val = MI->getOperand(OpNo).getImm(); 1284 unsigned Opcode = MI->getOpcode(); 1285 1286 bool Valid; 1287 StringRef Name; 1288 if (Opcode == AArch64::ISB) 1289 Name = AArch64ISB::ISBMapper().toString(Val, STI.getFeatureBits(), 1290 Valid); 1291 else 1292 Name = AArch64DB::DBarrierMapper().toString(Val, STI.getFeatureBits(), 1293 Valid); 1294 if (Valid) 1295 O << Name; 1296 else 1297 O << "#" << Val; 1298} 1299 1300void AArch64InstPrinter::printMRSSystemRegister(const MCInst *MI, unsigned OpNo, 1301 const MCSubtargetInfo &STI, 1302 raw_ostream &O) { 1303 unsigned Val = MI->getOperand(OpNo).getImm(); 1304 1305 auto Mapper = AArch64SysReg::MRSMapper(); 1306 std::string Name = Mapper.toString(Val, STI.getFeatureBits()); 1307 1308 O << StringRef(Name).upper(); 1309} 1310 1311void AArch64InstPrinter::printMSRSystemRegister(const MCInst *MI, unsigned OpNo, 1312 const MCSubtargetInfo &STI, 1313 raw_ostream &O) { 1314 unsigned Val = MI->getOperand(OpNo).getImm(); 1315 1316 auto Mapper = AArch64SysReg::MSRMapper(); 1317 std::string Name = Mapper.toString(Val, STI.getFeatureBits()); 1318 1319 O << StringRef(Name).upper(); 1320} 1321 1322void AArch64InstPrinter::printSystemPStateField(const MCInst *MI, unsigned OpNo, 1323 const MCSubtargetInfo &STI, 1324 raw_ostream &O) { 1325 unsigned Val = MI->getOperand(OpNo).getImm(); 1326 1327 bool Valid; 1328 StringRef Name = 1329 AArch64PState::PStateMapper().toString(Val, STI.getFeatureBits(), Valid); 1330 if (Valid) 1331 O << StringRef(Name.str()).upper(); 1332 else 1333 O << "#" << Val; 1334} 1335 1336void AArch64InstPrinter::printSIMDType10Operand(const MCInst *MI, unsigned OpNo, 1337 const MCSubtargetInfo &STI, 1338 raw_ostream &O) { 1339 unsigned RawVal = MI->getOperand(OpNo).getImm(); 1340 uint64_t Val = AArch64_AM::decodeAdvSIMDModImmType10(RawVal); 1341 O << format("#%#016llx", Val); 1342} 1343