1//===-- ARMRegisterInfo.td - ARM Register defs -------------*- tablegen -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9
10//===----------------------------------------------------------------------===//
11//  Declarations that describe the ARM register file
12//===----------------------------------------------------------------------===//
13
14// Registers are identified with 4-bit ID numbers.
15class ARMReg<bits<16> Enc, string n, list<Register> subregs = []> : Register<n> {
16  let HWEncoding = Enc;
17  let Namespace = "ARM";
18  let SubRegs = subregs;
19  // All bits of ARM registers with sub-registers are covered by sub-registers.
20  let CoveredBySubRegs = 1;
21}
22
23class ARMFReg<bits<16> Enc, string n> : Register<n> {
24  let HWEncoding = Enc;
25  let Namespace = "ARM";
26}
27
28// Subregister indices.
29let Namespace = "ARM" in {
30def qqsub_0 : SubRegIndex<256>;
31def qqsub_1 : SubRegIndex<256, 256>;
32
33// Note: Code depends on these having consecutive numbers.
34def qsub_0 : SubRegIndex<128>;
35def qsub_1 : SubRegIndex<128, 128>;
36def qsub_2 : ComposedSubRegIndex<qqsub_1, qsub_0>;
37def qsub_3 : ComposedSubRegIndex<qqsub_1, qsub_1>;
38
39def dsub_0 : SubRegIndex<64>;
40def dsub_1 : SubRegIndex<64, 64>;
41def dsub_2 : ComposedSubRegIndex<qsub_1, dsub_0>;
42def dsub_3 : ComposedSubRegIndex<qsub_1, dsub_1>;
43def dsub_4 : ComposedSubRegIndex<qsub_2, dsub_0>;
44def dsub_5 : ComposedSubRegIndex<qsub_2, dsub_1>;
45def dsub_6 : ComposedSubRegIndex<qsub_3, dsub_0>;
46def dsub_7 : ComposedSubRegIndex<qsub_3, dsub_1>;
47
48def ssub_0  : SubRegIndex<32>;
49def ssub_1  : SubRegIndex<32, 32>;
50def ssub_2  : ComposedSubRegIndex<dsub_1, ssub_0>;
51def ssub_3  : ComposedSubRegIndex<dsub_1, ssub_1>;
52
53def gsub_0  : SubRegIndex<32>;
54def gsub_1  : SubRegIndex<32, 32>;
55// Let TableGen synthesize the remaining 12 ssub_* indices.
56// We don't need to name them.
57}
58
59// Integer registers
60def R0  : ARMReg< 0, "r0">,  DwarfRegNum<[0]>;
61def R1  : ARMReg< 1, "r1">,  DwarfRegNum<[1]>;
62def R2  : ARMReg< 2, "r2">,  DwarfRegNum<[2]>;
63def R3  : ARMReg< 3, "r3">,  DwarfRegNum<[3]>;
64def R4  : ARMReg< 4, "r4">,  DwarfRegNum<[4]>;
65def R5  : ARMReg< 5, "r5">,  DwarfRegNum<[5]>;
66def R6  : ARMReg< 6, "r6">,  DwarfRegNum<[6]>;
67def R7  : ARMReg< 7, "r7">,  DwarfRegNum<[7]>;
68// These require 32-bit instructions.
69let CostPerUse = 1 in {
70def R8  : ARMReg< 8, "r8">,  DwarfRegNum<[8]>;
71def R9  : ARMReg< 9, "r9">,  DwarfRegNum<[9]>;
72def R10 : ARMReg<10, "r10">, DwarfRegNum<[10]>;
73def R11 : ARMReg<11, "r11">, DwarfRegNum<[11]>;
74def R12 : ARMReg<12, "r12">, DwarfRegNum<[12]>;
75def SP  : ARMReg<13, "sp">,  DwarfRegNum<[13]>;
76def LR  : ARMReg<14, "lr">,  DwarfRegNum<[14]>;
77def PC  : ARMReg<15, "pc">,  DwarfRegNum<[15]>;
78}
79
80// Float registers
81def S0  : ARMFReg< 0, "s0">;  def S1  : ARMFReg< 1, "s1">;
82def S2  : ARMFReg< 2, "s2">;  def S3  : ARMFReg< 3, "s3">;
83def S4  : ARMFReg< 4, "s4">;  def S5  : ARMFReg< 5, "s5">;
84def S6  : ARMFReg< 6, "s6">;  def S7  : ARMFReg< 7, "s7">;
85def S8  : ARMFReg< 8, "s8">;  def S9  : ARMFReg< 9, "s9">;
86def S10 : ARMFReg<10, "s10">; def S11 : ARMFReg<11, "s11">;
87def S12 : ARMFReg<12, "s12">; def S13 : ARMFReg<13, "s13">;
88def S14 : ARMFReg<14, "s14">; def S15 : ARMFReg<15, "s15">;
89def S16 : ARMFReg<16, "s16">; def S17 : ARMFReg<17, "s17">;
90def S18 : ARMFReg<18, "s18">; def S19 : ARMFReg<19, "s19">;
91def S20 : ARMFReg<20, "s20">; def S21 : ARMFReg<21, "s21">;
92def S22 : ARMFReg<22, "s22">; def S23 : ARMFReg<23, "s23">;
93def S24 : ARMFReg<24, "s24">; def S25 : ARMFReg<25, "s25">;
94def S26 : ARMFReg<26, "s26">; def S27 : ARMFReg<27, "s27">;
95def S28 : ARMFReg<28, "s28">; def S29 : ARMFReg<29, "s29">;
96def S30 : ARMFReg<30, "s30">; def S31 : ARMFReg<31, "s31">;
97
98// Aliases of the F* registers used to hold 64-bit fp values (doubles)
99let SubRegIndices = [ssub_0, ssub_1] in {
100def D0  : ARMReg< 0,  "d0", [S0,   S1]>, DwarfRegNum<[256]>;
101def D1  : ARMReg< 1,  "d1", [S2,   S3]>, DwarfRegNum<[257]>;
102def D2  : ARMReg< 2,  "d2", [S4,   S5]>, DwarfRegNum<[258]>;
103def D3  : ARMReg< 3,  "d3", [S6,   S7]>, DwarfRegNum<[259]>;
104def D4  : ARMReg< 4,  "d4", [S8,   S9]>, DwarfRegNum<[260]>;
105def D5  : ARMReg< 5,  "d5", [S10, S11]>, DwarfRegNum<[261]>;
106def D6  : ARMReg< 6,  "d6", [S12, S13]>, DwarfRegNum<[262]>;
107def D7  : ARMReg< 7,  "d7", [S14, S15]>, DwarfRegNum<[263]>;
108def D8  : ARMReg< 8,  "d8", [S16, S17]>, DwarfRegNum<[264]>;
109def D9  : ARMReg< 9,  "d9", [S18, S19]>, DwarfRegNum<[265]>;
110def D10 : ARMReg<10, "d10", [S20, S21]>, DwarfRegNum<[266]>;
111def D11 : ARMReg<11, "d11", [S22, S23]>, DwarfRegNum<[267]>;
112def D12 : ARMReg<12, "d12", [S24, S25]>, DwarfRegNum<[268]>;
113def D13 : ARMReg<13, "d13", [S26, S27]>, DwarfRegNum<[269]>;
114def D14 : ARMReg<14, "d14", [S28, S29]>, DwarfRegNum<[270]>;
115def D15 : ARMReg<15, "d15", [S30, S31]>, DwarfRegNum<[271]>;
116}
117
118// VFP3 defines 16 additional double registers
119def D16 : ARMFReg<16, "d16">, DwarfRegNum<[272]>;
120def D17 : ARMFReg<17, "d17">, DwarfRegNum<[273]>;
121def D18 : ARMFReg<18, "d18">, DwarfRegNum<[274]>;
122def D19 : ARMFReg<19, "d19">, DwarfRegNum<[275]>;
123def D20 : ARMFReg<20, "d20">, DwarfRegNum<[276]>;
124def D21 : ARMFReg<21, "d21">, DwarfRegNum<[277]>;
125def D22 : ARMFReg<22, "d22">, DwarfRegNum<[278]>;
126def D23 : ARMFReg<23, "d23">, DwarfRegNum<[279]>;
127def D24 : ARMFReg<24, "d24">, DwarfRegNum<[280]>;
128def D25 : ARMFReg<25, "d25">, DwarfRegNum<[281]>;
129def D26 : ARMFReg<26, "d26">, DwarfRegNum<[282]>;
130def D27 : ARMFReg<27, "d27">, DwarfRegNum<[283]>;
131def D28 : ARMFReg<28, "d28">, DwarfRegNum<[284]>;
132def D29 : ARMFReg<29, "d29">, DwarfRegNum<[285]>;
133def D30 : ARMFReg<30, "d30">, DwarfRegNum<[286]>;
134def D31 : ARMFReg<31, "d31">, DwarfRegNum<[287]>;
135
136// Advanced SIMD (NEON) defines 16 quad-word aliases
137let SubRegIndices = [dsub_0, dsub_1] in {
138def Q0  : ARMReg< 0,  "q0", [D0,   D1]>;
139def Q1  : ARMReg< 1,  "q1", [D2,   D3]>;
140def Q2  : ARMReg< 2,  "q2", [D4,   D5]>;
141def Q3  : ARMReg< 3,  "q3", [D6,   D7]>;
142def Q4  : ARMReg< 4,  "q4", [D8,   D9]>;
143def Q5  : ARMReg< 5,  "q5", [D10, D11]>;
144def Q6  : ARMReg< 6,  "q6", [D12, D13]>;
145def Q7  : ARMReg< 7,  "q7", [D14, D15]>;
146}
147let SubRegIndices = [dsub_0, dsub_1] in {
148def Q8  : ARMReg< 8,  "q8", [D16, D17]>;
149def Q9  : ARMReg< 9,  "q9", [D18, D19]>;
150def Q10 : ARMReg<10, "q10", [D20, D21]>;
151def Q11 : ARMReg<11, "q11", [D22, D23]>;
152def Q12 : ARMReg<12, "q12", [D24, D25]>;
153def Q13 : ARMReg<13, "q13", [D26, D27]>;
154def Q14 : ARMReg<14, "q14", [D28, D29]>;
155def Q15 : ARMReg<15, "q15", [D30, D31]>;
156}
157
158// Current Program Status Register.
159// We model fpscr with two registers: FPSCR models the control bits and will be
160// reserved. FPSCR_NZCV models the flag bits and will be unreserved. APSR_NZCV
161// models the APSR when it's accessed by some special instructions. In such cases
162// it has the same encoding as PC.
163def CPSR       : ARMReg<0,  "cpsr">;
164def APSR       : ARMReg<1,  "apsr">;
165def APSR_NZCV  : ARMReg<15, "apsr_nzcv">;
166def SPSR       : ARMReg<2,  "spsr">;
167def FPSCR      : ARMReg<3,  "fpscr">;
168def FPSCR_NZCV : ARMReg<3,  "fpscr_nzcv"> {
169  let Aliases = [FPSCR];
170}
171def ITSTATE    : ARMReg<4, "itstate">;
172
173// Special Registers - only available in privileged mode.
174def FPSID   : ARMReg<0,  "fpsid">;
175def MVFR2   : ARMReg<5,  "mvfr2">;
176def MVFR1   : ARMReg<6,  "mvfr1">;
177def MVFR0   : ARMReg<7,  "mvfr0">;
178def FPEXC   : ARMReg<8,  "fpexc">;
179def FPINST  : ARMReg<9,  "fpinst">;
180def FPINST2 : ARMReg<10, "fpinst2">;
181
182// Register classes.
183//
184// pc  == Program Counter
185// lr  == Link Register
186// sp  == Stack Pointer
187// r12 == ip (scratch)
188// r7  == Frame Pointer (thumb-style backtraces)
189// r9  == May be reserved as Thread Register
190// r11 == Frame Pointer (arm-style backtraces)
191// r10 == Stack Limit
192//
193def GPR : RegisterClass<"ARM", [i32], 32, (add (sequence "R%u", 0, 12),
194                                               SP, LR, PC)> {
195  // Allocate LR as the first CSR since it is always saved anyway.
196  // For Thumb1 mode, we don't want to allocate hi regs at all, as we don't
197  // know how to spill them. If we make our prologue/epilogue code smarter at
198  // some point, we can go back to using the above allocation orders for the
199  // Thumb1 instructions that know how to use hi regs.
200  let AltOrders = [(add LR, GPR), (trunc GPR, 8)];
201  let AltOrderSelect = [{
202      return 1 + MF.getSubtarget<ARMSubtarget>().isThumb1Only();
203  }];
204}
205
206// GPRs without the PC.  Some ARM instructions do not allow the PC in
207// certain operand slots, particularly as the destination.  Primarily
208// useful for disassembly.
209def GPRnopc : RegisterClass<"ARM", [i32], 32, (sub GPR, PC)> {
210  let AltOrders = [(add LR, GPRnopc), (trunc GPRnopc, 8)];
211  let AltOrderSelect = [{
212      return 1 + MF.getSubtarget<ARMSubtarget>().isThumb1Only();
213  }];
214}
215
216// GPRs without the PC but with APSR. Some instructions allow accessing the
217// APSR, while actually encoding PC in the register field. This is useful
218// for assembly and disassembly only.
219def GPRwithAPSR : RegisterClass<"ARM", [i32], 32, (add (sub GPR, PC), APSR_NZCV)> {
220  let AltOrders = [(add LR, GPRnopc), (trunc GPRnopc, 8)];
221  let AltOrderSelect = [{
222      return 1 + MF.getSubtarget<ARMSubtarget>().isThumb1Only();
223  }];
224}
225
226// GPRsp - Only the SP is legal. Used by Thumb1 instructions that want the
227// implied SP argument list.
228// FIXME: It would be better to not use this at all and refactor the
229// instructions to not have SP an an explicit argument. That makes
230// frame index resolution a bit trickier, though.
231def GPRsp : RegisterClass<"ARM", [i32], 32, (add SP)>;
232
233// restricted GPR register class. Many Thumb2 instructions allow the full
234// register range for operands, but have undefined behaviours when PC
235// or SP (R13 or R15) are used. The ARM ISA refers to these operands
236// via the BadReg() pseudo-code description.
237def rGPR : RegisterClass<"ARM", [i32], 32, (sub GPR, SP, PC)> {
238  let AltOrders = [(add LR, rGPR), (trunc rGPR, 8)];
239  let AltOrderSelect = [{
240      return 1 + MF.getSubtarget<ARMSubtarget>().isThumb1Only();
241  }];
242}
243
244// Thumb registers are R0-R7 normally. Some instructions can still use
245// the general GPR register class above (MOV, e.g.)
246def tGPR : RegisterClass<"ARM", [i32], 32, (trunc GPR, 8)>;
247
248// The high registers in thumb mode, R8-R15.
249def hGPR : RegisterClass<"ARM", [i32], 32, (sub GPR, tGPR)>;
250
251// For tail calls, we can't use callee-saved registers, as they are restored
252// to the saved value before the tail call, which would clobber a call address.
253// Note, getMinimalPhysRegClass(R0) returns tGPR because of the names of
254// this class and the preceding one(!)  This is what we want.
255def tcGPR : RegisterClass<"ARM", [i32], 32, (add R0, R1, R2, R3, R12)> {
256  let AltOrders = [(and tcGPR, tGPR)];
257  let AltOrderSelect = [{
258      return MF.getSubtarget<ARMSubtarget>().isThumb1Only();
259  }];
260}
261
262// Condition code registers.
263def CCR : RegisterClass<"ARM", [i32], 32, (add CPSR)> {
264  let CopyCost = -1;  // Don't allow copying of status registers.
265  let isAllocatable = 0;
266}
267
268// Scalar single precision floating point register class..
269// FIXME: Allocation order changed to s0, s2, s4, ... as a quick hack to
270// avoid partial-write dependencies on D registers (S registers are
271// renamed as portions of D registers).
272def SPR : RegisterClass<"ARM", [f32], 32, (add (decimate
273                                                (sequence "S%u", 0, 31), 2),
274                                               (sequence "S%u", 0, 31))>;
275
276// Subset of SPR which can be used as a source of NEON scalars for 16-bit
277// operations
278def SPR_8 : RegisterClass<"ARM", [f32], 32, (sequence "S%u", 0, 15)>;
279
280// Scalar double precision floating point / generic 64-bit vector register
281// class.
282// ARM requires only word alignment for double. It's more performant if it
283// is double-word alignment though.
284def DPR : RegisterClass<"ARM", [f64, v8i8, v4i16, v2i32, v1i64, v2f32], 64,
285                        (sequence "D%u", 0, 31)> {
286  // Allocate non-VFP2 registers D16-D31 first.
287  let AltOrders = [(rotl DPR, 16)];
288  let AltOrderSelect = [{ return 1; }];
289}
290
291// Subset of DPR that are accessible with VFP2 (and so that also have
292// 32-bit SPR subregs).
293def DPR_VFP2 : RegisterClass<"ARM", [f64, v8i8, v4i16, v2i32, v1i64, v2f32], 64,
294                             (trunc DPR, 16)>;
295
296// Subset of DPR which can be used as a source of NEON scalars for 16-bit
297// operations
298def DPR_8 : RegisterClass<"ARM", [f64, v8i8, v4i16, v2i32, v1i64, v2f32], 64,
299                          (trunc DPR, 8)>;
300
301// Generic 128-bit vector register class.
302def QPR : RegisterClass<"ARM", [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], 128,
303                        (sequence "Q%u", 0, 15)> {
304  // Allocate non-VFP2 aliases Q8-Q15 first.
305  let AltOrders = [(rotl QPR, 8)];
306  let AltOrderSelect = [{ return 1; }];
307}
308
309// Subset of QPR that have 32-bit SPR subregs.
310def QPR_VFP2 : RegisterClass<"ARM", [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
311                             128, (trunc QPR, 8)>;
312
313// Subset of QPR that have DPR_8 and SPR_8 subregs.
314def QPR_8 : RegisterClass<"ARM", [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
315                           128, (trunc QPR, 4)>;
316
317// Pseudo-registers representing odd-even pairs of D registers. The even-odd
318// pairs are already represented by the Q registers.
319// These are needed by NEON instructions requiring two consecutive D registers.
320// There is no D31_D0 register as that is always an UNPREDICTABLE encoding.
321def TuplesOE2D : RegisterTuples<[dsub_0, dsub_1],
322                                [(decimate (shl DPR, 1), 2),
323                                 (decimate (shl DPR, 2), 2)]>;
324
325// Register class representing a pair of consecutive D registers.
326// Use the Q registers for the even-odd pairs.
327def DPair : RegisterClass<"ARM", [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
328                          128, (interleave QPR, TuplesOE2D)> {
329  // Allocate starting at non-VFP2 registers D16-D31 first.
330  // Prefer even-odd pairs as they are easier to copy.
331  let AltOrders = [(add (rotl QPR, 8), (rotl DPair, 16))];
332  let AltOrderSelect = [{ return 1; }];
333}
334
335// Pseudo-registers representing even-odd pairs of GPRs from R1 to R13/SP.
336// These are needed by instructions (e.g. ldrexd/strexd) requiring even-odd GPRs.
337def Tuples2R : RegisterTuples<[gsub_0, gsub_1],
338                              [(add R0, R2, R4, R6, R8, R10, R12),
339                               (add R1, R3, R5, R7, R9, R11, SP)]>;
340
341// Register class representing a pair of even-odd GPRs.
342def GPRPair : RegisterClass<"ARM", [untyped], 64, (add Tuples2R)> {
343  let Size = 64; // 2 x 32 bits, we have no predefined type of that size.
344}
345
346// Pseudo-registers representing 3 consecutive D registers.
347def Tuples3D : RegisterTuples<[dsub_0, dsub_1, dsub_2],
348                              [(shl DPR, 0),
349                               (shl DPR, 1),
350                               (shl DPR, 2)]>;
351
352// 3 consecutive D registers.
353def DTriple : RegisterClass<"ARM", [untyped], 64, (add Tuples3D)> {
354  let Size = 192; // 3 x 64 bits, we have no predefined type of that size.
355}
356
357// Pseudo 256-bit registers to represent pairs of Q registers. These should
358// never be present in the emitted code.
359// These are used for NEON load / store instructions, e.g., vld4, vst3.
360def Tuples2Q : RegisterTuples<[qsub_0, qsub_1], [(shl QPR, 0), (shl QPR, 1)]>;
361
362// Pseudo 256-bit vector register class to model pairs of Q registers
363// (4 consecutive D registers).
364def QQPR : RegisterClass<"ARM", [v4i64], 256, (add Tuples2Q)> {
365  // Allocate non-VFP2 aliases first.
366  let AltOrders = [(rotl QQPR, 8)];
367  let AltOrderSelect = [{ return 1; }];
368}
369
370// Tuples of 4 D regs that isn't also a pair of Q regs.
371def TuplesOE4D : RegisterTuples<[dsub_0, dsub_1, dsub_2, dsub_3],
372                                [(decimate (shl DPR, 1), 2),
373                                 (decimate (shl DPR, 2), 2),
374                                 (decimate (shl DPR, 3), 2),
375                                 (decimate (shl DPR, 4), 2)]>;
376
377// 4 consecutive D registers.
378def DQuad : RegisterClass<"ARM", [v4i64], 256,
379                          (interleave Tuples2Q, TuplesOE4D)>;
380
381// Pseudo 512-bit registers to represent four consecutive Q registers.
382def Tuples2QQ : RegisterTuples<[qqsub_0, qqsub_1],
383                               [(shl QQPR, 0), (shl QQPR, 2)]>;
384
385// Pseudo 512-bit vector register class to model 4 consecutive Q registers
386// (8 consecutive D registers).
387def QQQQPR : RegisterClass<"ARM", [v8i64], 256, (add Tuples2QQ)> {
388  // Allocate non-VFP2 aliases first.
389  let AltOrders = [(rotl QQQQPR, 8)];
390  let AltOrderSelect = [{ return 1; }];
391}
392
393
394// Pseudo-registers representing 2-spaced consecutive D registers.
395def Tuples2DSpc : RegisterTuples<[dsub_0, dsub_2],
396                                 [(shl DPR, 0),
397                                  (shl DPR, 2)]>;
398
399// Spaced pairs of D registers.
400def DPairSpc : RegisterClass<"ARM", [v2i64], 64, (add Tuples2DSpc)>;
401
402def Tuples3DSpc : RegisterTuples<[dsub_0, dsub_2, dsub_4],
403                                 [(shl DPR, 0),
404                                  (shl DPR, 2),
405                                  (shl DPR, 4)]>;
406
407// Spaced triples of D registers.
408def DTripleSpc : RegisterClass<"ARM", [untyped], 64, (add Tuples3DSpc)> {
409  let Size = 192; // 3 x 64 bits, we have no predefined type of that size.
410}
411
412def Tuples4DSpc : RegisterTuples<[dsub_0, dsub_2, dsub_4, dsub_6],
413                                 [(shl DPR, 0),
414                                  (shl DPR, 2),
415                                  (shl DPR, 4),
416                                  (shl DPR, 6)]>;
417
418// Spaced quads of D registers.
419def DQuadSpc : RegisterClass<"ARM", [v4i64], 64, (add Tuples3DSpc)>;
420