1//===-- SystemZMCTargetDesc.h - SystemZ target descriptions -----*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9
10#ifndef LLVM_LIB_TARGET_SYSTEMZ_MCTARGETDESC_SYSTEMZMCTARGETDESC_H
11#define LLVM_LIB_TARGET_SYSTEMZ_MCTARGETDESC_SYSTEMZMCTARGETDESC_H
12
13#include "llvm/Support/DataTypes.h"
14
15namespace llvm {
16
17class MCAsmBackend;
18class MCCodeEmitter;
19class MCContext;
20class MCInstrInfo;
21class MCObjectWriter;
22class MCRegisterInfo;
23class MCSubtargetInfo;
24class StringRef;
25class Target;
26class raw_pwrite_stream;
27class raw_ostream;
28
29extern Target TheSystemZTarget;
30
31namespace SystemZMC {
32// How many bytes are in the ABI-defined, caller-allocated part of
33// a stack frame.
34const int64_t CallFrameSize = 160;
35
36// The offset of the DWARF CFA from the incoming stack pointer.
37const int64_t CFAOffsetFromInitialSP = CallFrameSize;
38
39// Maps of asm register numbers to LLVM register numbers, with 0 indicating
40// an invalid register.  In principle we could use 32-bit and 64-bit register
41// classes directly, provided that we relegated the GPR allocation order
42// in SystemZRegisterInfo.td to an AltOrder and left the default order
43// as %r0-%r15.  It seems better to provide the same interface for
44// all classes though.
45extern const unsigned GR32Regs[16];
46extern const unsigned GRH32Regs[16];
47extern const unsigned GR64Regs[16];
48extern const unsigned GR128Regs[16];
49extern const unsigned FP32Regs[16];
50extern const unsigned FP64Regs[16];
51extern const unsigned FP128Regs[16];
52
53// Return the 0-based number of the first architectural register that
54// contains the given LLVM register.   E.g. R1D -> 1.
55unsigned getFirstReg(unsigned Reg);
56
57// Return the given register as a GR64.
58inline unsigned getRegAsGR64(unsigned Reg) {
59  return GR64Regs[getFirstReg(Reg)];
60}
61
62// Return the given register as a low GR32.
63inline unsigned getRegAsGR32(unsigned Reg) {
64  return GR32Regs[getFirstReg(Reg)];
65}
66
67// Return the given register as a high GR32.
68inline unsigned getRegAsGRH32(unsigned Reg) {
69  return GRH32Regs[getFirstReg(Reg)];
70}
71} // end namespace SystemZMC
72
73MCCodeEmitter *createSystemZMCCodeEmitter(const MCInstrInfo &MCII,
74                                          const MCRegisterInfo &MRI,
75                                          MCContext &Ctx);
76
77MCAsmBackend *createSystemZMCAsmBackend(const Target &T,
78                                        const MCRegisterInfo &MRI,
79                                        StringRef TT, StringRef CPU);
80
81MCObjectWriter *createSystemZObjectWriter(raw_pwrite_stream &OS, uint8_t OSABI);
82} // end namespace llvm
83
84// Defines symbolic names for SystemZ registers.
85// This defines a mapping from register name to register number.
86#define GET_REGINFO_ENUM
87#include "SystemZGenRegisterInfo.inc"
88
89// Defines symbolic names for the SystemZ instructions.
90#define GET_INSTRINFO_ENUM
91#include "SystemZGenInstrInfo.inc"
92
93#define GET_SUBTARGETINFO_ENUM
94#include "SystemZGenSubtargetInfo.inc"
95
96#endif
97