1//===-- X86InstrSystem.td - System Instructions ------------*- tablegen -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file describes the X86 instructions that are generally used in
11// privileged modes.  These are not typically used by the compiler, but are
12// supported for the assembler and disassembler.
13//
14//===----------------------------------------------------------------------===//
15
16let SchedRW = [WriteSystem] in {
17let Defs = [RAX, RDX] in
18  def RDTSC : I<0x31, RawFrm, (outs), (ins), "rdtsc", [(X86rdtsc)], IIC_RDTSC>,
19              TB;
20
21let Defs = [RAX, RCX, RDX] in
22  def RDTSCP : I<0x01, MRM_F9, (outs), (ins), "rdtscp", [(X86rdtscp)]>, TB;
23
24// CPU flow control instructions
25
26let isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in {
27  def TRAP    : I<0x0B, RawFrm, (outs), (ins), "ud2", [(trap)]>, TB;
28  def UD2B    : I<0xB9, RawFrm, (outs), (ins), "ud2b", []>, TB;
29}
30
31def HLT : I<0xF4, RawFrm, (outs), (ins), "hlt", [], IIC_HLT>;
32def RSM : I<0xAA, RawFrm, (outs), (ins), "rsm", [], IIC_RSM>, TB;
33
34// Interrupt and SysCall Instructions.
35let Uses = [EFLAGS] in
36  def INTO : I<0xce, RawFrm, (outs), (ins), "into", []>;
37def INT3 : I<0xcc, RawFrm, (outs), (ins), "int3",
38              [(int_x86_int (i8 3))], IIC_INT3>;
39} // SchedRW
40
41// The long form of "int $3" turns into int3 as a size optimization.
42// FIXME: This doesn't work because InstAlias can't match immediate constants.
43//def : InstAlias<"int\t$3", (INT3)>;
44
45let SchedRW = [WriteSystem] in {
46
47def INT : Ii8<0xcd, RawFrm, (outs), (ins i8imm:$trap), "int\t$trap",
48              [(int_x86_int imm:$trap)], IIC_INT>;
49
50
51def SYSCALL  : I<0x05, RawFrm, (outs), (ins), "syscall", [], IIC_SYSCALL>, TB;
52def SYSRET   : I<0x07, RawFrm, (outs), (ins), "sysret{l}", [], IIC_SYSCALL>, TB;
53def SYSRET64 :RI<0x07, RawFrm, (outs), (ins), "sysret{q}", [], IIC_SYSCALL>, TB,
54               Requires<[In64BitMode]>;
55
56def SYSENTER : I<0x34, RawFrm, (outs), (ins), "sysenter", [],
57                 IIC_SYS_ENTER_EXIT>, TB;
58
59def SYSEXIT   : I<0x35, RawFrm, (outs), (ins), "sysexit{l}", [],
60                 IIC_SYS_ENTER_EXIT>, TB;
61def SYSEXIT64 :RI<0x35, RawFrm, (outs), (ins), "sysexit{q}", [],
62                 IIC_SYS_ENTER_EXIT>, TB, Requires<[In64BitMode]>;
63
64def IRET16 : I<0xcf, RawFrm, (outs), (ins), "iret{w}", [], IIC_IRET>, OpSize16;
65def IRET32 : I<0xcf, RawFrm, (outs), (ins), "iret{l|d}", [], IIC_IRET>,
66             OpSize32;
67def IRET64 : RI<0xcf, RawFrm, (outs), (ins), "iretq", [], IIC_IRET>,
68             Requires<[In64BitMode]>;
69} // SchedRW
70
71def : Pat<(debugtrap),
72          (INT3)>, Requires<[NotPS4]>;
73def : Pat<(debugtrap),
74          (INT (i8 0x41))>, Requires<[IsPS4]>;
75
76//===----------------------------------------------------------------------===//
77//  Input/Output Instructions.
78//
79let SchedRW = [WriteSystem] in {
80let Defs = [AL], Uses = [DX] in
81def IN8rr  : I<0xEC, RawFrm, (outs), (ins),
82               "in{b}\t{%dx, %al|al, dx}", [], IIC_IN_RR>;
83let Defs = [AX], Uses = [DX] in
84def IN16rr : I<0xED, RawFrm, (outs), (ins),
85               "in{w}\t{%dx, %ax|ax, dx}", [], IIC_IN_RR>,  OpSize16;
86let Defs = [EAX], Uses = [DX] in
87def IN32rr : I<0xED, RawFrm, (outs), (ins),
88               "in{l}\t{%dx, %eax|eax, dx}", [], IIC_IN_RR>, OpSize32;
89
90let Defs = [AL] in
91def IN8ri  : Ii8<0xE4, RawFrm, (outs), (ins i8imm:$port),
92                  "in{b}\t{$port, %al|al, $port}", [], IIC_IN_RI>;
93let Defs = [AX] in
94def IN16ri : Ii8<0xE5, RawFrm, (outs), (ins i8imm:$port),
95                  "in{w}\t{$port, %ax|ax, $port}", [], IIC_IN_RI>, OpSize16;
96let Defs = [EAX] in
97def IN32ri : Ii8<0xE5, RawFrm, (outs), (ins i8imm:$port),
98                  "in{l}\t{$port, %eax|eax, $port}", [], IIC_IN_RI>, OpSize32;
99
100let Uses = [DX, AL] in
101def OUT8rr  : I<0xEE, RawFrm, (outs), (ins),
102                "out{b}\t{%al, %dx|dx, al}", [], IIC_OUT_RR>;
103let Uses = [DX, AX] in
104def OUT16rr : I<0xEF, RawFrm, (outs), (ins),
105                "out{w}\t{%ax, %dx|dx, ax}", [], IIC_OUT_RR>, OpSize16;
106let Uses = [DX, EAX] in
107def OUT32rr : I<0xEF, RawFrm, (outs), (ins),
108                "out{l}\t{%eax, %dx|dx, eax}", [], IIC_OUT_RR>, OpSize32;
109
110let Uses = [AL] in
111def OUT8ir  : Ii8<0xE6, RawFrm, (outs), (ins i8imm:$port),
112                   "out{b}\t{%al, $port|$port, al}", [], IIC_OUT_IR>;
113let Uses = [AX] in
114def OUT16ir : Ii8<0xE7, RawFrm, (outs), (ins i8imm:$port),
115                   "out{w}\t{%ax, $port|$port, ax}", [], IIC_OUT_IR>, OpSize16;
116let Uses = [EAX] in
117def OUT32ir : Ii8<0xE7, RawFrm, (outs), (ins i8imm:$port),
118                  "out{l}\t{%eax, $port|$port, eax}", [], IIC_OUT_IR>, OpSize32;
119
120} // SchedRW
121
122//===----------------------------------------------------------------------===//
123// Moves to and from debug registers
124
125let SchedRW = [WriteSystem] in {
126def MOV32rd : I<0x21, MRMDestReg, (outs GR32:$dst), (ins DEBUG_REG:$src),
127                "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_REG_DR>, TB,
128                Requires<[Not64BitMode]>;
129def MOV64rd : I<0x21, MRMDestReg, (outs GR64:$dst), (ins DEBUG_REG:$src),
130                "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV_REG_DR>, TB,
131                Requires<[In64BitMode]>;
132
133def MOV32dr : I<0x23, MRMSrcReg, (outs DEBUG_REG:$dst), (ins GR32:$src),
134                "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_DR_REG>, TB,
135                Requires<[Not64BitMode]>;
136def MOV64dr : I<0x23, MRMSrcReg, (outs DEBUG_REG:$dst), (ins GR64:$src),
137                "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV_DR_REG>, TB,
138                Requires<[In64BitMode]>;
139} // SchedRW
140
141//===----------------------------------------------------------------------===//
142// Moves to and from control registers
143
144let SchedRW = [WriteSystem] in {
145def MOV32rc : I<0x20, MRMDestReg, (outs GR32:$dst), (ins CONTROL_REG:$src),
146                "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_REG_CR>, TB,
147                Requires<[Not64BitMode]>;
148def MOV64rc : I<0x20, MRMDestReg, (outs GR64:$dst), (ins CONTROL_REG:$src),
149                "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV_REG_CR>, TB,
150                Requires<[In64BitMode]>;
151
152def MOV32cr : I<0x22, MRMSrcReg, (outs CONTROL_REG:$dst), (ins GR32:$src),
153                "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_CR_REG>, TB,
154                Requires<[Not64BitMode]>;
155def MOV64cr : I<0x22, MRMSrcReg, (outs CONTROL_REG:$dst), (ins GR64:$src),
156                "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV_CR_REG>, TB,
157                Requires<[In64BitMode]>;
158} // SchedRW
159
160//===----------------------------------------------------------------------===//
161// Segment override instruction prefixes
162
163def CS_PREFIX : I<0x2E, RawFrm, (outs), (ins), "cs", []>;
164def SS_PREFIX : I<0x36, RawFrm, (outs), (ins), "ss", []>;
165def DS_PREFIX : I<0x3E, RawFrm, (outs), (ins), "ds", []>;
166def ES_PREFIX : I<0x26, RawFrm, (outs), (ins), "es", []>;
167def FS_PREFIX : I<0x64, RawFrm, (outs), (ins), "fs", []>;
168def GS_PREFIX : I<0x65, RawFrm, (outs), (ins), "gs", []>;
169
170
171//===----------------------------------------------------------------------===//
172// Moves to and from segment registers.
173//
174
175let SchedRW = [WriteMove] in {
176def MOV16rs : I<0x8C, MRMDestReg, (outs GR16:$dst), (ins SEGMENT_REG:$src),
177                "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV_REG_SR>, OpSize16;
178def MOV32rs : I<0x8C, MRMDestReg, (outs GR32:$dst), (ins SEGMENT_REG:$src),
179                "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_REG_SR>, OpSize32;
180def MOV64rs : RI<0x8C, MRMDestReg, (outs GR64:$dst), (ins SEGMENT_REG:$src),
181                 "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV_REG_SR>;
182
183def MOV16ms : I<0x8C, MRMDestMem, (outs i16mem:$dst), (ins SEGMENT_REG:$src),
184                "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV_MEM_SR>, OpSize16;
185def MOV32ms : I<0x8C, MRMDestMem, (outs i32mem:$dst), (ins SEGMENT_REG:$src),
186                "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_MEM_SR>, OpSize32;
187def MOV64ms : RI<0x8C, MRMDestMem, (outs i64mem:$dst), (ins SEGMENT_REG:$src),
188                 "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV_MEM_SR>;
189
190def MOV16sr : I<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR16:$src),
191                "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV_SR_REG>, OpSize16;
192def MOV32sr : I<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR32:$src),
193                "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_SR_REG>, OpSize32;
194def MOV64sr : RI<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR64:$src),
195                 "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV_SR_REG>;
196
197def MOV16sm : I<0x8E, MRMSrcMem, (outs SEGMENT_REG:$dst), (ins i16mem:$src),
198                "mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV_SR_MEM>, OpSize16;
199def MOV32sm : I<0x8E, MRMSrcMem, (outs SEGMENT_REG:$dst), (ins i32mem:$src),
200                "mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_SR_MEM>, OpSize32;
201def MOV64sm : RI<0x8E, MRMSrcMem, (outs SEGMENT_REG:$dst), (ins i64mem:$src),
202                 "mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV_SR_MEM>;
203} // SchedRW
204
205//===----------------------------------------------------------------------===//
206// Segmentation support instructions.
207
208let SchedRW = [WriteSystem] in {
209def SWAPGS : I<0x01, MRM_F8, (outs), (ins), "swapgs", [], IIC_SWAPGS>, TB;
210
211def LAR16rm : I<0x02, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
212                "lar{w}\t{$src, $dst|$dst, $src}", [], IIC_LAR_RM>, TB,
213                OpSize16;
214def LAR16rr : I<0x02, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
215                "lar{w}\t{$src, $dst|$dst, $src}", [], IIC_LAR_RR>, TB,
216                OpSize16;
217
218// i16mem operand in LAR32rm and GR32 operand in LAR32rr is not a typo.
219def LAR32rm : I<0x02, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
220                "lar{l}\t{$src, $dst|$dst, $src}", [], IIC_LAR_RM>, TB,
221                OpSize32;
222def LAR32rr : I<0x02, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
223                "lar{l}\t{$src, $dst|$dst, $src}", [], IIC_LAR_RR>, TB,
224                OpSize32;
225// i16mem operand in LAR64rm and GR32 operand in LAR32rr is not a typo.
226def LAR64rm : RI<0x02, MRMSrcMem, (outs GR64:$dst), (ins i16mem:$src),
227                 "lar{q}\t{$src, $dst|$dst, $src}", [], IIC_LAR_RM>, TB;
228def LAR64rr : RI<0x02, MRMSrcReg, (outs GR64:$dst), (ins GR32:$src),
229                 "lar{q}\t{$src, $dst|$dst, $src}", [], IIC_LAR_RR>, TB;
230
231def LSL16rm : I<0x03, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
232                "lsl{w}\t{$src, $dst|$dst, $src}", [], IIC_LSL_RM>, TB,
233                OpSize16;
234def LSL16rr : I<0x03, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
235                "lsl{w}\t{$src, $dst|$dst, $src}", [], IIC_LSL_RR>, TB,
236                OpSize16;
237def LSL32rm : I<0x03, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
238                "lsl{l}\t{$src, $dst|$dst, $src}", [], IIC_LSL_RM>, TB,
239                OpSize32;
240def LSL32rr : I<0x03, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
241                "lsl{l}\t{$src, $dst|$dst, $src}", [], IIC_LSL_RR>, TB,
242                OpSize32;
243def LSL64rm : RI<0x03, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
244                 "lsl{q}\t{$src, $dst|$dst, $src}", [], IIC_LSL_RM>, TB;
245def LSL64rr : RI<0x03, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
246                 "lsl{q}\t{$src, $dst|$dst, $src}", [], IIC_LSL_RR>, TB;
247
248def INVLPG : I<0x01, MRM7m, (outs), (ins i8mem:$addr), "invlpg\t$addr",
249               [], IIC_INVLPG>, TB;
250
251def STR16r : I<0x00, MRM1r, (outs GR16:$dst), (ins),
252               "str{w}\t$dst", [], IIC_STR>, TB, OpSize16;
253def STR32r : I<0x00, MRM1r, (outs GR32:$dst), (ins),
254               "str{l}\t$dst", [], IIC_STR>, TB, OpSize32;
255def STR64r : RI<0x00, MRM1r, (outs GR64:$dst), (ins),
256                "str{q}\t$dst", [], IIC_STR>, TB;
257def STRm   : I<0x00, MRM1m, (outs i16mem:$dst), (ins),
258               "str{w}\t$dst", [], IIC_STR>, TB;
259
260def LTRr : I<0x00, MRM3r, (outs), (ins GR16:$src),
261             "ltr{w}\t$src", [], IIC_LTR>, TB;
262def LTRm : I<0x00, MRM3m, (outs), (ins i16mem:$src),
263             "ltr{w}\t$src", [], IIC_LTR>, TB;
264
265def PUSHCS16 : I<0x0E, RawFrm, (outs), (ins),
266                 "push{w}\t{%cs|cs}", [], IIC_PUSH_SR>,
267                 OpSize16, Requires<[Not64BitMode]>;
268def PUSHCS32 : I<0x0E, RawFrm, (outs), (ins),
269                 "push{l}\t{%cs|cs}", [], IIC_PUSH_CS>,
270                 OpSize32, Requires<[Not64BitMode]>;
271def PUSHSS16 : I<0x16, RawFrm, (outs), (ins),
272                 "push{w}\t{%ss|ss}", [], IIC_PUSH_SR>,
273                 OpSize16, Requires<[Not64BitMode]>;
274def PUSHSS32 : I<0x16, RawFrm, (outs), (ins),
275                 "push{l}\t{%ss|ss}", [], IIC_PUSH_SR>,
276                 OpSize32, Requires<[Not64BitMode]>;
277def PUSHDS16 : I<0x1E, RawFrm, (outs), (ins),
278                 "push{w}\t{%ds|ds}", [], IIC_PUSH_SR>,
279                 OpSize16, Requires<[Not64BitMode]>;
280def PUSHDS32 : I<0x1E, RawFrm, (outs), (ins),
281                 "push{l}\t{%ds|ds}", [], IIC_PUSH_SR>,
282                 OpSize32, Requires<[Not64BitMode]>;
283def PUSHES16 : I<0x06, RawFrm, (outs), (ins),
284                 "push{w}\t{%es|es}", [], IIC_PUSH_SR>,
285                 OpSize16, Requires<[Not64BitMode]>;
286def PUSHES32 : I<0x06, RawFrm, (outs), (ins),
287                 "push{l}\t{%es|es}", [], IIC_PUSH_SR>,
288                 OpSize32, Requires<[Not64BitMode]>;
289def PUSHFS16 : I<0xa0, RawFrm, (outs), (ins),
290                 "push{w}\t{%fs|fs}", [], IIC_PUSH_SR>, OpSize16, TB;
291def PUSHFS32 : I<0xa0, RawFrm, (outs), (ins),
292                 "push{l}\t{%fs|fs}", [], IIC_PUSH_SR>, TB,
293               OpSize32, Requires<[Not64BitMode]>;
294def PUSHGS16 : I<0xa8, RawFrm, (outs), (ins),
295                 "push{w}\t{%gs|gs}", [], IIC_PUSH_SR>, OpSize16, TB;
296def PUSHGS32 : I<0xa8, RawFrm, (outs), (ins),
297                 "push{l}\t{%gs|gs}", [], IIC_PUSH_SR>, TB,
298               OpSize32, Requires<[Not64BitMode]>;
299def PUSHFS64 : I<0xa0, RawFrm, (outs), (ins),
300                 "push{q}\t{%fs|fs}", [], IIC_PUSH_SR>, TB,
301               OpSize32, Requires<[In64BitMode]>;
302def PUSHGS64 : I<0xa8, RawFrm, (outs), (ins),
303                 "push{q}\t{%gs|gs}", [], IIC_PUSH_SR>, TB,
304               OpSize32, Requires<[In64BitMode]>;
305
306// No "pop cs" instruction.
307def POPSS16 : I<0x17, RawFrm, (outs), (ins),
308                "pop{w}\t{%ss|ss}", [], IIC_POP_SR_SS>,
309              OpSize16, Requires<[Not64BitMode]>;
310def POPSS32 : I<0x17, RawFrm, (outs), (ins),
311                "pop{l}\t{%ss|ss}", [], IIC_POP_SR_SS>,
312              OpSize32, Requires<[Not64BitMode]>;
313
314def POPDS16 : I<0x1F, RawFrm, (outs), (ins),
315                "pop{w}\t{%ds|ds}", [], IIC_POP_SR>,
316              OpSize16, Requires<[Not64BitMode]>;
317def POPDS32 : I<0x1F, RawFrm, (outs), (ins),
318                "pop{l}\t{%ds|ds}", [], IIC_POP_SR>,
319              OpSize32, Requires<[Not64BitMode]>;
320
321def POPES16 : I<0x07, RawFrm, (outs), (ins),
322                "pop{w}\t{%es|es}", [], IIC_POP_SR>,
323              OpSize16, Requires<[Not64BitMode]>;
324def POPES32 : I<0x07, RawFrm, (outs), (ins),
325                "pop{l}\t{%es|es}", [], IIC_POP_SR>,
326              OpSize32, Requires<[Not64BitMode]>;
327
328def POPFS16 : I<0xa1, RawFrm, (outs), (ins),
329                "pop{w}\t{%fs|fs}", [], IIC_POP_SR>, OpSize16, TB;
330def POPFS32 : I<0xa1, RawFrm, (outs), (ins),
331                "pop{l}\t{%fs|fs}", [], IIC_POP_SR>, TB,
332              OpSize32, Requires<[Not64BitMode]>;
333def POPFS64 : I<0xa1, RawFrm, (outs), (ins),
334                "pop{q}\t{%fs|fs}", [], IIC_POP_SR>, TB,
335              OpSize32, Requires<[In64BitMode]>;
336
337def POPGS16 : I<0xa9, RawFrm, (outs), (ins),
338                "pop{w}\t{%gs|gs}", [], IIC_POP_SR>, OpSize16, TB;
339def POPGS32 : I<0xa9, RawFrm, (outs), (ins),
340                "pop{l}\t{%gs|gs}", [], IIC_POP_SR>, TB,
341              OpSize32, Requires<[Not64BitMode]>;
342def POPGS64 : I<0xa9, RawFrm, (outs), (ins),
343                "pop{q}\t{%gs|gs}", [], IIC_POP_SR>, TB,
344              OpSize32, Requires<[In64BitMode]>;
345
346
347def LDS16rm : I<0xc5, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
348                "lds{w}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, OpSize16;
349def LDS32rm : I<0xc5, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
350                "lds{l}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, OpSize32;
351
352def LSS16rm : I<0xb2, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
353                "lss{w}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB, OpSize16;
354def LSS32rm : I<0xb2, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
355                "lss{l}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB, OpSize32;
356def LSS64rm : RI<0xb2, MRMSrcMem, (outs GR64:$dst), (ins opaque80mem:$src),
357                 "lss{q}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB;
358
359def LES16rm : I<0xc4, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
360                "les{w}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, OpSize16;
361def LES32rm : I<0xc4, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
362                "les{l}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, OpSize32;
363
364def LFS16rm : I<0xb4, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
365                "lfs{w}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB, OpSize16;
366def LFS32rm : I<0xb4, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
367                "lfs{l}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB, OpSize32;
368def LFS64rm : RI<0xb4, MRMSrcMem, (outs GR64:$dst), (ins opaque80mem:$src),
369                 "lfs{q}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB;
370
371def LGS16rm : I<0xb5, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
372                "lgs{w}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB, OpSize16;
373def LGS32rm : I<0xb5, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
374                "lgs{l}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB, OpSize32;
375
376def LGS64rm : RI<0xb5, MRMSrcMem, (outs GR64:$dst), (ins opaque80mem:$src),
377                 "lgs{q}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB;
378
379
380def VERRr : I<0x00, MRM4r, (outs), (ins GR16:$seg),
381              "verr\t$seg", [], IIC_VERR>, TB;
382def VERRm : I<0x00, MRM4m, (outs), (ins i16mem:$seg),
383              "verr\t$seg", [], IIC_VERR>, TB;
384def VERWr : I<0x00, MRM5r, (outs), (ins GR16:$seg),
385              "verw\t$seg", [], IIC_VERW_MEM>, TB;
386def VERWm : I<0x00, MRM5m, (outs), (ins i16mem:$seg),
387              "verw\t$seg", [], IIC_VERW_REG>, TB;
388} // SchedRW
389
390//===----------------------------------------------------------------------===//
391// Descriptor-table support instructions
392
393let SchedRW = [WriteSystem] in {
394def SGDT16m : I<0x01, MRM0m, (outs opaque48mem:$dst), (ins),
395              "sgdt{w}\t$dst", [], IIC_SGDT>, TB, OpSize16, Requires<[Not64BitMode]>;
396def SGDT32m : I<0x01, MRM0m, (outs opaque48mem:$dst), (ins),
397              "sgdt{l}\t$dst", [], IIC_SGDT>, OpSize32, TB, Requires <[Not64BitMode]>;
398def SGDT64m : I<0x01, MRM0m, (outs opaque80mem:$dst), (ins),
399              "sgdt{q}\t$dst", [], IIC_SGDT>, TB, Requires <[In64BitMode]>;
400def SIDT16m : I<0x01, MRM1m, (outs opaque48mem:$dst), (ins),
401              "sidt{w}\t$dst", [], IIC_SIDT>, TB, OpSize16, Requires<[Not64BitMode]>;
402def SIDT32m : I<0x01, MRM1m, (outs opaque48mem:$dst), (ins),
403              "sidt{l}\t$dst", []>, OpSize32, TB, Requires <[Not64BitMode]>;
404def SIDT64m : I<0x01, MRM1m, (outs opaque80mem:$dst), (ins),
405              "sidt{q}\t$dst", []>, TB, Requires <[In64BitMode]>;
406def SLDT16r : I<0x00, MRM0r, (outs GR16:$dst), (ins),
407                "sldt{w}\t$dst", [], IIC_SLDT>, TB, OpSize16;
408def SLDT16m : I<0x00, MRM0m, (outs i16mem:$dst), (ins),
409                "sldt{w}\t$dst", [], IIC_SLDT>, TB;
410def SLDT32r : I<0x00, MRM0r, (outs GR32:$dst), (ins),
411                "sldt{l}\t$dst", [], IIC_SLDT>, OpSize32, TB;
412
413// LLDT is not interpreted specially in 64-bit mode because there is no sign
414//   extension.
415def SLDT64r : RI<0x00, MRM0r, (outs GR64:$dst), (ins),
416                 "sldt{q}\t$dst", [], IIC_SLDT>, TB;
417def SLDT64m : RI<0x00, MRM0m, (outs i16mem:$dst), (ins),
418                 "sldt{q}\t$dst", [], IIC_SLDT>, TB;
419
420def LGDT16m : I<0x01, MRM2m, (outs), (ins opaque48mem:$src),
421              "lgdt{w}\t$src", [], IIC_LGDT>, TB, OpSize16, Requires<[Not64BitMode]>;
422def LGDT32m : I<0x01, MRM2m, (outs), (ins opaque48mem:$src),
423              "lgdt{l}\t$src", [], IIC_LGDT>, OpSize32, TB, Requires<[Not64BitMode]>;
424def LGDT64m : I<0x01, MRM2m, (outs), (ins opaque80mem:$src),
425              "lgdt{q}\t$src", [], IIC_LGDT>, TB, Requires<[In64BitMode]>;
426def LIDT16m : I<0x01, MRM3m, (outs), (ins opaque48mem:$src),
427              "lidt{w}\t$src", [], IIC_LIDT>, TB, OpSize16, Requires<[Not64BitMode]>;
428def LIDT32m : I<0x01, MRM3m, (outs), (ins opaque48mem:$src),
429              "lidt{l}\t$src", [], IIC_LIDT>, OpSize32, TB, Requires<[Not64BitMode]>;
430def LIDT64m : I<0x01, MRM3m, (outs), (ins opaque80mem:$src),
431              "lidt{q}\t$src", [], IIC_LIDT>, TB, Requires<[In64BitMode]>;
432def LLDT16r : I<0x00, MRM2r, (outs), (ins GR16:$src),
433                "lldt{w}\t$src", [], IIC_LLDT_REG>, TB;
434def LLDT16m : I<0x00, MRM2m, (outs), (ins i16mem:$src),
435                "lldt{w}\t$src", [], IIC_LLDT_MEM>, TB;
436} // SchedRW
437
438//===----------------------------------------------------------------------===//
439// Specialized register support
440let SchedRW = [WriteSystem] in {
441let Uses = [EAX, ECX, EDX] in
442def WRMSR : I<0x30, RawFrm, (outs), (ins), "wrmsr", [], IIC_WRMSR>, TB;
443let Defs = [EAX, EDX], Uses = [ECX] in
444def RDMSR : I<0x32, RawFrm, (outs), (ins), "rdmsr", [], IIC_RDMSR>, TB;
445
446let Defs = [RAX, RDX], Uses = [ECX] in
447  def RDPMC : I<0x33, RawFrm, (outs), (ins), "rdpmc", [(X86rdpmc)], IIC_RDPMC>,
448              TB;
449
450def SMSW16r : I<0x01, MRM4r, (outs GR16:$dst), (ins),
451                "smsw{w}\t$dst", [], IIC_SMSW>, OpSize16, TB;
452def SMSW32r : I<0x01, MRM4r, (outs GR32:$dst), (ins),
453                "smsw{l}\t$dst", [], IIC_SMSW>, OpSize32, TB;
454// no m form encodable; use SMSW16m
455def SMSW64r : RI<0x01, MRM4r, (outs GR64:$dst), (ins),
456                 "smsw{q}\t$dst", [], IIC_SMSW>, TB;
457
458// For memory operands, there is only a 16-bit form
459def SMSW16m : I<0x01, MRM4m, (outs i16mem:$dst), (ins),
460                "smsw{w}\t$dst", [], IIC_SMSW>, TB;
461
462def LMSW16r : I<0x01, MRM6r, (outs), (ins GR16:$src),
463                "lmsw{w}\t$src", [], IIC_LMSW_MEM>, TB;
464def LMSW16m : I<0x01, MRM6m, (outs), (ins i16mem:$src),
465                "lmsw{w}\t$src", [], IIC_LMSW_REG>, TB;
466
467let Defs = [EAX, EBX, ECX, EDX], Uses = [EAX, ECX] in
468  def CPUID : I<0xA2, RawFrm, (outs), (ins), "cpuid", [], IIC_CPUID>, TB;
469} // SchedRW
470
471//===----------------------------------------------------------------------===//
472// Cache instructions
473let SchedRW = [WriteSystem] in {
474def INVD : I<0x08, RawFrm, (outs), (ins), "invd", [], IIC_INVD>, TB;
475def WBINVD : I<0x09, RawFrm, (outs), (ins), "wbinvd", [], IIC_INVD>, TB;
476} // SchedRW
477
478//===----------------------------------------------------------------------===//
479// XSAVE instructions
480let SchedRW = [WriteSystem] in {
481let Defs = [EDX, EAX], Uses = [ECX] in
482  def XGETBV : I<0x01, MRM_D0, (outs), (ins), "xgetbv", []>, TB;
483
484let Uses = [EDX, EAX, ECX] in
485  def XSETBV : I<0x01, MRM_D1, (outs), (ins), "xsetbv", []>, TB;
486
487let Uses = [RDX, RAX] in {
488  def XSAVE : I<0xAE, MRM4m, (outs opaque512mem:$dst), (ins),
489               "xsave\t$dst", []>, TB;
490  def XSAVE64 : RI<0xAE, MRM4m, (outs opaque512mem:$dst), (ins),
491                 "xsave64\t$dst", []>, TB, Requires<[In64BitMode]>;
492  def XRSTOR : I<0xAE, MRM5m, (outs), (ins opaque512mem:$dst),
493               "xrstor\t$dst", []>, TB;
494  def XRSTOR64 : RI<0xAE, MRM5m, (outs), (ins opaque512mem:$dst),
495                 "xrstor64\t$dst", []>, TB, Requires<[In64BitMode]>;
496  def XSAVEOPT : I<0xAE, MRM6m, (outs opaque512mem:$dst), (ins),
497                  "xsaveopt\t$dst", []>, PS;
498  def XSAVEOPT64 : RI<0xAE, MRM6m, (outs opaque512mem:$dst), (ins),
499                    "xsaveopt64\t$dst", []>, PS, Requires<[In64BitMode]>;
500
501  def XRSTORS : I<0xC7, MRM3m, (outs), (ins opaque512mem:$dst),
502                "xrstors\t$dst", []>, TB;
503  def XRSTORS64 : RI<0xC7, MRM3m, (outs), (ins opaque512mem:$dst),
504                  "xrstors64\t$dst", []>, TB, Requires<[In64BitMode]>;
505  def XSAVEC : I<0xC7, MRM4m, (outs opaque512mem:$dst), (ins),
506                "xsavec\t$dst", []>, TB;
507  def XSAVEC64 : RI<0xC7, MRM4m, (outs opaque512mem:$dst), (ins),
508                  "xsavec64\t$dst", []>, TB, Requires<[In64BitMode]>;
509  def XSAVES : I<0xC7, MRM5m, (outs opaque512mem:$dst), (ins),
510                "xsaves\t$dst", []>, TB;
511  def XSAVES64 : RI<0xC7, MRM5m, (outs opaque512mem:$dst), (ins),
512                  "xsaves64\t$dst", []>, TB, Requires<[In64BitMode]>;
513}
514} // SchedRW
515
516//===----------------------------------------------------------------------===//
517// VIA PadLock crypto instructions
518let Defs = [RAX, RDI], Uses = [RDX, RDI] in
519  def XSTORE : I<0xa7, MRM_C0, (outs), (ins), "xstore", []>, TB;
520
521def : InstAlias<"xstorerng", (XSTORE)>;
522
523let Defs = [RSI, RDI], Uses = [RBX, RDX, RSI, RDI] in {
524  def XCRYPTECB : I<0xa7, MRM_C8, (outs), (ins), "xcryptecb", []>, TB;
525  def XCRYPTCBC : I<0xa7, MRM_D0, (outs), (ins), "xcryptcbc", []>, TB;
526  def XCRYPTCTR : I<0xa7, MRM_D8, (outs), (ins), "xcryptctr", []>, TB;
527  def XCRYPTCFB : I<0xa7, MRM_E0, (outs), (ins), "xcryptcfb", []>, TB;
528  def XCRYPTOFB : I<0xa7, MRM_E8, (outs), (ins), "xcryptofb", []>, TB;
529}
530
531let Defs = [RAX, RSI, RDI], Uses = [RAX, RSI, RDI] in {
532  def XSHA1 : I<0xa6, MRM_C8, (outs), (ins), "xsha1", []>, TB;
533  def XSHA256 : I<0xa6, MRM_D0, (outs), (ins), "xsha256", []>, TB;
534}
535let Defs = [RAX, RDX, RSI], Uses = [RAX, RSI] in
536  def MONTMUL : I<0xa6, MRM_C0, (outs), (ins), "montmul", []>, TB;
537
538//===----------------------------------------------------------------------===//
539// FS/GS Base Instructions
540let Predicates = [HasFSGSBase, In64BitMode] in {
541  def RDFSBASE : I<0xAE, MRM0r, (outs GR32:$dst), (ins),
542                   "rdfsbase{l}\t$dst",
543                   [(set GR32:$dst, (int_x86_rdfsbase_32))]>, XS;
544  def RDFSBASE64 : RI<0xAE, MRM0r, (outs GR64:$dst), (ins),
545                     "rdfsbase{q}\t$dst",
546                     [(set GR64:$dst, (int_x86_rdfsbase_64))]>, XS;
547  def RDGSBASE : I<0xAE, MRM1r, (outs GR32:$dst), (ins),
548                   "rdgsbase{l}\t$dst",
549                   [(set GR32:$dst, (int_x86_rdgsbase_32))]>, XS;
550  def RDGSBASE64 : RI<0xAE, MRM1r, (outs GR64:$dst), (ins),
551                     "rdgsbase{q}\t$dst",
552                     [(set GR64:$dst, (int_x86_rdgsbase_64))]>, XS;
553  def WRFSBASE : I<0xAE, MRM2r, (outs), (ins GR32:$src),
554                   "wrfsbase{l}\t$src",
555                   [(int_x86_wrfsbase_32 GR32:$src)]>, XS;
556  def WRFSBASE64 : RI<0xAE, MRM2r, (outs), (ins GR64:$src),
557                      "wrfsbase{q}\t$src",
558                      [(int_x86_wrfsbase_64 GR64:$src)]>, XS;
559  def WRGSBASE : I<0xAE, MRM3r, (outs), (ins GR32:$src),
560                   "wrgsbase{l}\t$src",
561                   [(int_x86_wrgsbase_32 GR32:$src)]>, XS;
562  def WRGSBASE64 : RI<0xAE, MRM3r, (outs), (ins GR64:$src),
563                      "wrgsbase{q}\t$src",
564                      [(int_x86_wrgsbase_64 GR64:$src)]>, XS;
565}
566
567//===----------------------------------------------------------------------===//
568// INVPCID Instruction
569def INVPCID32 : I<0x82, MRMSrcMem, (outs), (ins GR32:$src1, i128mem:$src2),
570                "invpcid\t{$src2, $src1|$src1, $src2}", []>, T8PD,
571                Requires<[Not64BitMode]>;
572def INVPCID64 : I<0x82, MRMSrcMem, (outs), (ins GR64:$src1, i128mem:$src2),
573                "invpcid\t{$src2, $src1|$src1, $src2}", []>, T8PD,
574                Requires<[In64BitMode]>;
575
576//===----------------------------------------------------------------------===//
577// SMAP Instruction
578let Defs = [EFLAGS] in {
579  def CLAC : I<0x01, MRM_CA, (outs), (ins), "clac", []>, TB;
580  def STAC : I<0x01, MRM_CB, (outs), (ins), "stac", []>, TB;
581}
582
583//===----------------------------------------------------------------------===//
584// SMX Instruction
585let Uses = [RAX, RBX, RCX, RDX], Defs = [RAX, RBX, RCX] in {
586  def GETSEC : I<0x37, RawFrm, (outs), (ins), "getsec", []>, TB;
587}
588