X86RegisterInfo.td revision 47622e37215429c20d8278ff57496d840811cc13 
1//===- X86RegisterInfo.td - Describe the X86 Register File ------*- C++ -*-===//
2// 
3//                     The LLVM Compiler Infrastructure
4//
5// This file was developed by the LLVM research group and is distributed under
6// the University of Illinois Open Source License. See LICENSE.TXT for details.
7// 
8//===----------------------------------------------------------------------===//
9//
10// This file describes the X86 Register file, defining the registers themselves,
11// aliases between the registers, and the register classes built out of the
12// registers.
13//
14//===----------------------------------------------------------------------===//
15
16//===----------------------------------------------------------------------===//
17//  Register definitions...
18//
19let Namespace = "X86" in {
20
21  // In the register alias definitions below, we define which registers alias
22  // which others.  We only specify which registers the small registers alias,
23  // because the register file generator is smart enough to figure out that
24  // AL aliases AX if we tell it that AX aliased AL (for example).
25
26  // 32-bit registers
27  def EAX : Register<"EAX">, DwarfRegNum<0>;
28  def ECX : Register<"ECX">, DwarfRegNum<2>;
29  def EDX : Register<"EDX">, DwarfRegNum<1>;
30  def EBX : Register<"EBX">, DwarfRegNum<3>;
31  def ESP : Register<"ESP">, DwarfRegNum<7>;
32  def EBP : Register<"EBP">, DwarfRegNum<6>;
33  def ESI : Register<"ESI">, DwarfRegNum<4>;
34  def EDI : Register<"EDI">, DwarfRegNum<5>;
35  
36  // 16-bit registers
37  def AX : RegisterGroup<"AX", [EAX]>, DwarfRegNum<0>;
38  def CX : RegisterGroup<"CX", [ECX]>, DwarfRegNum<2>;
39  def DX : RegisterGroup<"DX", [EDX]>, DwarfRegNum<1>;
40  def BX : RegisterGroup<"BX", [EBX]>, DwarfRegNum<3>;
41  def SP : RegisterGroup<"SP", [ESP]>, DwarfRegNum<7>;
42  def BP : RegisterGroup<"BP", [EBP]>, DwarfRegNum<6>;
43  def SI : RegisterGroup<"SI", [ESI]>, DwarfRegNum<4>;
44  def DI : RegisterGroup<"DI", [EDI]>, DwarfRegNum<5>;
45  
46  // 8-bit registers
47  def AL : RegisterGroup<"AL", [AX,EAX]>, DwarfRegNum<0>;
48  def CL : RegisterGroup<"CL", [CX,ECX]>, DwarfRegNum<2>;
49  def DL : RegisterGroup<"DL", [DX,EDX]>, DwarfRegNum<1>;
50  def BL : RegisterGroup<"BL", [BX,EBX]>, DwarfRegNum<0>;
51  def AH : RegisterGroup<"AH", [AX,EAX]>, DwarfRegNum<2>;
52  def CH : RegisterGroup<"CH", [CX,ECX]>, DwarfRegNum<2>;
53  def DH : RegisterGroup<"DH", [DX,EDX]>, DwarfRegNum<1>;
54  def BH : RegisterGroup<"BH", [BX,EBX]>, DwarfRegNum<3>;
55
56  // MMX Registers. These are actually aliased to ST0 .. ST7
57  def MM0 : Register<"MM0">, DwarfRegNum<29>;
58  def MM1 : Register<"MM1">, DwarfRegNum<30>;
59  def MM2 : Register<"MM2">, DwarfRegNum<31>;
60  def MM3 : Register<"MM3">, DwarfRegNum<32>;
61  def MM4 : Register<"MM4">, DwarfRegNum<33>;
62  def MM5 : Register<"MM5">, DwarfRegNum<34>;
63  def MM6 : Register<"MM6">, DwarfRegNum<35>;
64  def MM7 : Register<"MM7">, DwarfRegNum<36>;
65  
66  // Pseudo Floating Point registers
67  def FP0 : Register<"FP0">, DwarfRegNum<-1>;
68  def FP1 : Register<"FP1">, DwarfRegNum<-1>;
69  def FP2 : Register<"FP2">, DwarfRegNum<-1>;
70  def FP3 : Register<"FP3">, DwarfRegNum<-1>;
71  def FP4 : Register<"FP4">, DwarfRegNum<-1>;
72  def FP5 : Register<"FP5">, DwarfRegNum<-1>;
73  def FP6 : Register<"FP6">, DwarfRegNum<-1>; 
74
75  // XMM Registers, used by the various SSE instruction set extensions
76  def XMM0: Register<"XMM0">, DwarfRegNum<21>;
77  def XMM1: Register<"XMM1">, DwarfRegNum<22>;
78  def XMM2: Register<"XMM2">, DwarfRegNum<23>;
79  def XMM3: Register<"XMM3">, DwarfRegNum<24>;
80  def XMM4: Register<"XMM4">, DwarfRegNum<25>;
81  def XMM5: Register<"XMM5">, DwarfRegNum<26>;
82  def XMM6: Register<"XMM6">, DwarfRegNum<27>;
83  def XMM7: Register<"XMM7">, DwarfRegNum<28>;
84
85  // Floating point stack registers
86  def ST0 : Register<"ST(0)">, DwarfRegNum<8>;
87  def ST1 : Register<"ST(1)">, DwarfRegNum<9>;
88  def ST2 : Register<"ST(2)">, DwarfRegNum<10>;
89  def ST3 : Register<"ST(3)">, DwarfRegNum<11>;
90  def ST4 : Register<"ST(4)">, DwarfRegNum<12>;
91  def ST5 : Register<"ST(5)">, DwarfRegNum<13>;
92  def ST6 : Register<"ST(6)">, DwarfRegNum<14>;
93  def ST7 : Register<"ST(7)">, DwarfRegNum<15>; 
94}
95
96//===----------------------------------------------------------------------===//
97// Register Class Definitions... now that we have all of the pieces, define the
98// top-level register classes.  The order specified in the register list is
99// implicitly defined to be the register allocation order.
100//
101
102// List AL,CL,DL before AH,CH,DH, as X86 processors often suffer from false
103// dependences between upper and lower parts of the register.  BL and BH are
104// last because they are call clobbered. Both Athlon and P4 chips suffer this
105// issue.
106def R8  : RegisterClass<"X86", [i8],  8, [AL, CL, DL, AH, CH, DH, BL, BH]>;
107
108def R16 : RegisterClass<"X86", [i16], 16, [AX, CX, DX, SI, DI, BX, BP, SP]> {
109  let MethodProtos = [{
110    iterator allocation_order_end(MachineFunction &MF) const;
111  }];
112  let MethodBodies = [{
113    R16Class::iterator
114    R16Class::allocation_order_end(MachineFunction &MF) const {
115      if (hasFP(MF))     // Does the function dedicate EBP to being a frame ptr?
116        return end()-2;  // If so, don't allocate SP or BP
117      else
118        return end()-1;  // If not, just don't allocate SP
119    }
120  }];
121}
122
123def R32 : RegisterClass<"X86", [i32], 32, 
124                        [EAX, ECX, EDX, ESI, EDI, EBX, EBP, ESP]> {
125  let MethodProtos = [{
126    iterator allocation_order_end(MachineFunction &MF) const;
127  }];
128  let MethodBodies = [{
129    R32Class::iterator
130    R32Class::allocation_order_end(MachineFunction &MF) const {
131      if (hasFP(MF))     // Does the function dedicate EBP to being a frame ptr?
132        return end()-2;  // If so, don't allocate ESP or EBP
133      else
134        return end()-1;  // If not, just don't allocate ESP
135    }
136  }];
137}
138
139// Scalar SSE2 floating point registers.
140def FR32 : RegisterClass<"X86", [f32], 32,
141                         [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7]>;
142def FR64 : RegisterClass<"X86", [f64], 64,
143                         [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7]>;
144
145// FIXME: This sets up the floating point register files as though they are f64
146// values, though they really are f80 values.  This will cause us to spill
147// values as 64-bit quantities instead of 80-bit quantities, which is much much
148// faster on common hardware.  In reality, this should be controlled by a
149// command line option or something.
150
151def RFP : RegisterClass<"X86", [f64], 32, [FP0, FP1, FP2, FP3, FP4, FP5, FP6]>;
152
153// Floating point stack registers (these are not allocatable by the
154// register allocator - the floating point stackifier is responsible
155// for transforming FPn allocations to STn registers)
156def RST : RegisterClass<"X86", [f64], 32,
157                        [ST0, ST1, ST2, ST3, ST4, ST5, ST6, ST7]> {
158    let MethodProtos = [{
159    iterator allocation_order_end(MachineFunction &MF) const;
160  }];
161  let MethodBodies = [{
162    RSTClass::iterator
163    RSTClass::allocation_order_end(MachineFunction &MF) const {
164      return begin();
165    }
166  }];
167}
168
169// Generic vector registers: VR64 and VR128.
170def VR64  : RegisterClass<"X86", [v8i8, v4i16, v2i32], 64,
171                          [MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7]>;
172def VR128 : RegisterClass<"X86", [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],128,
173                         [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7]>;
174