| ebe69fe11e48d322045d5949c83283927a0d790b |
|
23-Mar-2015 |
Stephen Hines <srhines@google.com> |
Update aosp/master LLVM for rebase to r230699.
Change-Id: I2b5be30509658cb8266be782de0ab24f9099f9b9
/external/llvm/lib/Target/X86/X86RegisterInfo.td
|
| 37ed9c199ca639565f6ce88105f9e39e898d82d0 |
|
01-Dec-2014 |
Stephen Hines <srhines@google.com> |
Update aosp/master LLVM for rebase to r222494.
Change-Id: Ic787f5e0124df789bd26f3f24680f45e678eef2d
/external/llvm/lib/Target/X86/X86RegisterInfo.td
|
| 36b56886974eae4f9c5ebc96befd3e7bfe5de338 |
|
24-Apr-2014 |
Stephen Hines <srhines@google.com> |
Update to LLVM 3.5a.
Change-Id: Ifadecab779f128e62e430c2b4f6ddd84953ed617
/external/llvm/lib/Target/X86/X86RegisterInfo.td
|
| e3809eed34f000581a464689596eefde2a6d1f24 |
|
24-Jul-2013 |
Elena Demikhovsky <elena.demikhovsky@intel.com> |
I'm starting to commit KNL backend. I'll push patches one-by-one. This patch includes support for the extended register set XMM16-31, YMM16-31, ZMM0-31.
The full ISA you can see here: http://software.intel.com/en-us/intel-isa-extensions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187030 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86RegisterInfo.td
|
| b8ce45752b0b2f149d43a51f6a5a849140f378fe |
|
03-Jun-2013 |
Ahmed Bougacha <ahmed.bougacha@gmail.com> |
X86: sub_xmm registers are 128 bits wide.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183103 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86RegisterInfo.td
|
| bed23081860275c79137f65d592920e7991b8198 |
|
31-May-2013 |
Ahmed Bougacha <ahmed.bougacha@gmail.com> |
Add a way to define the bit range covered by a SubRegIndex.
NOTE: If this broke your out-of-tree backend, in *RegisterInfo.td, change
the instances of SubRegIndex that have a comps template arg to use the
ComposedSubRegIndex class instead.
In TableGen land, this adds Size and Offset attributes to SubRegIndex,
and the ComposedSubRegIndex class, for which the Size and Offset are
computed by TableGen. This also adds an accessor in MCRegisterInfo, and
Size/Offsets for the X86 and ARM subreg indices.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183020 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86RegisterInfo.td
|
| 7abf67a092c0a75d6d1631766d6a8ef14e38d526 |
|
04-Oct-2012 |
Michael Liao <michael.liao@intel.com> |
Add register encoding support in X86 backend
- Add 'HwEncoding' for X86 registers and call getEncodingValue() to
retrieve their encoding values.
- This's the first step to adopt new scheme. Furthur revising is onging.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165241 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86RegisterInfo.td
|
| 3ba90d9c0ec6c669174431ff6b4f504a582559c4 |
|
27-Jul-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Remove the X86 sub_ss and sub_sd sub-register indexes completely.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160833 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86RegisterInfo.td
|
| 338607ae0ddab00e197222e769748e2e0c0b4e18 |
|
04-May-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Remove the SubRegClasses field from RegisterClass descriptions.
This information in now computed by TableGen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156152 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86RegisterInfo.td
|
| 17c836c4b51a14f07a5d5442cf2e984474a8f57d |
|
27-Apr-2012 |
Benjamin Kramer <benny.kra@googlemail.com> |
X86: Don't emit conditional floating point moves on when targeting pre-pentiumpro architectures.
* Model FPSW (the FPU status word) as a register.
* Add ISel patterns for the FUCOM*, FNSTSW and SAHF instructions.
* During Legalize/Lowering, build a node sequence to transfer the comparison
result from FPSW into EFLAGS. If you're wondering about the right-shift: That's
an implicit sub-register extraction (%ax -> %ah) which is handled later on by
the instruction selector.
Fixes PR6679. Patch by Christoph Erhardt!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155704 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86RegisterInfo.td
|
| 8b0a3f2df96dae0a6ee4fb240f7190c5bc20e0b7 |
|
16-Feb-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Remove the YMM_HI_6_15 hack.
Call clobbers are now represented with register mask operands. The
regmask can easily represent the fact that xmm6 is call-preserved while
ymm6 isn't. This is automatically computed by TableGen from the
CalleeSavedRegs containing xmm6.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150709 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86RegisterInfo.td
|
| 53fa56e8dc60c8b594f22b888b4fb3c3b0567d82 |
|
26-Jan-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Handle call-clobbered ymm registers on Win64.
The Win64 calling convention has xmm6-15 as callee-saved while still
clobbering all ymm registers.
Add a YMM_HI_6_15 pseudo-register that aliases the clobbered part of the
ymm registers, and mark that as call-clobbered. This allows live xmm
registers across calls.
This hack wouldn't be necessary with RegisterMask operands representing
the call clobbers, but they are not quite operational yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149088 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86RegisterInfo.td
|
| 31867660cb81ea2b1d1a6ffa7d09c91acb754a8b |
|
18-Jan-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Add a CoveredBySubRegs property to Register descriptions.
When set, this bit indicates that a register is completely defined by
the value of its sub-registers.
Use the CoveredBySubRegs property to infer which super-registers are
call-preserved given a list of callee-saved registers. For example, the
ARM registers D8-D15 are callee-saved. This now automatically implies
that Q4-Q7 are call-preserved.
Conversely, Win64 callees save XMM6-XMM15, but the corresponding
YMM6-YMM15 registers are not call-preserved because they are not fully
defined by their sub-registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148363 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86RegisterInfo.td
|
| 25f6dfd108801d1dc5877c420ef0dd47131aeda7 |
|
07-Oct-2011 |
Craig Topper <craig.topper@gmail.com> |
Revert part of r141274. Only need to change encoding for xchg %eax, %eax in 64-bit mode. This is because in 64-bit mode xchg %eax, %eax implies zeroing the upper 32-bits of RAX which makes it not a NOP. In 32-bit mode using NOP encoding is fine.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141353 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86RegisterInfo.td
|
| 7ea16b01fad5236cc132cb5fc3e443fcbf70d3b8 |
|
06-Oct-2011 |
Craig Topper <craig.topper@gmail.com> |
Fix assembling of xchg %eax, %eax to not use the NOP encoding of 0x90. This was done by creating a new register group that excludes AX registers. Fixes PR10345. Also added aliases for flipping the order of the operands of xchg <reg>, %eax.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141274 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86RegisterInfo.td
|
| 11bbb2003a4b435e384e8f515a51af3f43fd4cca |
|
21-Jul-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Add v16i16 type to VR256 class
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135658 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86RegisterInfo.td
|
| 9bbe4d6c004f25bc491e2583cce7bc91891f68c7 |
|
28-Jun-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Clean up the handling of the x87 fp stack to make it more robust.
Drop the FpMov instructions, use plain COPY instead.
Drop the FpSET/GET instruction for accessing fixed stack positions.
Instead use normal COPY to/from ST registers around inline assembly, and
provide a single new FpPOP_RETVAL instruction that can access the return
value(s) from a call. This is still necessary since you cannot tell from
the CALL instruction alone if it returns anything on the FP stack. Teach
fast isel to use this.
This provides a much more robust way of handling fixed stack registers -
we can tolerate arbitrary FP stack instructions inserted around calls
and inline assembly. Live range splitting could sometimes break x87 code
by inserting spill code in unfortunate places.
As a bonus we handle floating point inline assembly correctly now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134018 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86RegisterInfo.td
|
| e8c38ca3b591baeb2aab1f8a405e1bece17f5269 |
|
18-Jun-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Switch x86 to using AltOrders instead of MethodBodies.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133325 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86RegisterInfo.td
|
| f28987b76e758b5f2fcc2c5d2c8e073df54ca91e |
|
16-Jun-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Use set operations instead of plain lists to enumerate register classes.
This simplifies many of the target description files since it is common
for register classes to be related or contain sequences of numbered
registers.
I have verified that this doesn't change the files generated by TableGen
for ARM and X86. It alters the allocation order of MBlaze GPR and Mips
FGR32 registers, but I believe the change is benign.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133105 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86RegisterInfo.td
|
| 2a9d1ca9c244aeac98044a5fc9a081ff3df7b2ff |
|
09-Jun-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Remove custom allocation order boilerplate that is no longer needed.
The register allocators automatically filter out reserved registers and
place the callee saved registers last in the allocation order, so custom
methods are no longer necessary just for that.
Some targets still use custom allocation orders:
ARM/Thumb: The high registers are removed from GPR in thumb mode. The
NEON allocation orders prefer to use non-VFP2 registers first.
X86: The GR8 classes omit AH-DH in x86-64 mode to avoid REX trouble.
SystemZ: Some of the allocation orders are omitting R12 aliases without
explanation. I don't understand this target well enough to fix that. It
looks like all the boilerplate could be removed by reserving the right
registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132781 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86RegisterInfo.td
|
| 4f3fb6d08be511a277f92279e803ae6e95b00126 |
|
03-Jun-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Flag unallocatable register classes instead of giving them empty
allocation orders.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132509 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86RegisterInfo.td
|
| 7a067cc6e0b980b186696c13fe847929fbc0d373 |
|
30-May-2011 |
Rafael Espindola <rafael.espindola@gmail.com> |
Introduce the DwarfRegAlias class for declaring that two registers have the
same dwarf number. This will be used for creating a dwarf number to register
mapping.
The only case that needs this so far is the XMM/YMM registers that unfortunately
do have the same numbers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132314 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86RegisterInfo.td
|
| e99f75a300abc89b798c5ca491cba13940d52702 |
|
30-May-2011 |
Rafael Espindola <rafael.espindola@gmail.com> |
Mark the 32 bit registers as invalid in 64 bit mode. In 64 bit mode they are
subregisters of the 64 bit ones.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132313 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86RegisterInfo.td
|
| 36ea4f0206e7c4265e588b41451bdeffbbdf1711 |
|
28-May-2011 |
Rafael Espindola <rafael.espindola@gmail.com> |
Add 132187 back now that the real problem is fixed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132238 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86RegisterInfo.td
|
| 157371f376f817b6cbe48f51a006ece2186a5a4c |
|
28-May-2011 |
Rafael Espindola <rafael.espindola@gmail.com> |
It looks like 132187 might have broken the llvm-gcc bootstrap. Revert while I check.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132230 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86RegisterInfo.td
|
| f5e771db37bb4c63f81f902a1d21269c4bd45236 |
|
28-May-2011 |
Cameron Zwarich <zwarich@apple.com> |
Add a GR32_NOREX_NOSP register class and fix a bug where getMatchingSuperRegClass()
was saying that the matching superregister class of GR32_NOREX in GR64_NOREX_NOSP
is GR64_NOREX, which drops the NOSP constraint. This fixes PR10032.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132225 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86RegisterInfo.td
|
| 11f6cc96bf794c7ede7bf8e24805f4187b24c549 |
|
27-May-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Delete MethodBodies that only filtered reserved registers.
The register allocators know to filter reserved registers from the allocation
orders, so we don't need all of this boilerplate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132199 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86RegisterInfo.td
|
| 81e193cc1fad7ef13bb2d2043de011cac591894c |
|
27-May-2011 |
Rafael Espindola <rafael.espindola@gmail.com> |
Remove dwarf numbers from subregs. We should use DW_OP_bit_piece to
refer to them.
I tested this with both check-all and the gdb testsuite.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132187 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86RegisterInfo.td
|
| 37fed38ec155705803250273467d5bec66e0dcd5 |
|
21-May-2011 |
Cameron Zwarich <zwarich@apple.com> |
Fix PR9978 by adding RIP to GR64_TC so it can be used as an address in PIC code. It
is already in GR64 for the same reasons. Since it isn't allocatable it can't cause
any problems.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131787 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86RegisterInfo.td
|
| 6bfba2e5af163442a1c6b11fe14aa9df9101cfd7 |
|
20-Apr-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Prefer cheap registers for busy live ranges.
On the x86-64 and thumb2 targets, some registers are more expensive to encode
than others in the same register class.
Add a CostPerUse field to the TableGen register description, and make it
available from TRI->getCostPerUse. This represents the cost of a REX prefix or a
32-bit instruction encoding required by choosing a high register.
Teach the greedy register allocator to prefer cheap registers for busy live
ranges (as indicated by spill weight).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129864 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86RegisterInfo.td
|
| 7754f85885f8a961cb403ef13ab39583492d2b1e |
|
26-Jan-2011 |
NAKAMURA Takumi <geek4civic@gmail.com> |
Target/X86: Tweak win64's tailcall.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124272 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86RegisterInfo.td
|
| e5fffe9c3fa402cb5d5167327783f82b86f52b8f |
|
26-Jan-2011 |
NAKAMURA Takumi <geek4civic@gmail.com> |
Fix whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124270 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86RegisterInfo.td
|
| 16c29b5f285f375be53dabaa73e3e91107485fe4 |
|
10-Jan-2011 |
Anton Korobeynikov <asl@math.spbu.ru> |
Rename TargetFrameInfo into TargetFrameLowering. Also, put couple of FIXMEs and fixes here and there.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123170 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86RegisterInfo.td
|
| d0c38176690e9602a93a20a43f1bd084564a8116 |
|
18-Nov-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
Move hasFP() and few related hooks to TargetFrameInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119740 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86RegisterInfo.td
|
| b0269cd2c8d8512ea156a6c6df798faa6c76145c |
|
14-Nov-2010 |
Chris Lattner <sabre@nondot.org> |
random acts of tidiness.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119049 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86RegisterInfo.td
|
| 417b54354b3fcccb4f5919b8d2d9dcd8bba50069 |
|
06-Oct-2010 |
Chris Lattner <sabre@nondot.org> |
lets go all meta and define new X86 type wrappers that declare the associated
gunk that goes along with an MVT (e.g. reg class, preferred load operation,
memory operand)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115727 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86RegisterInfo.td
|
| 20b2499a7c407733a79e32b84a9d44e57eb89684 |
|
06-Oct-2010 |
Chris Lattner <sabre@nondot.org> |
associate the instruction suffix letter with the integer gpr
register class, and use this to simplify use of BinOpRR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115716 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86RegisterInfo.td
|
| 0488fb649a56b7fc89a5814df5308813f9e5a85d |
|
01-Oct-2010 |
Dale Johannesen <dalej@apple.com> |
Massive rewrite of MMX:
The x86_mmx type is used for MMX intrinsics, parameters and
return values where these use MMX registers, and is also
supported in load, store, and bitcast.
Only the above operations generate MMX instructions, and optimizations
do not operate on or produce MMX intrinsics.
MMX-sized vectors <2 x i32> etc. are lowered to XMM or split into
smaller pieces. Optimizations may occur on these forms and the
result casted back to x86_mmx, provided the result feeds into a
previous existing x86_mmx operation.
The point of all this is prevent optimizations from introducing
MMX operations, which is unsafe due to the EMMS problem.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115243 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86RegisterInfo.td
|
| bc57c6db4a3a1f5df4450d8dbb100e1eb6944c28 |
|
22-Sep-2010 |
Chris Lattner <sabre@nondot.org> |
fix rdar://8456412 - llvm-mc crash in encoder on "mov %rdx, %cr8"
Teaching the code generator about CR8-15, how to rex them up, etc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114533 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86RegisterInfo.td
|
| 63b1dbaadd4bb70a6fcb84db880fc34d72b9a956 |
|
31-Aug-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Make %EFLAGS unallocatable.
No CCR virtual registers should exist, and %EFLAGS is used in ways that can
surprise RegAllocFast.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112650 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86RegisterInfo.td
|
| 3c8e1bee6399e829eda801a32158c1f52d2733ad |
|
24-Jul-2010 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Support x86 "eiz" and "riz" pseudo index registers in the assembler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109295 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86RegisterInfo.td
|
| 94143ee6254944a26adba2200037328c2c8ef289 |
|
20-Jul-2010 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Add 256-bit vaddsub, vhadd, vhsub, vblend and vdpp instructions!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108769 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86RegisterInfo.td
|
| 58dbf3784d3daff5f1e5e08363aee8290d1a5dc1 |
|
09-Jul-2010 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Declare YMM subregisters in the right way! Thanks Jakob
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108022 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86RegisterInfo.td
|
| e86b01c153ba52307ecb6e7513ec33f57caedfdd |
|
09-Jul-2010 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Start the support for AVX instructions with 256-bit %ymm registers. A couple of
notes:
- The instructions are being added with dummy placeholder patterns using some 256
specifiers, this is not meant to work now, but since there are some multiclasses
generic enough to accept them, when we go for codegen, the stuff will be already
there.
- Add VEX encoding bits to support YMM
- Add MOVUPS and MOVAPS in the first round
- Use "Y" as suffix for those Instructions: MOVUPSYrr, ...
- All AVX instructions in X86InstrSSE.td will move soon to a new X86InstrAVX
file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107996 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86RegisterInfo.td
|
| a5b412581c09f634eb2983965fbbe8790ae4817f |
|
05-Jul-2010 |
Chris Lattner <sabre@nondot.org> |
rip out even more sporadic v2f32 support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107610 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86RegisterInfo.td
|
| ca561ffcf320e9dbfafcac5efcee81471f3259c3 |
|
26-May-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Replace the SubRegSet tablegen class with a less error-prone mechanism.
A Register with subregisters must also provide SubRegIndices for adressing the
subregisters. TableGen automatically inherits indices for sub-subregisters to
minimize typing.
CompositeIndices may be specified for the weirder cases such as the XMM sub_sd
index that returns the same register, and ARM NEON Q registers where both D
subregs have ssub_0 and ssub_1 sub-subregs.
It is now required that all subregisters are named by an index, and a future
patch will also require inherited subregisters to be named. This is necessary to
allow composite subregister indices to be reduced to a single index.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104704 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86RegisterInfo.td
|
| b555609e73f5091bf8180c0875fb1fa6c5ad0e7a |
|
26-May-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Revert "Replace the SubRegSet tablegen class with a less error-prone mechanism."
This reverts commit 104654.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104660 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86RegisterInfo.td
|
| 6a45d681e53a99b4c4f63e0b1664626a596a8151 |
|
26-May-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Replace the SubRegSet tablegen class with a less error-prone mechanism.
A Register with subregisters must also provide SubRegIndices for adressing the
subregisters. TableGen automatically inherits indices for sub-subregisters to
minimize typing.
CompositeIndices may be specified for the weirder cases such as the XMM sub_sd
index that returns the same register, and ARM NEON Q registers where both D
subregs have ssub_0 and ssub_1 sub-subregs.
It is now required that all subregisters are named by an index, and a future
patch will also require inherited subregisters to be named. This is necessary to
allow composite subregister indices to be reduced to a single index.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104654 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86RegisterInfo.td
|
| 4fda9670f0a9cd448d1905ab669421316b8864c5 |
|
25-May-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Remove NumberHack entirely.
SubRegIndex instances are now numbered uniquely the same way Register instances
are - in lexicographical order by name.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104627 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86RegisterInfo.td
|
| 33276d95ef4191663d8e6b972481f9faf37ce541 |
|
25-May-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Switch SubRegSet to using symbolic SubRegIndices
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104571 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86RegisterInfo.td
|
| 09bc0298650c76db1a06e20ca84c1dcb34071600 |
|
24-May-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Replace the tablegen RegisterClass field SubRegClassList with an alist-like data
structure that represents a mapping without any dependencies on SubRegIndex
numbering.
This brings us closer to being able to remove the explicit SubRegIndex
numbering, and it is now possible to specify any mapping without inventing
*_INVALID register classes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104563 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86RegisterInfo.td
|
| 3458e9e4dfc8689179a74e954aad78d3a4b564ff |
|
24-May-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Rename X86 subregister indices to something shorter.
Use the tablegen-produced enums.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104493 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86RegisterInfo.td
|
| 73ea7bf4509663267317ec3911aac00ca35a2f2c |
|
24-May-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Add the SubRegIndex TableGen class.
This is the beginning of purely symbolic subregister indices, but we need a bit
of jiggling before the explicit numeric indices can be completely removed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104492 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86RegisterInfo.td
|
| 1a8b789a4b8290d263c1c75411788ca45bae3230 |
|
06-May-2010 |
Sean Callanan <scallanan@apple.com> |
Eliminated the classification of control registers into %ecr_
and %rcr_, leaving just %cr_ which is what people expect.
Updated the disassembler to support this unified register set.
Added a testcase to verify that the registers continue to be
decoded correctly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103196 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86RegisterInfo.td
|
| fa85eb62378900a884a7eb4933a9deb6513d26ab |
|
06-Apr-2010 |
Jim Grosbach <grosbach@apple.com> |
Fix PR6696 and PR6663
When a frame pointer is not otherwise required, and dynamic stack alignment
is necessary solely due to the spilling of a register with larger alignment
requirements than the default stack alignment, the frame pointer can be both
used as a general purpose register and a frame pointer. That goes poorly, for
obvious reasons. This patch brings back a bit of old logic for identifying
the use of such registers and conservatively reserves the frame pointer
during register allocation in such cases.
For now, implement for X86 only since it's 32-bit linux which is hitting this,
and we want a targeted fix for 2.7. As a follow-on, this will be expanded
to handle other targets, as theoretically the problem could arise elsewhere
as well.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100559 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86RegisterInfo.td
|
| f48ef0365545b6160836e3f4b4a210d1e21f1881 |
|
14-Mar-2010 |
Evan Cheng <evan.cheng@apple.com> |
Do not force indirect tailcall through fixed registers: eax, r11. Add support to allow loads to be folded to tail call instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98465 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86RegisterInfo.td
|
| 874cadaf210d4ab05eadc64a41228df0f5078eb7 |
|
28-Feb-2010 |
Dan Gohman <gohman@apple.com> |
Implement XMM subregs.
Extracting the low element of a vector is now done with EXTRACT_SUBREG,
and the zero-extension performed by load movss is now modeled with
SUBREG_TO_REG, and so on.
Register-to-register movss and movsd are no longer considered copies;
they are two-address instructions which insert a scalar into a vector.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97354 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86RegisterInfo.td
|
| ea32d8f46514f2c9168505793621ea8f1ed54be5 |
|
26-Jan-2010 |
Dan Gohman <gohman@apple.com> |
Remove SIL, DIL, and BPL from the GR8_NOREX allocation order also.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94560 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86RegisterInfo.td
|
| 369d4b4c2ebf3475e397d754115aafe7e12c797f |
|
26-Jan-2010 |
Dan Gohman <gohman@apple.com> |
SIL, DIL, BPL, and SPL require a REX prefix.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94558 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86RegisterInfo.td
|
| 108934c65d4cba18f08ed4fab0cae506c20fd212 |
|
18-Dec-2009 |
Sean Callanan <scallanan@apple.com> |
Instruction fixes, added instructions, and AsmString changes in the
X86 instruction tables.
Also (while I was at it) cleaned up the X86 tables, removing tabs and
80-line violations.
This patch was reviewed by Chris Lattner, but please let me know if
there are any problems.
* X86*.td
Removed tabs and fixed 80-line violations
* X86Instr64bit.td
(IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW)
Added
(CALL, CMOV) Added qualifiers
(JMP) Added PC-relative jump instruction
(POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate
that it is 64-bit only (ambiguous since it has no
REX prefix)
(MOV) Added rr form going the other way, which is encoded
differently
(MOV) Changed immediates to offsets, which is more correct;
also fixed MOV64o64a to have to a 64-bit offset
(MOV) Fixed qualifiers
(MOV) Added debug-register and condition-register moves
(MOVZX) Added more forms
(ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which
(as with MOV) are encoded differently
(ROL) Made REX.W required
(BT) Uncommented mr form for disassembly only
(CVT__2__) Added several missing non-intrinsic forms
(LXADD, XCHG) Reordered operands to make more sense for
MRMSrcMem
(XCHG) Added register-to-register forms
(XADD, CMPXCHG, XCHG) Added non-locked forms
* X86InstrSSE.td
(CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ)
Added
* X86InstrFPStack.td
(COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP,
FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X,
FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM,
FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE,
FXRSTOR)
Added
(FCOM, FCOMP) Added qualifiers
(FSTENV, FSAVE, FSTSW) Fixed opcode names
(FNSTSW) Added implicit register operand
* X86InstrInfo.td
(opaque512mem) Added for FXSAVE/FXRSTOR
(offset8, offset16, offset32, offset64) Added for MOV
(NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR,
LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS,
LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT,
LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC,
CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC,
SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL,
VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD,
VMWRITE, VMXOFF, VMXON) Added
(NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier
(JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL,
JGE, JLE, JG, JCXZ) Added 32-bit forms
(MOV) Changed some immediate forms to offset forms
(MOV) Added reversed reg-reg forms, which are encoded
differently
(MOV) Added debug-register and condition-register moves
(CMOV) Added qualifiers
(AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV
(BT) Uncommented memory-register forms for disassembler
(MOVSX, MOVZX) Added forms
(XCHG, LXADD) Made operand order make sense for MRMSrcMem
(XCHG) Added register-register forms
(XADD, CMPXCHG) Added unlocked forms
* X86InstrMMX.td
(MMX_MOVD, MMV_MOVQ) Added forms
* X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table
change
* X86RegisterInfo.td: Added debug and condition register sets
* x86-64-pic-3.ll: Fixed testcase to reflect call qualifier
* peep-test-3.ll: Fixed testcase to reflect test qualifier
* cmov.ll: Fixed testcase to reflect cmov qualifier
* loop-blocks.ll: Fixed testcase to reflect call qualifier
* x86-64-pic-11.ll: Fixed testcase to reflect call qualifier
* 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call
qualifier
* x86-64-pic-2.ll: Fixed testcase to reflect call qualifier
* live-out-reg-info.ll: Fixed testcase to reflect test qualifier
* tail-opts.ll: Fixed testcase to reflect call qualifiers
* x86-64-pic-10.ll: Fixed testcase to reflect call qualifier
* bss-pagealigned.ll: Fixed testcase to reflect call qualifier
* x86-64-pic-1.ll: Fixed testcase to reflect call qualifier
* widen_load-1.ll: Fixed testcase to reflect call qualifier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91638 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86RegisterInfo.td
|
| 21313bc62f285d89aa0311ab42ad3a108432f4af |
|
05-Oct-2009 |
Dan Gohman <gohman@apple.com> |
Add RIP to GR64_NOREX. This fixed a MachineVerifier error when RIP
is used in an operand which requires GR64_NOREX.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83307 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86RegisterInfo.td
|
| 38fee0edcf36ea5e0541c448edf6cdead2727faf |
|
15-Sep-2009 |
Sean Callanan <scallanan@apple.com> |
Added a new register class for segment registers
to the Intel register table.
Added 16- and 64-bit MOVs to and from the segment
registers to the Intel instruction tables.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81895 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86RegisterInfo.td
|
| 524dab14f4f8f547465250c6ae44cac7414e7e0a |
|
30-Jul-2009 |
Dan Gohman <gohman@apple.com> |
Minor whitespace tidiness.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77602 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86RegisterInfo.td
|
| 68a31c2583dde574f1dce0b6b161754c2e7e28cd |
|
30-Jul-2009 |
Dan Gohman <gohman@apple.com> |
Rename GRAD to GR32_AD, to follow the naming convention of other
classes. And define its SubRegClassList.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77601 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86RegisterInfo.td
|
| a4714e025de720d0fcbaa78ab6c12dc789599233 |
|
30-Jul-2009 |
Dan Gohman <gohman@apple.com> |
Add a new register class to describe operands that can't be SP,
due to x86 encoding restrictions. This is currently off by default
because it may cause code quality regressions. This is for PR4572.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77565 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86RegisterInfo.td
|
| 084d1ba5ad9986947fd1e80afdccc4dce6578f95 |
|
30-Jul-2009 |
Dan Gohman <gohman@apple.com> |
Eliminate a bunch of redundant tables.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77558 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86RegisterInfo.td
|
| 7c5f0c5ce92f6daa2b06970dcab5dfa0405ce911 |
|
30-Jul-2009 |
Dan Gohman <gohman@apple.com> |
Use array_endof instead of doing it manually.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77553 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86RegisterInfo.td
|
| d94c101abb2753e4d3cb7c7f436c7a38de94dc3c |
|
30-Jun-2009 |
David Greene <greened@obbligato.org> |
Add a 256-bit register class and YMM registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74469 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86RegisterInfo.td
|
| c4233af20079b163000ea87ec42cdf3edd0c8016 |
|
26-Jun-2009 |
Chris Lattner <sabre@nondot.org> |
add %rip to the GR64 register class. Lets avoid allocating it to anything though! :)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74328 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86RegisterInfo.td
|
| 4af325d1b4b811277365a20aa6cfc7f719625198 |
|
27-Apr-2009 |
Dan Gohman <gohman@apple.com> |
Rename GR8_ABCD to GR8_ABCD_L and create GR8_ABCD_H, and use these
to precisely describe the h-register subreg register classes.
Thanks to Jakob Stoklund Olesen for spotting this and for the
initial patch!
Also, make getStoreRegOpcode and getLoadRegOpcode aware of the
needs of h registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70211 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86RegisterInfo.td
|
| 6241762c5a8f5e22679ffcd7a592e405e279f0a9 |
|
27-Apr-2009 |
Dan Gohman <gohman@apple.com> |
Rename GR8_, GR16_, GR32_, and GR64_ to GR8_ABCD, GR16_ABCD,
GR32_ABCD, and GR64_ABCD, respectively, to help describe them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70210 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86RegisterInfo.td
|
| aaa1fdb271073893699f3af57f5439dae35a8f59 |
|
15-Apr-2009 |
Dan Gohman <gohman@apple.com> |
Do for GR16_NOREX what r69049 did for GR8_NOREX, to avoid trouble with
the local register allocator.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69115 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86RegisterInfo.td
|
| a2f3703efd159352481cdb7b493bd430fc9c89f4 |
|
15-Apr-2009 |
Dan Gohman <gohman@apple.com> |
GR8_NOREX can contain the H registers, since they don't require
REX prefixes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69108 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86RegisterInfo.td
|
| b3f5bfe37f7d0c2b77bda1530da6d98f5ccb5ae6 |
|
14-Apr-2009 |
Evan Cheng <evan.cheng@apple.com> |
Some of GR8_NOREX registers are only available in 64-bit mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69049 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86RegisterInfo.td
|
| 21e3dfbc86955cf46a362e8ed36b5b73b42961c9 |
|
13-Apr-2009 |
Dan Gohman <gohman@apple.com> |
Implement x86 h-register extract support.
- Add patterns for h-register extract, which avoids a shift and mask,
and in some cases a temporary register.
- Add address-mode matching for turning (X>>(8-n))&(255<<n), where
n is a valid address-mode scale value, into an h-register extract
and a scaled-offset address.
- Replace X86's MOV32to32_ and related instructions with the new
target-independent COPY_TO_SUBREG instruction.
On x86-64 there are complicated constraints on h registers, and
CodeGen doesn't currently provide a high-level way to express all of them,
so they are handled with a bunch of special code. This code currently only
supports extracts where the result is used by a zero-extend or a store,
though these are fairly common.
These transformations are not always beneficial; since there are only
4 h registers, they sometimes require extra move instructions, and
this sometimes increases register pressure because it can force out
values that would otherwise be in one of those registers. However,
this appears to be relatively uncommon.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68962 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86RegisterInfo.td
|
| 3cf9b3e4557322ab88731ee3dfc2d527be5cbc31 |
|
13-Apr-2009 |
Dan Gohman <gohman@apple.com> |
Fix copy+pastos in comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68958 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86RegisterInfo.td
|
| ee30047386d283c488832952487d1e6775bab95f |
|
13-Apr-2009 |
Dan Gohman <gohman@apple.com> |
List the l registers before h registers, for consistency.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68954 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86RegisterInfo.td
|
| 094fad37b90946c91a09eb9270a0dbe800f49d87 |
|
08-Apr-2009 |
Rafael Espindola <rafael.espindola@gmail.com> |
Re-apply 68552.
Tested by bootstrapping llvm-gcc and using that to build llvm.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68645 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86RegisterInfo.td
|
| 044b5344c4a97b3c709a05b9c5f9296656477652 |
|
08-Apr-2009 |
Bill Wendling <isanbard@gmail.com> |
Temporarily revert r68552. This was causing a failure in the self-hosting LLVM
builds.
--- Reverse-merging (from foreign repository) r68552 into '.':
U test/CodeGen/X86/tls8.ll
U test/CodeGen/X86/tls10.ll
U test/CodeGen/X86/tls2.ll
U test/CodeGen/X86/tls6.ll
U lib/Target/X86/X86Instr64bit.td
U lib/Target/X86/X86InstrSSE.td
U lib/Target/X86/X86InstrInfo.td
U lib/Target/X86/X86RegisterInfo.cpp
U lib/Target/X86/X86ISelLowering.cpp
U lib/Target/X86/X86CodeEmitter.cpp
U lib/Target/X86/X86FastISel.cpp
U lib/Target/X86/X86InstrInfo.h
U lib/Target/X86/X86ISelDAGToDAG.cpp
U lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp
U lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.cpp
U lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.h
U lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.h
U lib/Target/X86/X86ISelLowering.h
U lib/Target/X86/X86InstrInfo.cpp
U lib/Target/X86/X86InstrBuilder.h
U lib/Target/X86/X86RegisterInfo.td
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68560 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86RegisterInfo.td
|
| 2a6411bbbdc6a23605fa206e07fc4f99a3d5dff2 |
|
07-Apr-2009 |
Rafael Espindola <rafael.espindola@gmail.com> |
Reduce code duplication on the TLS implementation.
This introduces a small regression on the generated code
quality in the case we are just computing addresses, not
loading values.
Will work on it and on X86-64 support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68552 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86RegisterInfo.td
|
| 599a6a88ce1925a6349ac7af9a9638aad1d832cc |
|
04-Mar-2009 |
Evan Cheng <evan.cheng@apple.com> |
Fix PR3701. 1. X86 target renamed eflags register to flags. This matches what llvm-gcc generates so codegen knows flags register is being clobbered by inline asm. 2. BURR scheduler should also check if inline asm nodes can clobber "live" physical registers. Previously it was only checking target nodes with implicit defs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@65996 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86RegisterInfo.td
|
| d3f184906d341924fbebe9b09e225c624b4e0474 |
|
27-Jan-2009 |
Dan Gohman <gohman@apple.com> |
Reformat the allocation-order arrays to a more conventional style.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63121 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86RegisterInfo.td
|
| be362abe9c2a57f094386329ba4cd3285acb38bc |
|
19-Nov-2008 |
Stuart Hastings <stuart@apple.com> |
<rdar://problem/6351057>
Discourage (allocate last) use of x86_64 R12 and R13 due to their
longer instruction encodings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59644 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86RegisterInfo.td
|
| fb88f1f9a73eea206013dfe0043970e9484760f8 |
|
14-Nov-2008 |
Dale Johannesen <dalej@apple.com> |
Remove unneeded stuff from GRAD register class.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59311 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86RegisterInfo.td
|
| 330169fa3e9c46c46bf130746d38e6ec2fac303a |
|
13-Nov-2008 |
Dale Johannesen <dalej@apple.com> |
Extend InlineAsm::C_Register to allow multiple specific registers
(actually, code already all worked, only the comment
changed). Use this to implement 'A' constraint on x86.
Fixes PR 1779.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59266 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86RegisterInfo.td
|
| 9ed08f4a410a3f0b6d38eb6eec0ddb94349e74dd |
|
31-Oct-2008 |
Evan Cheng <evan.cheng@apple.com> |
Change x86 register allocation ordering to match that of gcc. Otherwise some tools get confused by prologue generated by llvm.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58517 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86RegisterInfo.td
|
| ae270f66aa02dc440a34bdd39646fc1dc5754e92 |
|
08-Jul-2008 |
Evan Cheng <evan.cheng@apple.com> |
ATT asm printer just print register AsmName's instead of calling tolower on each charater of Name. This speeds it up by 10%.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53208 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86RegisterInfo.td
|
| a68f9013f2019652892e5701a876adec1d8b7e7f |
|
25-Jun-2008 |
Dale Johannesen <dalej@apple.com> |
Add v2f32 (MMX) type to X86. Support is primitive:
load,store,call,return,bitcast. This is enough to
make call and return work.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52691 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86RegisterInfo.td
|
| 1fab4a6bbb6eb5d44d35c8aade2493143b44d288 |
|
11-Mar-2008 |
Christopher Lamb <christopher.lamb@gmail.com> |
Recommitting parts of r48130. These do not appear to cause the observed failures.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48223 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86RegisterInfo.td
|
| 204496d58e7e740f0da6d41c6214a91d67950d26 |
|
11-Mar-2008 |
Evan Cheng <evan.cheng@apple.com> |
In 32-bit mode, mark 64-bit GPR's as unallocatable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48217 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86RegisterInfo.td
|
| 8e6da15e54125db38c0ae32f7a6b2273c792c588 |
|
10-Mar-2008 |
Chris Lattner <sabre@nondot.org> |
Eliminate the FP_GET_ST0/FP_SET_ST0 target-specific dag nodes, just lower to
copyfromreg/copytoreg instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48174 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86RegisterInfo.td
|
| 4499e495eabe8de7d595416a03c56af4688df507 |
|
10-Mar-2008 |
Evan Cheng <evan.cheng@apple.com> |
Revert 48125, 48126, and 48130 for now to unbreak some x86-64 tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48167 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86RegisterInfo.td
|
| 3feb0170a8d65984ce5c01a85e7dfd4005f8bb35 |
|
10-Mar-2008 |
Christopher Lamb <christopher.lamb@gmail.com> |
Allow insert_subreg into implicit, target-specific values.
Change insert/extract subreg instructions to be able to be used in TableGen patterns.
Use the above features to reimplement an x86-64 pseudo instruction as a pattern.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48130 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86RegisterInfo.td
|
| 8dc023f684216ecfae816cff370a40de8437300e |
|
09-Mar-2008 |
Chris Lattner <sabre@nondot.org> |
claim ST(x) registers are 80 bits, which is true. This doesn't affect
codegen yet because these can't be spilled (they don't exist until after RA).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48098 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86RegisterInfo.td
|
| 6f0d024a534af18d9e60b3ea757376cd8a3a980e |
|
10-Feb-2008 |
Dan Gohman <gohman@apple.com> |
Rename MRegisterInfo to TargetRegisterInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46930 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86RegisterInfo.td
|
| 8eea3392984428930b287aecb160c2feda981a13 |
|
25-Jan-2008 |
Anton Korobeynikov <asl@math.spbu.ru> |
Provide correct DWARF register numbering for debug information emission on x86-32/Darwin.
This should fix bunch of issues.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46337 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86RegisterInfo.td
|
| 4ee451de366474b9c228b4e5fa573795a715216d |
|
29-Dec-2007 |
Chris Lattner <sabre@nondot.org> |
Remove attribution from file headers, per discussion on llvmdev.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45418 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86RegisterInfo.td
|
| f191c80cd79ee35e47b5a4feed98d687782dfe85 |
|
11-Nov-2007 |
Anton Korobeynikov <asl@math.spbu.ru> |
Use TableGen to emit information for dwarf register numbers.
This makes DwarfRegNum to accept list of numbers instead.
Added three different "flavours", but only slightly tested on x86-32/linux.
Please check another subtargets if possible,
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43997 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86RegisterInfo.td
|
| 7a42f24f0c4171d6df94aca8db9cab567e79cf18 |
|
09-Nov-2007 |
Dale Johannesen <dalej@apple.com> |
Revert previous rewrite per chris's comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43950 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86RegisterInfo.td
|
| 3556bc1a9dde393a415ba3ac43c1e94426c90add |
|
09-Nov-2007 |
Dale Johannesen <dalej@apple.com> |
Rewrite Dwarf number handling per review comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43918 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86RegisterInfo.td
|
| 4542edcaa7fb508481f454b87d3dd11f636082dc |
|
07-Nov-2007 |
Dale Johannesen <dalej@apple.com> |
Complete conditionalization of Dwarf reg numbers.
Would somebody not on Darwin please make sure this
doesn't break anything. Exception handling failures
would be the most likely symptom.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43844 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86RegisterInfo.td
|
| 48abc5cf6ba6d53513034aa8c68b0a9abd748190 |
|
12-Oct-2007 |
Arnold Schwaighofer <arnold.schwaighofer@gmail.com> |
Corrected many typing errors. And removed 'nest' parameter handling
for fastcc from X86CallingConv.td. This means that nested functions
are not supported for calling convention 'fastcc'.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42934 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86RegisterInfo.td
|
| dcfa73fe3cf9b67573b188424477bc22ed900adf |
|
19-Sep-2007 |
Evan Cheng <evan.cheng@apple.com> |
Set CCR (EFLAGS) copy cost to -1, i.e. extremely expensive to copy.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42124 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86RegisterInfo.td
|
| 3054dde81377e24f312385c01fcab503d35f2d02 |
|
11-Sep-2007 |
Evan Cheng <evan.cheng@apple.com> |
Added status flags register: EFLAGS.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41862 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86RegisterInfo.td
|
| a3231ba237b1a5113a71253eab50c6b7a5239132 |
|
10-Aug-2007 |
Evan Cheng <evan.cheng@apple.com> |
Temporarily backing out this change until we know why some dejagnu tests are failing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40973 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86RegisterInfo.td
|
| a333b41af93a8a7f81d1d3d80651cf014d0390b2 |
|
09-Aug-2007 |
Evan Cheng <evan.cheng@apple.com> |
GR16_ sub-register class should be GR8_, not GR8. That is, it should only be 8-bit registers in 32-bit mode. Ditto for GR32_.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40970 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86RegisterInfo.td
|
| 59a587337e1c3bde6c0c560ad34f9ee73bb78328 |
|
05-Aug-2007 |
Dale Johannesen <dalej@apple.com> |
Long double patch 4 of N: initial x87 implementation.
Lots of problems yet but some simple things work.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40847 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86RegisterInfo.td
|
| f9b90ea955bb7e2839e24885f4bbe6ddea2ee013 |
|
28-Jul-2007 |
Christopher Lamb <christopher.lamb@gmail.com> |
Add register info needed to use subreg sets on X86.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40572 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86RegisterInfo.td
|
| 849f214a4e3676e41168b0c5398165c4d4fb99f8 |
|
03-Jul-2007 |
Dale Johannesen <dalej@apple.com> |
Fix for PR 1505 (and 1489). Rewrite X87 register
model to include f32 variants. Some factoring
improvments forthcoming.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37847 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86RegisterInfo.td
|
| 038082d96652601c70a98d4edffc834c835fc0bf |
|
02-May-2007 |
Anton Korobeynikov <asl@math.spbu.ru> |
Emit correct DWARF reg # for RA (return address) register
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36646 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86RegisterInfo.td
|
| 6120433e9e4748d72563125ed82108d7b66c7271 |
|
20-Apr-2007 |
Evan Cheng <evan.cheng@apple.com> |
Specify sub-register relations. e.g. RAX: [EAX], EAX: [AX], AX: [AL,AH].
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36279 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86RegisterInfo.td
|
| eebc8a1bc505ebb5c702e63c248a8956d88fda77 |
|
26-Mar-2007 |
Bill Wendling <isanbard@gmail.com> |
Add support for the v1i64 type. This makes better code for this:
#include <mmintrin.h>
extern __m64 C;
void baz(__v2si *A, __v2si *B)
{
*A = C;
_mm_empty();
}
We get this:
_baz:
call "L1$pb"
"L1$pb":
popl %eax
movl L_C$non_lazy_ptr-"L1$pb"(%eax), %eax
movq (%eax), %mm0
movl 4(%esp), %eax
movq %mm0, (%eax)
emms
ret
GCC gives us this:
_baz:
pushl %ebx
call L3
"L00000000001$pb":
L3:
popl %ebx
subl $8, %esp
movl L_C$non_lazy_ptr-"L00000000001$pb"(%ebx), %eax
movl (%eax), %edx
movl 4(%eax), %ecx
movl 16(%esp), %eax
movl %edx, (%eax)
movl %ecx, 4(%eax)
emms
addl $8, %esp
popl %ebx
ret
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35351 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86RegisterInfo.td
|
| dc77540d9506dc151d79b94bae88bd841880ef37 |
|
23-Jan-2007 |
Evan Cheng <evan.cheng@apple.com> |
hasFP() is now a virtual method of MRegisterInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33455 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86RegisterInfo.td
|
| 25ab690a43cbbb591b76d49e3595b019c32f4b3f |
|
08-Sep-2006 |
Evan Cheng <evan.cheng@apple.com> |
Committing X86-64 support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30177 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86RegisterInfo.td
|
| 5ea64fd9eb0027ad20a66ea29211eef79d8842a0 |
|
18-Aug-2006 |
Chris Lattner <sabre@nondot.org> |
Constify some methods. Patch provided by Anton Vayvod, thanks!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29756 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86RegisterInfo.td
|
| e46e1a5da7963f038f8534be51c9c7080a65374d |
|
07-Aug-2006 |
Evan Cheng <evan.cheng@apple.com> |
Make XMM, FP register dwarf register numbers consistent with gcc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29543 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86RegisterInfo.td
|
| 6b59a36564782fccca39ec5d43ba202c012829aa |
|
03-Aug-2006 |
Jim Laskey <jlaskey@mac.com> |
Get darwin intel debugging up and running.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29504 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86RegisterInfo.td
|
| 069287d460321af43b7c88b816da5c778e5f46d1 |
|
16-May-2006 |
Evan Cheng <evan.cheng@apple.com> |
X86 integer register classes naming changes. Make them consistent with FP, vector classes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28324 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86RegisterInfo.td
|
| 403be7eafc8922c20d7e8253bc8d6d0abd0448cb |
|
08-May-2006 |
Evan Cheng <evan.cheng@apple.com> |
Fixing truncate. Previously we were emitting truncate from r16 to r8 as
movw. That is we promote the destination operand to r16. So
%CH = TRUNC_R16_R8 %BP
is emitted as
movw %bp, %cx.
This is incorrect. If %cl is live, it would be clobbered.
Ideally we want to do the opposite, that is emitted it as
movb ??, %ch
But this is not possible since %bp does not have a r8 sub-register.
We are now defining a new register class R16_ which is a subclass of R16
containing only those 16-bit registers that have r8 sub-registers (i.e.
AX - DX). We isel the truncate to two instructions, a MOV16to16_ to copy the
value to the R16_ class, followed by a TRUNC_R16_R8.
Due to bug 770, the register colaescer is not going to coalesce between R16 and
R16_. That will be fixed later so we can eliminate the MOV16to16_. Right now, it
can only be eliminated if we are lucky that source and destination registers are
the same.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28164 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86RegisterInfo.td
|
| 74811450b24ee03f7328273b72efbeaad54d9e74 |
|
07-May-2006 |
Evan Cheng <evan.cheng@apple.com> |
Typo's
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28158 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86RegisterInfo.td
|
| 47622e37215429c20d8278ff57496d840811cc13 |
|
24-Mar-2006 |
Jim Laskey <jlaskey@mac.com> |
Add dwarf register numbering to register data.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27081 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86RegisterInfo.td
|
| 5c791c8ba44a16c743b6d480dd6b5f8f46e246fd |
|
21-Mar-2006 |
Evan Cheng <evan.cheng@apple.com> |
Junk unused vector register classes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26910 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86RegisterInfo.td
|
| 933be3318be64ec08687ac3ee92e8405662fb88f |
|
21-Feb-2006 |
Evan Cheng <evan.cheng@apple.com> |
Added SSE2 128-bit integer packed types: V16I8, V8I16, V4I32, and V2I64.
Added generic vector types: VR64 and VR128.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26295 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86RegisterInfo.td
|
| aea20f50e53a16374d514bc70e30b4ff234c015a |
|
20-Feb-2006 |
Evan Cheng <evan.cheng@apple.com> |
Added x86 integer vector types: 64-bit packed byte integer (v16i8), 64-bit
packed word integer (v8i16), and 64-bit packed doubleword integer (v2i32).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26294 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86RegisterInfo.td
|
| 71fb9ad5d90acf9c04f9f028fc8341569c90774d |
|
26-Jan-2006 |
Evan Cheng <evan.cheng@apple.com> |
Remove the uses of STATUS flag register. Rely on node property SDNPInFlag,
SDNPOutFlag, and SDNPOptInFlag instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25629 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86RegisterInfo.td
|
| 5bc4da48933a097924c4b80c9fa1cdb133978a54 |
|
22-Dec-2005 |
Evan Cheng <evan.cheng@apple.com> |
Bye bye HACKTROCITY.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24935 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86RegisterInfo.td
|
| b077b842b64af39c8e2e9aaad327b3be446790dd |
|
21-Dec-2005 |
Evan Cheng <evan.cheng@apple.com> |
* Added lowering hook for external weak global address. It inserts a load
for Darwin.
* Added lowering hook for ISD::RET. It inserts CopyToRegs for the return
value (or store / fld / copy to ST(0) for floating point value). This
eliminate the need to write C++ code to handle RET with variable number
of operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24888 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86RegisterInfo.td
|
| bbc8ddbea30ea807ef6deeaa2b7965e38ac3c28a |
|
20-Dec-2005 |
Evan Cheng <evan.cheng@apple.com> |
SSE2 floating point load / store patterns. SSE2 fp to int conversion patterns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24886 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86RegisterInfo.td
|
| aed7c721dfd6a3a27d07f582cb0057e64385ba45 |
|
17-Dec-2005 |
Evan Cheng <evan.cheng@apple.com> |
Added support for cmp, test, and conditional move instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24756 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86RegisterInfo.td
|
| 6510b22cec7de4f0acc9965ec24c3668a6a8a87e |
|
01-Dec-2005 |
Nate Begeman <natebegeman@mac.com> |
Support multiple ValueTypes per RegisterClass, needed for upcoming vector
work. This change has no effect on generated code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24563 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86RegisterInfo.td
|
| 14e2cf62f43130a6ba5c4c72f83051a452633d8b |
|
15-Oct-2005 |
Nate Begeman <natebegeman@mac.com> |
Properly split f32 and f64 into separate register classes for scalar sse fp
fixing a bunch of nasty hackery
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23735 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86RegisterInfo.td
|
| ecbce617ca5ca4c8f881c56297b9aac931d91744 |
|
19-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
Split RegisterClass 'Methods' into MethodProtos and MethodBodies
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22929 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86RegisterInfo.td
|
| 03ba7b9f25b60b1e95caacb34b0a7e8fc05e860e |
|
19-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
Put register classes into namespaces
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22925 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86RegisterInfo.td
|
| f63be7d3959939b2ffaf0bba5519b71216ec9ee6 |
|
06-Jul-2005 |
Nate Begeman <natebegeman@mac.com> |
First round of support for doing scalar FP using the SSE2 ISA extension and
XMM registers. There are many known deficiencies and fixmes, which will be
addressed ASAP. The major benefit of this work is that it will allow the
LLVM register allocator to allocate FP registers across basic blocks.
The x86 backend will still default to x87 style FP. To enable this work,
you must pass -enable-sse-scalar-fp and either -sse2 or -sse3 to llc.
An example before and after would be for:
double foo(double *P) { double Sum = 0; int i; for (i = 0; i < 1000; ++i)
Sum += P[i]; return Sum; }
The inner loop looks like the following:
x87:
.LBB_foo_1: # no_exit
fldl (%esp)
faddl (%eax,%ecx,8)
fstpl (%esp)
incl %ecx
cmpl $1000, %ecx
#FP_REG_KILL
jne .LBB_foo_1 # no_exit
SSE2:
addsd (%eax,%ecx,8), %xmm0
incl %ecx
cmpl $1000, %ecx
#FP_REG_KILL
jne .LBB_foo_1 # no_exit
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22340 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86RegisterInfo.td
|
| f1702ac589126e527f8fc5e46c971353b94682fa |
|
27-Jun-2005 |
Nate Begeman <natebegeman@mac.com> |
Initial set of .td file changes necessary to get scalar fp in xmm registers
working. The instruction selector changes will hopefully be coming later
this week once they are debugged. This is necessary to support the darwin
x86 FP model, and is recommended by intel as the replacement for x87. As
a bonus, the register allocator knows how to deal with these registers
across basic blocks, unliky the FP stackifier. This leads to significantly
better codegen in several cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22300 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86RegisterInfo.td
|
| 0539313fe5b9d9050cc23b245cfe213b927a296b |
|
05-Jan-2005 |
Chris Lattner <sabre@nondot.org> |
Minor optimization to allocate R8 registers in a better order.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19289 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86RegisterInfo.td
|
| 45de191b0bb337142a3f2a09f5f7410844e46a81 |
|
02-Dec-2004 |
Chris Lattner <sabre@nondot.org> |
Spill/restore X86 floating point stack registers with 64-bits of precision
instead of 80-bits of precision. This fixes PR467.
This change speeds up fldry on X86 with LLC from 7.32s on apoc to 4.68s.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@18433 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86RegisterInfo.td
|
| 65cbfa0f370f70bb5bd57c084fd73dde6fa35cee |
|
21-Sep-2004 |
Alkis Evlogimenos <alkis@evlogimenos.com> |
The real x87 floating point registers should not be allocatable. They
are only used by the stackifier when transforming FPn register
allocations to the real stack file x87 registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16472 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86RegisterInfo.td
|
| a2700194aed0b9d11a0ebf70e260f7ed70c86213 |
|
15-Sep-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
Fit long lines into 80 cols via creative space elimination
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16353 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86RegisterInfo.td
|
| b228657acc4afbdc74dc523e9f465d08935f9e8d |
|
14-Sep-2004 |
Chris Lattner <sabre@nondot.org> |
Revamp the Register class, and allow the use of the RegisterGroup class to
specify aliases directly in register definitions.
Patch contributed by Jason Eckhardt!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16330 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86RegisterInfo.td
|
| 47d2f2bb50414eb1b2fc26592ebad6b00272e0e5 |
|
24-Aug-2004 |
Chris Lattner <sabre@nondot.org> |
Nuke commented out stuff
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16017 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86RegisterInfo.td
|
| ff0a6e6aac13f15cb80c54c16e4c906b3e303b9b |
|
21-Aug-2004 |
Chris Lattner <sabre@nondot.org> |
Switch from bytes to bits for alignment for consistency
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15974 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86RegisterInfo.td
|
| 068758e518f0fe4ab67490f2eec0fd3b376a4d2c |
|
01-Aug-2004 |
Chris Lattner <sabre@nondot.org> |
give FP stack registers names
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15394 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86RegisterInfo.td
|
| 9c22aeb0b2c294b3d6a50672ecfd9a0f505f2dc0 |
|
29-Feb-2004 |
Alkis Evlogimenos <alkis@evlogimenos.com> |
Improve allocation order:
1) For 8-bit registers try to use first the ones that are parts of the
same register (AL then AH). This way we only alias 2 16/32-bit
registers after allocating 4 8-bit variables.
2) Move EBX as the last register to allocate. This will cause less
spills to happen since we will have 8-bit registers available up to
register excaustion (assuming we use the allocation order). It
would be nice if we could push all of the 8-bit aliased registers
towards the end but we much prefer to keep callee saved register to
the end to avoid saving them on entry and exit of the function.
For example this gives a slight reduction of spills with linear scan
on 164.gzip.
Before:
11221 asm-printer - Number of machine instrs printed
975 spiller - Number of loads added
675 spiller - Number of stores added
398 spiller - Number of register spills
After:
11182 asm-printer - Number of machine instrs printed
952 spiller - Number of loads added
652 spiller - Number of stores added
386 spiller - Number of register spills
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11996 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86RegisterInfo.td
|
| 856ba76200ec2302f2fe500bc507f426c7d566c8 |
|
21-Oct-2003 |
John Criswell <criswell@uiuc.edu> |
Added LLVM copyright header.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@9321 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86RegisterInfo.td
|
| bf2f8a9963d880db15c0a30d4ed540bd43ed469d |
|
11-Aug-2003 |
Misha Brukman <brukman+llvm@gmail.com> |
Converted tabs to spaces.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@7728 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86RegisterInfo.td
|
| 69666e552ef0f4d9437de8b323de80255bf035a1 |
|
07-Aug-2003 |
Chris Lattner <sabre@nondot.org> |
This register is never used, disable it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@7661 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86RegisterInfo.td
|
| 6770aedf7f463201d787a4d1b5a61d9d6a51bd38 |
|
04-Aug-2003 |
Chris Lattner <sabre@nondot.org> |
Rename register classes to be upper case to make it obvious that they are X86
specific in the tree patterns
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@7578 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86RegisterInfo.td
|
| c8f4587efd04745c510fe4dd7b6f8fd303fb167d |
|
04-Aug-2003 |
Chris Lattner <sabre@nondot.org> |
transition to using let instead of set
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@7564 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86RegisterInfo.td
|
| 7af9a38d0f895a72ef58f165662993974a3b7bad |
|
04-Aug-2003 |
Chris Lattner <sabre@nondot.org> |
Specify custom name for registers to get the ()'s in the name.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@7547 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86RegisterInfo.td
|
| 9eab31652856e6a5a15bdf7431a01638cba5a1f7 |
|
03-Aug-2003 |
Chris Lattner <sabre@nondot.org> |
The RegisterInfo class is obsolete
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@7522 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86RegisterInfo.td
|
| b76d6fc4d55f532cce435db43e6121cc8b5e60a7 |
|
03-Aug-2003 |
Chris Lattner <sabre@nondot.org> |
Initial checkin of X86 Register File description
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@7509 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86RegisterInfo.td
|