X86RegisterInfo.td revision c8f4587efd04745c510fe4dd7b6f8fd303fb167d 
1//===- X86RegisterInfo.td - Describe the X86 Register File ------*- C++ -*-===//
2//
3// This file describes the X86 Register file, defining the registers themselves,
4// aliases between the registers, and the register classes built out of the
5// registers.
6//
7//===----------------------------------------------------------------------===//
8
9//===----------------------------------------------------------------------===//
10//  Register definitions...
11//
12let Namespace = "X86" in {
13  // 32-bit registers
14  def EAX : Register; def ECX : Register;
15  def EDX : Register; def EBX : Register;
16  def ESP : Register; def EBP : Register;
17  def ESI : Register; def EDI : Register;
18  
19  // 16-bit registers
20  def AX : Register; def CX : Register;
21  def DX : Register; def BX : Register;
22  def SP : Register; def BP : Register;
23  def SI : Register; def DI : Register;
24  
25  // 8-bit registers
26  def AL : Register; def CL : Register;
27  def DL : Register; def BL : Register;
28  def AH : Register; def CH : Register;
29  def DH : Register; def BH : Register;
30  
31  // Pseudo Floating Point registers
32  def FP0 : Register; def FP1 : Register;
33  def FP2 : Register; def FP3 : Register;
34  def FP4 : Register; def FP5 : Register;
35  def FP6 : Register; 
36
37  // Floating point stack registers
38  def ST0 : NamedReg<"ST(0)">; def ST1 : NamedReg<"ST(1)">;
39  def ST2 : NamedReg<"ST(2)">; def ST3 : NamedReg<"ST(3)">;
40  def ST4 : NamedReg<"ST(4)">; def ST5 : NamedReg<"ST(5)">;
41  def ST6 : NamedReg<"ST(6)">; def ST7 : NamedReg<"ST(7)">; 
42  
43  // Flags, Segment registers, etc...
44  
45  // This is a slimy hack to make it possible to say that flags are clobbered...
46  // Ideally we'd model instructions based on which particular flag(s) they
47  // could clobber. 
48  def EFLAGS : Register;
49}
50
51//===----------------------------------------------------------------------===//
52// Register alias definitions... define which registers alias which others.  We
53// only specify which registers the small registers alias, because the register
54// file generator is smart enough to figure out that AL aliases AX if we tell it
55// that AX aliases AL (for example).
56//
57def : RegisterAliases<AL, [AX, EAX]>; def : RegisterAliases<BL, [BX, EBX]>;
58def : RegisterAliases<CL, [CX, ECX]>; def : RegisterAliases<DL, [DX, EDX]>;
59def : RegisterAliases<AH, [AX, EAX]>; def : RegisterAliases<BH, [BX, EBX]>;
60def : RegisterAliases<CH, [CX, ECX]>; def : RegisterAliases<DH, [DX, EDX]>;
61
62def : RegisterAliases<AX, [EAX]>;     def : RegisterAliases<BX, [EBX]>;
63def : RegisterAliases<CX, [ECX]>;     def : RegisterAliases<DX, [EDX]>;
64def : RegisterAliases<SI, [ESI]>;     def : RegisterAliases<DI, [EDI]>;
65def : RegisterAliases<SP, [ESP]>;     def : RegisterAliases<BP, [EBP]>;
66
67//===----------------------------------------------------------------------===//
68// Register Class Definitions... now that we have all of the pieces, define the
69// top-level register classes.  The order specified in the register list is
70// implicitly defined to be the register allocation order.
71//
72def r8  : RegisterClass<i8,  1, [AL, CL, DL, BL, AH, CH, DH, BH]>;
73def r16 : RegisterClass<i16, 2, [AX, CX, DX, BX, SI, DI, BP, SP]> {
74  let Methods = [{
75    iterator allocation_order_end(MachineFunction &MF) const {
76      if (hasFP(MF))     // Does the function dedicate EBP to being a frame ptr?
77	return end()-2;  // If so, don't allocate SP or BP
78      else
79	return end()-1;  // If not, just don't allocate SP
80    }
81  }];
82}
83
84def r32 : RegisterClass<i32, 4, [EAX, ECX, EDX, EBX, ESI, EDI, EBP, ESP]> {
85  let Methods = [{
86    iterator allocation_order_end(MachineFunction &MF) const {
87      if (hasFP(MF))     // Does the function dedicate EBP to being a frame ptr?
88        return end()-2;  // If so, don't allocate ESP or EBP
89      else
90        return end()-1;  // If not, just don't allocate ESP
91    }
92  }];
93}
94
95def rFP : RegisterClass<f80, 4, [FP0, FP1, FP2, FP3, FP4, FP5, FP6]>;
96
97// Registers which cannot be allocated... and are thus left unnamed.
98def : RegisterClass<f80, 4, [ST0, ST1, ST2, ST3, ST4, ST5, ST6, ST7]>;
99def : RegisterClass<i16, 2, [EFLAGS]>;
100
101