X86RegisterInfo.td revision 933be3318be64ec08687ac3ee92e8405662fb88f 
1//===- X86RegisterInfo.td - Describe the X86 Register File ------*- C++ -*-===//
2// 
3//                     The LLVM Compiler Infrastructure
4//
5// This file was developed by the LLVM research group and is distributed under
6// the University of Illinois Open Source License. See LICENSE.TXT for details.
7// 
8//===----------------------------------------------------------------------===//
9//
10// This file describes the X86 Register file, defining the registers themselves,
11// aliases between the registers, and the register classes built out of the
12// registers.
13//
14//===----------------------------------------------------------------------===//
15
16//===----------------------------------------------------------------------===//
17//  Register definitions...
18//
19let Namespace = "X86" in {
20
21  // In the register alias definitions below, we define which registers alias
22  // which others.  We only specify which registers the small registers alias,
23  // because the register file generator is smart enough to figure out that
24  // AL aliases AX if we tell it that AX aliased AL (for example).
25
26  // 32-bit registers
27  def EAX : Register<"EAX">; def ECX : Register<"ECX">;
28  def EDX : Register<"EDX">; def EBX : Register<"EBX">;
29  def ESP : Register<"ESP">; def EBP : Register<"EBP">;
30  def ESI : Register<"ESI">; def EDI : Register<"EDI">;
31  
32  // 16-bit registers
33  def AX : RegisterGroup<"AX", [EAX]>; def CX : RegisterGroup<"CX", [ECX]>;
34  def DX : RegisterGroup<"DX", [EDX]>; def BX : RegisterGroup<"BX", [EBX]>;
35  def SP : RegisterGroup<"SP", [ESP]>; def BP : RegisterGroup<"BP", [EBP]>;
36  def SI : RegisterGroup<"SI", [ESI]>; def DI : RegisterGroup<"DI", [EDI]>;
37  
38  // 8-bit registers
39  def AL : RegisterGroup<"AL", [AX,EAX]>; def CL : RegisterGroup<"CL",[CX,ECX]>;
40  def DL : RegisterGroup<"DL", [DX,EDX]>; def BL : RegisterGroup<"BL",[BX,EBX]>;
41  def AH : RegisterGroup<"AH", [AX,EAX]>; def CH : RegisterGroup<"CH",[CX,ECX]>;
42  def DH : RegisterGroup<"DH", [DX,EDX]>; def BH : RegisterGroup<"BH",[BX,EBX]>;
43
44  // MMX Registers. These are actually aliased to ST0 .. ST7
45  def MM0 : Register<"MM0">; def MM1 : Register<"MM1">;
46  def MM2 : Register<"MM2">; def MM3 : Register<"MM3">;
47  def MM4 : Register<"MM4">; def MM5 : Register<"MM5">;
48  def MM6 : Register<"MM6">; def MM7 : Register<"MM7">;
49  
50  // Pseudo Floating Point registers
51  def FP0 : Register<"FP0">; def FP1 : Register<"FP1">;
52  def FP2 : Register<"FP2">; def FP3 : Register<"FP3">;
53  def FP4 : Register<"FP4">; def FP5 : Register<"FP5">;
54  def FP6 : Register<"FP6">; 
55
56  // XMM Registers, used by the various SSE instruction set extensions
57  def XMM0: Register<"XMM0">; def XMM1: Register<"XMM1">;
58  def XMM2: Register<"XMM2">; def XMM3: Register<"XMM3">;
59  def XMM4: Register<"XMM4">; def XMM5: Register<"XMM5">;
60  def XMM6: Register<"XMM6">; def XMM7: Register<"XMM7">;
61
62  // Floating point stack registers
63  def ST0 : Register<"ST(0)">; def ST1 : Register<"ST(1)">;
64  def ST2 : Register<"ST(2)">; def ST3 : Register<"ST(3)">;
65  def ST4 : Register<"ST(4)">; def ST5 : Register<"ST(5)">;
66  def ST6 : Register<"ST(6)">; def ST7 : Register<"ST(7)">; 
67}
68
69//===----------------------------------------------------------------------===//
70// Register Class Definitions... now that we have all of the pieces, define the
71// top-level register classes.  The order specified in the register list is
72// implicitly defined to be the register allocation order.
73//
74
75// List AL,CL,DL before AH,CH,DH, as X86 processors often suffer from false
76// dependences between upper and lower parts of the register.  BL and BH are
77// last because they are call clobbered. Both Athlon and P4 chips suffer this
78// issue.
79def R8  : RegisterClass<"X86", [i8],  8, [AL, CL, DL, AH, CH, DH, BL, BH]>;
80
81def R16 : RegisterClass<"X86", [i16], 16, [AX, CX, DX, SI, DI, BX, BP, SP]> {
82  let MethodProtos = [{
83    iterator allocation_order_end(MachineFunction &MF) const;
84  }];
85  let MethodBodies = [{
86    R16Class::iterator
87    R16Class::allocation_order_end(MachineFunction &MF) const {
88      if (hasFP(MF))     // Does the function dedicate EBP to being a frame ptr?
89        return end()-2;  // If so, don't allocate SP or BP
90      else
91        return end()-1;  // If not, just don't allocate SP
92    }
93  }];
94}
95
96def R32 : RegisterClass<"X86", [i32], 32, 
97                        [EAX, ECX, EDX, ESI, EDI, EBX, EBP, ESP]> {
98  let MethodProtos = [{
99    iterator allocation_order_end(MachineFunction &MF) const;
100  }];
101  let MethodBodies = [{
102    R32Class::iterator
103    R32Class::allocation_order_end(MachineFunction &MF) const {
104      if (hasFP(MF))     // Does the function dedicate EBP to being a frame ptr?
105        return end()-2;  // If so, don't allocate ESP or EBP
106      else
107        return end()-1;  // If not, just don't allocate ESP
108    }
109  }];
110}
111
112// Scalar SSE2 floating point registers.
113def FR32 : RegisterClass<"X86", [f32], 32,
114                         [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7]>;
115def FR64 : RegisterClass<"X86", [f64], 64,
116                         [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7]>;
117
118// FIXME: This sets up the floating point register files as though they are f64
119// values, though they really are f80 values.  This will cause us to spill
120// values as 64-bit quantities instead of 80-bit quantities, which is much much
121// faster on common hardware.  In reality, this should be controlled by a
122// command line option or something.
123
124def RFP : RegisterClass<"X86", [f64], 32, [FP0, FP1, FP2, FP3, FP4, FP5, FP6]>;
125
126// Floating point stack registers (these are not allocatable by the
127// register allocator - the floating point stackifier is responsible
128// for transforming FPn allocations to STn registers)
129def RST : RegisterClass<"X86", [f64], 32,
130                        [ST0, ST1, ST2, ST3, ST4, ST5, ST6, ST7]> {
131    let MethodProtos = [{
132    iterator allocation_order_end(MachineFunction &MF) const;
133  }];
134  let MethodBodies = [{
135    RSTClass::iterator
136    RSTClass::allocation_order_end(MachineFunction &MF) const {
137      return begin();
138    }
139  }];
140}
141
142// Vector integer registers: V8I8, the 8 x i8 class, V4I16, the 4 x i16 class,
143// V2I32, the 2 x i32 class, V16I8, the 16 x i8 class, V8I16, the 8 x i16 class,
144// V4I32, the 4 x i32 class, and V2I64, the 2 x i64 class.
145def V8I8  : RegisterClass<"X86", [v8i8],  64,
146                          [MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7]>;
147def V4I16 : RegisterClass<"X86", [v4i16], 64,
148                          [MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7]>;
149def V2I32 : RegisterClass<"X86", [v2i32], 64,
150                          [MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7]>;
151def V16I8 : RegisterClass<"X86", [v16i8], 128,
152                          [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7]>;
153def V8I16 : RegisterClass<"X86", [v8i16], 128,
154                          [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7]>;
155def V4I32 : RegisterClass<"X86", [v4i32], 128,
156                          [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7]>;
157def V2I64 : RegisterClass<"X86", [v2i64], 128,
158                          [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7]>;
159
160// Vector floating point registers: V4F4, the 4 x f32 class, and V2F8,
161// the 2 x f64 class.
162def V4F32 : RegisterClass<"X86", [v4f32], 128,
163                         [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7]>;
164def V2F64 : RegisterClass<"X86", [v2f64], 128,
165                         [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7]>;
166
167// Generic vector registers: VR64 and VR128.
168def VR64  : RegisterClass<"X86", [v8i8, v4i16, v2i32], 64,
169                          [MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7]>;
170def VR128 : RegisterClass<"X86", [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],128,
171                         [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7]>;
172