1// RUN: llvm-mc -arch=amdgcn -show-encoding %s | FileCheck %s
2// RUN: llvm-mc -arch=amdgcn -mcpu=SI -show-encoding %s | FileCheck %s
3
4//===----------------------------------------------------------------------===//
5// Generic Checks for floating-point instructions (These have modifiers).
6//===----------------------------------------------------------------------===//
7
8// TODO: 64-bit encoding of instructions with modifiers
9
10// _e32 suffix
11// CHECK: v_add_f32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x06]
12v_add_f32_e32 v1, v2, v3
13
14// src0 inline immediate
15// CHECK: v_add_f32_e32 v1, 1.0, v3 ; encoding: [0xf2,0x06,0x02,0x06]
16v_add_f32 v1, 1.0, v3
17
18// src0 negative inline immediate
19// CHECK: v_add_f32_e32 v1, -1.0, v3 ; encoding: [0xf3,0x06,0x02,0x06]
20v_add_f32 v1, -1.0, v3
21
22// src0 literal
23// CHECK: v_add_f32_e32 v1, 0x42c80000, v3 ; encoding: [0xff,0x06,0x02,0x06,0x00,0x00,0xc8,0x42]
24v_add_f32 v1, 100.0, v3
25
26// src0 negative literal
27// CHECK: v_add_f32_e32 v1, 0xc2c80000, v3 ; encoding: [0xff,0x06,0x02,0x06,0x00,0x00,0xc8,0xc2]
28v_add_f32 v1, -100.0, v3
29
30//===----------------------------------------------------------------------===//
31// Generic Checks for integer instructions (These don't have modifiers).
32//===----------------------------------------------------------------------===//
33
34// _e32 suffix
35// CHECK: v_mul_i32_i24_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x12]
36v_mul_i32_i24_e32 v1, v2, v3
37
38// _e64 suffix
39// CHECK: v_mul_i32_i24_e64 v1, v2, v3 ; encoding: [0x01,0x00,0x12,0xd2,0x02,0x07,0x02,0x00]
40v_mul_i32_i24_e64 v1, v2, v3
41
42// src0 inline
43// CHECK: v_mul_i32_i24_e32 v1, 3, v3 ; encoding: [0x83,0x06,0x02,0x12]
44v_mul_i32_i24 v1, 3, v3
45
46// src0 negative inline
47// CHECK: v_mul_i32_i24_e32 v1, -3, v3 ; encoding: [0xc3,0x06,0x02,0x12]
48v_mul_i32_i24 v1, -3, v3
49
50// src1 inline
51// CHECK: v_mul_i32_i24_e64 v1, v2, 3 ; encoding: [0x01,0x00,0x12,0xd2,0x02,0x07,0x01,0x00]
52v_mul_i32_i24 v1, v2, 3
53
54// src1 negative inline
55// CHECK: v_mul_i32_i24_e64 v1, v2, -3 ; encoding: [0x01,0x00,0x12,0xd2,0x02,0x87,0x01,0x00]
56v_mul_i32_i24 v1, v2, -3
57
58// src0 literal
59// CHECK: v_mul_i32_i24_e32 v1, 0x64, v3 ; encoding: [0xff,0x06,0x02,0x12,0x64,0x00,0x00,0x00]
60v_mul_i32_i24 v1, 100, v3
61
62// src1 negative literal
63// CHECK: v_mul_i32_i24_e32 v1, 0xffffff9c, v3 ; encoding: [0xff,0x06,0x02,0x12,0x9c,0xff,0xff,0xff]
64v_mul_i32_i24 v1, -100, v3
65
66//===----------------------------------------------------------------------===//
67// Checks for legal operands
68//===----------------------------------------------------------------------===//
69
70// src0 sgpr
71// CHECK: v_mul_i32_i24_e32 v1, s2, v3 ; encoding: [0x02,0x06,0x02,0x12]
72v_mul_i32_i24 v1, s2, v3
73
74// src1 sgpr
75// CHECK: v_mul_i32_i24_e64 v1, v2, s3 ; encoding: [0x01,0x00,0x12,0xd2,0x02,0x07,0x00,0x00]
76v_mul_i32_i24 v1, v2, s3
77
78// src0, src1 same sgpr
79// CHECK: v_mul_i32_i24_e64 v1, s2, s2 ; encoding: [0x01,0x00,0x12,0xd2,0x02,0x04,0x00,0x00]
80v_mul_i32_i24 v1, s2, s2
81
82// src0 sgpr, src1 inline
83// CHECK: v_mul_i32_i24_e64 v1, s2, 3 ; encoding: [0x01,0x00,0x12,0xd2,0x02,0x06,0x01,0x00]
84v_mul_i32_i24 v1, s2, 3
85
86// src0 inline src1 sgpr
87// CHECK: v_mul_i32_i24_e64 v1, 3, s3 ; encoding: [0x01,0x00,0x12,0xd2,0x83,0x06,0x00,0x00]
88v_mul_i32_i24 v1, 3, s3
89
90//===----------------------------------------------------------------------===//
91// Instructions
92//===----------------------------------------------------------------------===//
93
94// CHECK: v_cndmask_b32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x00]
95v_cndmask_b32 v1, v2, v3
96
97// CHECK: v_readlane_b32 s1, v2, s3 ; encoding: [0x02,0x07,0x02,0x02]
98v_readlane_b32 s1, v2, s3
99
100// CHECK: v_writelane_b32 v1, s2, s3 ; encoding: [0x02,0x06,0x02,0x04]
101v_writelane_b32 v1, s2, s3
102
103// CHECK: v_add_f32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x06]
104v_add_f32 v1, v2, v3
105
106// CHECK: v_sub_f32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x08]
107v_sub_f32 v1, v2, v3
108
109// CHECK: v_subrev_f32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x0a]
110v_subrev_f32 v1, v2, v3
111
112// CHECK: v_mac_legacy_f32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x0c]
113v_mac_legacy_f32 v1, v2, v3
114
115// CHECK: v_mul_legacy_f32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x0e]
116v_mul_legacy_f32_e32 v1, v2, v3
117
118// CHECK: v_mul_f32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x10]
119v_mul_f32 v1, v2, v3
120
121// CHECK: v_mul_i32_i24_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x12]
122v_mul_i32_i24 v1, v2, v3
123
124// CHECK: v_mul_hi_i32_i24_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x14]
125v_mul_hi_i32_i24 v1, v2, v3
126
127// CHECK: v_mul_u32_u24_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x16]
128v_mul_u32_u24 v1, v2, v3
129
130// CHECK: v_mul_hi_u32_u24_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x18]
131v_mul_hi_u32_u24 v1, v2, v3
132
133// CHECK: v_min_legacy_f32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x1a]
134v_min_legacy_f32_e32 v1, v2, v3
135
136// CHECK: v_max_legacy_f32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x1c]
137v_max_legacy_f32 v1, v2, v3
138
139// CHECK: v_min_f32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x1e]
140v_min_f32_e32 v1, v2, v3
141
142// CHECK: v_max_f32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x20]
143v_max_f32 v1, v2 v3
144
145// CHECK: v_min_i32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x22]
146v_min_i32 v1, v2, v3
147
148// CHECK: v_max_i32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x24]
149v_max_i32 v1, v2, v3
150
151// CHECK: v_min_u32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x26]
152v_min_u32 v1, v2, v3
153
154// CHECK: v_max_u32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x28]
155v_max_u32 v1, v2, v3
156
157// CHECK: v_lshr_b32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x2a]
158v_lshr_b32 v1, v2, v3
159
160// CHECK: v_lshrrev_b32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x2c]
161v_lshrrev_b32 v1, v2, v3
162
163// CHECK: v_ashr_i32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x2e]
164v_ashr_i32 v1, v2, v3
165
166// CHECK: v_ashrrev_i32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x30]
167v_ashrrev_i32 v1, v2, v3
168
169// CHECK: v_lshl_b32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x32]
170v_lshl_b32_e32 v1, v2, v3
171
172// CHECK: v_lshlrev_b32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x34]
173v_lshlrev_b32 v1, v2, v3
174
175// CHECK: v_and_b32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x36]
176v_and_b32 v1, v2, v3
177
178// CHECK: v_or_b32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x38]
179v_or_b32 v1, v2, v3
180
181// CHECK: v_xor_b32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x3a]
182v_xor_b32 v1, v2, v3
183
184// CHECK: v_bfm_b32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x3c]
185v_bfm_b32 v1, v2, v3
186
187// CHECK: v_mac_f32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x3e]
188v_mac_f32 v1, v2, v3
189
190// CHECK: v_madmk_f32_e32 v1, v2, v3, 0x42800000 ; encoding: [0x02,0x07,0x02,0x40,0x00,0x00,0x80,0x42]
191v_madmk_f32 v1, v2, v3, 64.0
192
193// CHECK: v_madak_f32_e32 v1, v2, v3, 0x42800000 ; encoding: [0x02,0x07,0x02,0x42,0x00,0x00,0x80,0x42]
194v_madak_f32 v1, v2, v3, 64.0
195
196// CHECK: v_bcnt_u32_b32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x44]
197v_bcnt_u32_b32 v1, v2, v3
198
199// CHECK: v_mbcnt_lo_u32_b32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x46]
200v_mbcnt_lo_u32_b32 v1, v2, v3
201
202// CHECK: v_mbcnt_hi_u32_b32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x48]
203v_mbcnt_hi_u32_b32_e32 v1, v2, v3
204
205// CHECK: v_add_i32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x4a]
206v_add_i32 v1, v2, v3
207
208// CHECK: v_sub_i32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x4c]
209v_sub_i32_e32 v1, v2, v3
210
211// CHECK: v_subrev_i32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x4e]
212v_subrev_i32 v1, v2, v3
213
214// CHECK : v_addc_u32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x50]
215v_addc_u32 v1, v2, v3
216
217// CHECK: v_subb_u32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x52]
218v_subb_u32 v1, v2, v3
219
220// CHECK: v_subbrev_u32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x54]
221v_subbrev_u32 v1, v2, v3
222
223// CHECK: v_ldexp_f32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x56]
224v_ldexp_f32 v1, v2, v3
225
226// CHECK: v_cvt_pkaccum_u8_f32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x58]
227v_cvt_pkaccum_u8_f32 v1, v2, v3
228
229// CHECK: v_cvt_pknorm_i16_f32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x5a]
230v_cvt_pknorm_i16_f32 v1, v2, v3
231
232// CHECK: v_cvt_pknorm_u16_f32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x5c]
233v_cvt_pknorm_u16_f32 v1, v2, v3
234
235// CHECK: v_cvt_pkrtz_f16_f32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x5e]
236v_cvt_pkrtz_f16_f32 v1, v2, v3
237
238// CHECK: v_cvt_pk_u16_u32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x60]
239v_cvt_pk_u16_u32_e32 v1, v2, v3
240
241// CHECK: v_cvt_pk_i16_i32_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x62]
242v_cvt_pk_i16_i32 v1, v2, v3
243