3d21bdf8894e780d349c481e5c9e29fe1556051c |
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22-Apr-2015 |
Mathieu Chartier <mathieuc@google.com> |
Move mirror::ArtMethod to native Optimizing + quick tests are passing, devices boot. TODO: Test and fix bugs in mips64. Saves 16 bytes per most ArtMethod, 7.5MB reduction in system PSS. Some of the savings are from removal of virtual methods and direct methods object arrays. Bug: 19264997 (cherry picked from commit e401d146407d61eeb99f8d6176b2ac13c4df1e33) Change-Id: I622469a0cfa0e7082a2119f3d6a9491eb61e3f3d Fix some ArtMethod related bugs Added root visiting for runtime methods, not currently required since the GcRoots in these methods are null. Added missing GetInterfaceMethodIfProxy in GetMethodLine, fixes --trace run-tests 005, 044. Fixed optimizing compiler bug where we used a normal stack location instead of double on ARM64, this fixes the debuggable tests. TODO: Fix JDWP tests. Bug: 19264997 Change-Id: I7c55f69c61d1b45351fd0dc7185ffe5efad82bd3 ART: Fix casts for 64-bit pointers on 32-bit compiler. Bug: 19264997 Change-Id: Ief45cdd4bae5a43fc8bfdfa7cf744e2c57529457 Fix JDWP tests after ArtMethod change Fixes Throwable::GetStackDepth for exception event detection after internal stack trace representation change. Adds missing ArtMethod::GetInterfaceMethodIfProxy call in case of proxy method. Bug: 19264997 Change-Id: I363e293796848c3ec491c963813f62d868da44d2 Fix accidental IMT and root marking regression Was always using the conflict trampoline. Also included fix for regression in GC time caused by extra roots. Most of the regression was IMT. Fixed bug in DumpGcPerformanceInfo where we would get SIGABRT due to detached thread. EvaluateAndApplyChanges: From ~2500 -> ~1980 GC time: 8.2s -> 7.2s due to 1s less of MarkConcurrentRoots Bug: 19264997 Change-Id: I4333e80a8268c2ed1284f87f25b9f113d4f2c7e0 Fix bogus image test assert Previously we were comparing the size of the non moving space to size of the image file. Now we properly compare the size of the image space against the size of the image file. Bug: 19264997 Change-Id: I7359f1f73ae3df60c5147245935a24431c04808a [MIPS64] Fix art_quick_invoke_stub argument offsets. ArtMethod reference's size got bigger, so we need to move other args and leave enough space for ArtMethod* and 'this' pointer. This fixes mips64 boot. Bug: 19264997 Change-Id: I47198d5f39a4caab30b3b77479d5eedaad5006ab
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69a503050fb8a7b3a79b2cd2cdc2d8fbc594575d |
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14-Apr-2015 |
Zheng Xu <zheng.xu@arm.com> |
ARM64: Remove suspend register. It also clean up build/remove frame used by JNI compiler and generates stp/ldp instead of str/ldr. Also x19 has been unblocked in both quick and optimizing compiler. Change-Id: Idbeac0942265f493266b2ef9b7a65bb4054f0e2d
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20f85597828194c12be10d3a927999def066555e |
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19-Mar-2015 |
Vladimir Marko <vmarko@google.com> |
Fixed layout for dex caches in boot image. Define a fixed layout for dex cache arrays (type, method, string and field arrays) for dex caches in the boot image. This gives those arrays fixed offsets from the boot image code and allows PC-relative addressing of their elements. Use the PC-relative load on arm64 for relevant instructions, i.e. invoke-static, invoke-direct, const-string, const-class, check-cast and instance-of. This reduces the arm64 boot.oat on Nexus 9 by 1.1MiB. This CL provides the infrastructure and shows on the arm64 the gains that we can achieve by having fixed dex cache arrays' layout. To fully use this for the boot images, we need to implement the PC-relative addressing for other architectures. To achieve similar gains for apps, we need to move the dex cache arrays to a .bss section of the oat file. These changes will be implemented in subsequent CLs. (Also remove some compiler_driver.h dependencies to reduce incremental build times.) Change-Id: Ib1859fa4452d01d983fd92ae22b611f45a85d69b
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0b9203e7996ee1856f620f95d95d8a273c43a3df |
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23-Jan-2015 |
Andreas Gampe <agampe@google.com> |
ART: Some Quick cleanup Make several fields const in CompilationUnit. May benefit some Mir2Lir code that repeats tests, and in general immutability is good. Remove compiler_internals.h and refactor some other headers to reduce overly broad imports (and thus forced recompiles on changes). Change-Id: I898405907c68923581373b5981d8a85d2e5d185a
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a262f7707330dccfb50af6345813083182b61043 |
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25-Nov-2014 |
Ningsheng Jian <ningsheng.jian@arm.com> |
ARM: Combine multiply accumulate operations. Try to combine integer multiply and add(sub) into a MAC operation. For AArch64, also try to combine long type multiply and add(sub). Change-Id: Ic85812e941eb5a66abc355cab81a4dd16de1b66e
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65420b244f18a3492a342ee3edaefeb26aed4230 |
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27-Oct-2014 |
Matteo Franchin <matteo.franchin@arm.com> |
AArch64: Addressing Cortex-A53 erratum 835769. Some early revisions of the Cortex-A53 have an erratum (835769) whereby it is possible for a 64-bit multiply-accumulate instruction in AArch64 state to generate an incorrect result. The conditions which a portion of code must satisfy in order for the issue to be observed are somewhat complex, but all cases end with a memory (load, store, or prefetch) instruction followed immediately by the multiply-accumulate operation. This commit makes sure to insert a nop instruction before a 64-bit msub instruction, whenever the latter is preceded by a memory instruction. This behaviour should make it impossible for the Arm64 backend to generate a sequence of instructions which matches the erratum conditions. Change-Id: I0022eccd41180183c20231dab6e2671d001a204c
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6a3c1fcb4ba42ad4d5d142c17a3712a6ddd3866f |
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31-Oct-2014 |
Ian Rogers <irogers@google.com> |
Remove -Wno-unused-parameter and -Wno-sign-promo from base cflags. Fix associated errors about unused paramenters and implict sign conversions. For sign conversion this was largely in the area of enums, so add ostream operators for the effected enums and fix tools/generate-operator-out.py. Tidy arena allocation code and arena allocated data types, rather than fixing new and delete operators. Remove dead code. Change-Id: I5b433e722d2f75baacfacae4d32aef4a828bfe1b
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7c2ad5af0bdd3cc1069038f8e3422d99aeb5f44c |
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24-Sep-2014 |
Vladimir Marko <vmarko@google.com> |
Implement method calls using relative BL on ARM64. Change-Id: I9e5d0b6c100b6cddd6bbb7ab07cff77ab104ea31
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4163c53ce38a0f1f88bf3e8d26de9914da38498b |
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15-Jul-2014 |
Matteo Franchin <matteo.franchin@arm.com> |
AArch64: address some outstanding TODOs. Fix comments in arm64_lir.h. Rename Arm* to A64* and replace FWIDE, FUNWIDE, ... with WIDE, UNWIDE, ... Change-Id: I4900902e28463ea5e00e34ea40ddfc15704c0bfa
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5d7cdec7527f8043bf15e23a0041c40156727243 |
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18-Aug-2014 |
Zheng Xu <zheng.xu@arm.com> |
AArch64: Add tbz/tbnz and tst. Since the branch offset supported by tbz/tbnz is quite small(-32k ~ +32k), it will be replaced by tst and beq/bneq in the fix-up stage if the branch offset is too large. Change-Id: I4cace06bec6425e0f2e1f5f7c471eec08d06bca6
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f29ecd69af2743a425314baa4abd6c44d8d88649 |
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29-Jul-2014 |
Andreas Gampe <agampe@google.com> |
ART: Rework ARM64 entry sequence Try to fold one sub of SP in the ARM64 entry sequence. When the framesize is small, generate a sub over the full frame-size, and adjust the spill offsets accordingly. If the framesize is too large, use a pre-indexed store and fill upwards from there. Change-Id: I1c15ac6276fb62b8164372de02fd92437f605938
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2eba1fa7e9e5f91e18ae3778d529520bd2c78d55 |
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31-Jul-2014 |
Serban Constantinescu <serban.constantinescu@arm.com> |
AArch64: Add inlining support for ceil(), floor(), rint(), round() This patch adds inlining support for the following Math, StrictMath methods in the ARM64 backend: * double ceil(double) * double floor(double) * double rint(double) * long round(double) * int round(float) Also some cleanup. Change-Id: I9f5a2f4065b1313649f4b0c4380b8176703c3fe1 Signed-off-by: Serban Constantinescu <serban.constantinescu@arm.com>
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b551fdcda9eb128c80de37c4fb978968bec6d4b3 |
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25-Jul-2014 |
Zheng Xu <zheng.xu@arm.com> |
AArch64: Clean up CalleeSaveMethod frame and the use of temp registers. CalleeSaveMethod frame size changes : SaveAll : 368 -> 176 RefOnly : 176 -> 96 RefsAndArgs : 304 -> 224 JNI register spill size changes : 160 -> 88 In the transition assembly, use registers following the rules: 1. x0-x7 as temp/argument registers. 2. IP0, IP1 as scratch registers. 3. After correct type of callee-save-frame has been setup, all registers are scratch-able(probably except xSELF and xSUSPEND). 4. When restore callee-save-frame, IP0 and IP1 should be untouched. 5. From C to managed code, we assume all callee save register in AAPCS will be restored by managed code except x19(SUSPEND). In quick compiler: 1. Use IP0, IP1 as scratch register. 2. Use IP1 as hidden argument register(IP0 will be scratched by trampoline.) Change-Id: I05ed9d418b01b9e87218a7608536f57e7a286e4c
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48f5c47907654350ce30a8dfdda0e977f5d3d39f |
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27-Jun-2014 |
Hans Boehm <hboehm@google.com> |
Replace memory barriers to better reflect Java needs. Replaces barriers that enforce ordering of one access type (e.g. Load) with respect to another (e.g. store) with more general ones that better reflect both Java requirements and actual hardware barrier/fence instructions. The old code was inconsistent and unclear about which barriers implied which others. Sometimes multiple barriers were generated and then eliminated; sometimes it was assumed that certain barriers implied others. The new barriers closely parallel those in C++11, though, for now, we use something closer to the old naming. Bug: 14685856 Change-Id: Ie1c80afe3470057fc6f2b693a9831dfe83add831
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7c6c2ac4252ac31b42967e0f0233e8d32c5b5abe |
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01-Jul-2014 |
Matteo Franchin <matteo.franchin@arm.com> |
Aarch64: easy division and remainder for long ints. Also adding test 701 to test easy division and remainder for int and long integers. Change-Id: I8212c84e4d9eb3e9f3f4f1f1c3418537bb13dc55
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873c371eea7d8700c8037d790de168b5ed7c20d0 |
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11-Jul-2014 |
Stuart Monteith <stuart.monteith@arm.com> |
ART: Fix GenSelect for ARM64 Add CSINV and replace CSNEG in GenSelect. Some tests were failing in 083-complier-regression as CSNEG was used instead of CSINV. CSNEG on xzr yields 0, whereas CSINV negates the bits and yields -1, which was the intention. Change-Id: I60557e34483f98310f7d33f18d8db203fba6e78f Signed-off-by: Stuart Monteith <stuart.monteith@arm.com>
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23abec955e2e733999a1e2c30e4e384e46e5dde4 |
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02-Jul-2014 |
Serban Constantinescu <serban.constantinescu@arm.com> |
AArch64: Add few more inline functions This patch adds inlining support for the following functions: * Math.max/min(long, long) * Math.max/min(float, float) * Math.max/min(double, double) * Integer.reverse(int) * Long.reverse(long) Change-Id: Ia2b1619fd052358b3a0d23e5fcbfdb823d2029b9 Signed-off-by: Serban Constantinescu <serban.constantinescu@arm.com>
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4b537a851b686402513a7c4a4e60f5457bb8d7c1 |
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01-Jul-2014 |
Andreas Gampe <agampe@google.com> |
ART: Quick compiler: More size checks, add TargetReg variants Add variants for TargetReg for requesting specific register usage, e.g., wide and ref. More register size checks. With code adapted from https://android-review.googlesource.com/#/c/98605/. Change-Id: I852d3be509d4dcd242c7283da702a2a76357278d
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baa7c88a34fdfd230a2a383c2e388945f4d907b6 |
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30-Jun-2014 |
Zheng Xu <zheng.xu@arm.com> |
AArch64: Rename A64_/A32_ register prefix to x/w. A64/A32 look like architecture name, but they are all for arm64. Use lower-case to name the registers defined in "ARM ARM" which can also be directly used in assembly file. Use upper-case to name the registers which are other aliases. Change-Id: I0ac38ed75f977fdc362288b01179b84feaee5614
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c6301bcfbefa1c320f922d2209caee3481dc1aa2 |
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27-Jun-2014 |
Andreas Gampe <agampe@google.com> |
ART: ARM64 fp return reg locations are FP Change-Id: Ica14b63ebde8efda113a146939309a6c37adc9aa
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de68676b24f61a55adc0b22fe828f036a5925c41 |
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24-Jun-2014 |
Andreas Gampe <agampe@google.com> |
Revert "ART: Split out more cases of Load/StoreRef, volatile as parameter" This reverts commit 2689fbad6b5ec1ae8f8c8791a80c6fd3cf24144d. Breaks the build. Change-Id: I9faad4e9a83b32f5f38b2ef95d6f9a33345efa33
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3c12c512faf6837844d5465b23b9410889e5eb11 |
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24-Jun-2014 |
Andreas Gampe <agampe@google.com> |
Revert "Revert "ART: Split out more cases of Load/StoreRef, volatile as parameter"" This reverts commit de68676b24f61a55adc0b22fe828f036a5925c41. Fixes an API comment, and differentiates between inserting and appending. Change-Id: I0e9a21bb1d25766e3cbd802d8b48633ae251a6bf
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2689fbad6b5ec1ae8f8c8791a80c6fd3cf24144d |
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23-Jun-2014 |
Andreas Gampe <agampe@google.com> |
ART: Split out more cases of Load/StoreRef, volatile as parameter Splits out more cases of ref registers being loaded or stored. For code clarity, adds volatile as a flag parameter instead of a separate method. On ARM64, continue cleanup. Add flags to print/fatal on size mismatches. Change-Id: I30ed88433a6b4ff5399aefffe44c14a5e6f4ca4e
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9f975bfe091e9592a1b6b5b46d224ec04b1183b6 |
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19-Jun-2014 |
Andreas Gampe <agampe@google.com> |
ART: Change rrr add and sub for ARM64 OpRegRegImm will fall back to loading a constant into a register and then doing the operation with three registers. That is, for example, the case when we allocate large stack frames. However, the currently chosen operations are add/sub shifted, which does *not* allow to specify SP (x31 will be interpreted as xzr). Switch to add/sub extended. There won't be a practical difference, as we do not call with anything other than 0 shift. Change-Id: I2b78df9f044d2963e3e890777c855b339952f9f4
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47b31aa855379471c06735b738396fa76e7c1988 |
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19-Jun-2014 |
Andreas Gampe <agampe@google.com> |
ART: Start implementation of OpRegRegRegExtend for ARM64 We need a sign-extending add for packed-switch and sparse-switch, as the 32b values are signed offsets. This starts an implementation that is sufficient for the use cases. Change-Id: Ib5bae24b902077346a97d5e9e061533f9cdfcdb0
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f8ec48e8eff0050de1451fc8e9c3a71c26d5ce7e |
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06-Jun-2014 |
Stuart Monteith <stuart.monteith@arm.com> |
ART: arm64 explicit stack overflow checks Implement only the explicit checks for the quick backend for arm64. Implicit checks require fault handlers, which are currently unimplemented. CMN + CMP have extended versions implemented for comparisons against the stack pointer. More extended opcode implementations will need to follow. Change-Id: I8db297aec73df818b20fe410297800c886701c76
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169489b4f4be8c5dd880ba6f152948324d22ff79 |
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11-Jun-2014 |
Serban Constantinescu <serban.constantinescu@arm.com> |
AArch64: Add support for inlined methods This patch adds support for Arm64 inlined methods. Change-Id: Ic6aeed6d2d32f65cd1e63cf482f83cdcf958798a
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8dea81ca9c0201ceaa88086b927a5838a06a3e69 |
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06-Jun-2014 |
Vladimir Marko <vmarko@google.com> |
Rewrite use/def masks to support 128 bits. Reduce LIR memory usage by holding masks by pointers in the LIR rather than directly and using pre-defined const masks for the common cases, allocating very few on the arena. Change-Id: I0f6d27ef6867acd157184c8c74f9612cebfe6c16
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ffddfdf6fec0b9d98a692e27242eecb15af5ead2 |
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03-Jun-2014 |
Tim Murray <timmurray@google.com> |
DO NOT MERGE Merge ART from AOSP to lmp-preview-dev. Change-Id: I0f578733a4b8756fd780d4a052ad69b746f687a9
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ed65c5e982705defdb597d94d1aa3f2997239c9b |
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22-May-2014 |
Serban Constantinescu <serban.constantinescu@arm.com> |
AArch64: Enable LONG_* and INT_* opcodes. This patch fixes some of the issues with LONG and INT opcodes. The patch has been tested and passes all the dalvik tests except for 018 and 107. Change-Id: Idd1923ed935ee8236ab0c7e5fa969eaefeea8708 Signed-off-by: Serban Constantinescu <serban.constantinescu@arm.com>
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b01bf15d18f9b08d77e7a3c6e2897af0e02bf8ca |
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14-May-2014 |
buzbee <buzbee@google.com> |
64-bit temp register support. Add a 64-bit temp register allocation path. The recent physical register handling rework supports multiple views of the same physical register (or, such as for Arm's float/double regs, different parts of the same physical register). This CL adds a 64-bit core register view for 64-bit targets. In short, each core register will have a 64-bit name, and a 32-bit name. The different views will be kept in separate register pools, but aliasing will be tracked. The core temp register allocation routines will be largely identical - except for 32-bit targets, which will continue to use pairs of 32-bit core registers for holding long values. Change-Id: I8f118e845eac7903ad8b6dcec1952f185023c053
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9cdf48e03c302e03e2ec118a22cbdfae460b1665 |
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20-May-2014 |
buzbee <buzbee@google.com> |
Arm64 - update fp callee save base Hit commit button too quickly - this should have been part of CL 95013. Change-Id: I4a733414db74d6e9cab2d8fbe2eb9b398fff3f45
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bc6d197cdb02eeac0c98ec4ed37f530b003a4e7a |
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13-May-2014 |
Matteo Franchin <matteo.franchin@arm.com> |
AArch64: fixes in A64 code generation. - Disabled special method compilation, as it requires hard-float ABI, - Disabled suspend checks, as runtime is not yet ready (e.g. trampolines are not setting the suspend register, etc), - Changing definition of zero register (the zero register has now 0x3f as its register number), - Fixing some issues with handling of cmp instructions in the assembler: we now use the shift-register rather than the extended-register variant of cmp and cmn, - Partially fixing register setup (register sN is now mapped to dN), - Fixing and completing implementation of register spills/unspills, - Fixing LoadBaseDispBody() and StoreBaseDispBody(). Change-Id: Ia49ba48b6ca0f782380066345b7a198cb6c1dc1d
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c830430ed65497c2268649d8e78121364e31b184 |
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15-May-2014 |
Zheng Xu <zheng.xu@arm.com> |
AArch64: Fix quick compiler monitor implementation. Also with some small fixes : 1. Enable some dex byte code to compile. 2. Copy the register definition from runtime.cc. 3. A quick fix for "cmp Wn, Wm" in the assembler. 4. Optimise GenMoveException a bit by using xzr. 5. Fix improper use of StoreValueWide() on 32-bit value in FlushIns(). 6. Fix one debug assert in the assembler. It can pass all cases in run-all-test, except 044 which also fails with the interpreter. Change-Id: I9cc0253f1039c78d5100640235ac33e884b02560
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2f244e9faccfcca68af3c5484c397a01a1c3a342 |
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08-May-2014 |
Andreas Gampe <agampe@google.com> |
ART: Add more ThreadOffset in Mir2Lir and backends This duplicates all methods with ThreadOffset parameters, so that both ThreadOffset<4> and ThreadOffset<8> can be handled. Dynamic checks against the compilation unit's instruction set determine which pointer size to use and therefore which methods to call. Methods with unsupported pointer sizes should fatally fail, as this indicates an issue during method selection. Change-Id: Ifdb445b3732d3dc5e6a220db57374a55e91e1bf6
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e45fb9e7976c8462b94a58ad60b006b0eacec49f |
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06-May-2014 |
Matteo Franchin <matteo.franchin@arm.com> |
AArch64: Change arm64 backend to produce A64 code. The arm backend clone is changed to produce A64 code. At the moment this backend can only compile simple methods (both leaf and non-leaf). Most of the work on the assembler (assembler_arm64.cc) has been done. Some work on the LIR generation layer (functions such as OpRegRegImm & friends) is still necessary. The register allocator still needs to be adapted to the A64 instruction set (it is mostly unchanged from the arm backend). Offsets for helpers in gen_invoke.cc still need to be changed to work on 64-bit. Change-Id: I388f99eeb832857981c7d9d5cb5b71af64a4b921
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43ec8737d8356dbff0a90bee521fb0e73438da47 |
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31-Mar-2014 |
Matteo Franchin <matteo.franchin@arm.com> |
AArch64: Added arm64 quick backend as an arm clone. Created a new directory arm64 under compiler/dex/quick which contains a copy of the 32-bit arm backend. In following CLs, this code will be replaced/modified to support Aarch64. Change-Id: I06c468db8d588e339eecf4d7d85276d5e334a17a
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