| 3d21bdf8894e780d349c481e5c9e29fe1556051c |
|
22-Apr-2015 |
Mathieu Chartier <mathieuc@google.com> |
Move mirror::ArtMethod to native
Optimizing + quick tests are passing, devices boot.
TODO: Test and fix bugs in mips64.
Saves 16 bytes per most ArtMethod, 7.5MB reduction in system PSS.
Some of the savings are from removal of virtual methods and direct
methods object arrays.
Bug: 19264997
(cherry picked from commit e401d146407d61eeb99f8d6176b2ac13c4df1e33)
Change-Id: I622469a0cfa0e7082a2119f3d6a9491eb61e3f3d
Fix some ArtMethod related bugs
Added root visiting for runtime methods, not currently required
since the GcRoots in these methods are null.
Added missing GetInterfaceMethodIfProxy in GetMethodLine, fixes
--trace run-tests 005, 044.
Fixed optimizing compiler bug where we used a normal stack location
instead of double on ARM64, this fixes the debuggable tests.
TODO: Fix JDWP tests.
Bug: 19264997
Change-Id: I7c55f69c61d1b45351fd0dc7185ffe5efad82bd3
ART: Fix casts for 64-bit pointers on 32-bit compiler.
Bug: 19264997
Change-Id: Ief45cdd4bae5a43fc8bfdfa7cf744e2c57529457
Fix JDWP tests after ArtMethod change
Fixes Throwable::GetStackDepth for exception event detection after
internal stack trace representation change.
Adds missing ArtMethod::GetInterfaceMethodIfProxy call in case of
proxy method.
Bug: 19264997
Change-Id: I363e293796848c3ec491c963813f62d868da44d2
Fix accidental IMT and root marking regression
Was always using the conflict trampoline. Also included fix for
regression in GC time caused by extra roots. Most of the regression
was IMT.
Fixed bug in DumpGcPerformanceInfo where we would get SIGABRT due to
detached thread.
EvaluateAndApplyChanges:
From ~2500 -> ~1980
GC time: 8.2s -> 7.2s due to 1s less of MarkConcurrentRoots
Bug: 19264997
Change-Id: I4333e80a8268c2ed1284f87f25b9f113d4f2c7e0
Fix bogus image test assert
Previously we were comparing the size of the non moving space to
size of the image file.
Now we properly compare the size of the image space against the size
of the image file.
Bug: 19264997
Change-Id: I7359f1f73ae3df60c5147245935a24431c04808a
[MIPS64] Fix art_quick_invoke_stub argument offsets.
ArtMethod reference's size got bigger, so we need to move other args
and leave enough space for ArtMethod* and 'this' pointer.
This fixes mips64 boot.
Bug: 19264997
Change-Id: I47198d5f39a4caab30b3b77479d5eedaad5006ab
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| 41b175aba41c9365a1c53b8a1afbd17129c87c14 |
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19-May-2015 |
Vladimir Marko <vmarko@google.com> |
ART: Clean up arm64 kNumberOfXRegisters usage.
Avoid undefined behavior for arm64 stemming from 1u << 32 in
loops with upper bound kNumberOfXRegisters.
Create iterators for enumerating bits in an integer either
from high to low or from low to high and use them for
<arch>Context::FillCalleeSaves() on all architectures.
Refactor runtime/utils.{h,cc} by moving all bit-fiddling
functions to runtime/base/bit_utils.{h,cc} (together with
the new bit iterators) and all time-related functions to
runtime/base/time_utils.{h,cc}. Improve test coverage and
fix some corner cases for the bit-fiddling functions.
Bug: 13925192
(cherry picked from commit 80afd02024d20e60b197d3adfbb43cc303cf29e0)
Change-Id: I905257a21de90b5860ebe1e39563758f721eab82
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| 2cebb24bfc3247d3e9be138a3350106737455918 |
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22-Apr-2015 |
Mathieu Chartier <mathieuc@google.com> |
Replace NULL with nullptr
Also fixed some lines that were too long, and a few other minor
details.
Change-Id: I6efba5fb6e03eb5d0a300fddb2a75bf8e2f175cb
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| ab4a2f5995b79c2b5b28c91b419a2c91cb88e377 |
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11-Mar-2015 |
Guillaume "Vermeille" Sanchez <guillaumesa@google.com> |
Forbid the use of shifts in ShifterOperand in Thumb2
Change-Id: I4b3b4d90f11f2dd0c9a274b724051fa98982fb19
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| b7f2be9238e49db5d163d23e956d1bbec25da013 |
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17-Mar-2015 |
Calin Juravle <calin@google.com> |
Revert "Forbid the use of shifts in ShifterOperand in Thumb2"
This reverts commit bada8b0f0a10bd32d6cb87ed4e57f2aa3d7c03c2.
Change-Id: Ic89c76367c8ab91cfb5d1510789ac2e352922da8
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| bada8b0f0a10bd32d6cb87ed4e57f2aa3d7c03c2 |
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11-Mar-2015 |
Guillaume "Vermeille" Sanchez <guillaumesa@google.com> |
Forbid the use of shifts in ShifterOperand in Thumb2
Change-Id: Ib141f53e52cce3032a42fbc991303e227c98820b
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| ffe8a577a4c644a2c5387f1e8efe92fb0efac43f |
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11-Feb-2015 |
Nicolas Geoffray <ngeoffray@google.com> |
Optimize double/float immediate loading on arm.
Also reserve a D register for temp.
Change-Id: I6584d9005b0f5685c3afcd8e9153b4c87b56aa8e
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| f7a0c4e421b5edaad5b7a15bfff687da28d0b287 |
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10-Feb-2015 |
Nicolas Geoffray <ngeoffray@google.com> |
Improve ParallelMoveResolver to work with pairs.
Change-Id: Ie2a540ffdb78f7f15d69c16a08ca2d3e794f65b9
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| 840e5461a85f8908f51e7f6cd562a9129ff0e7ce |
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07-Jan-2015 |
Nicolas Geoffray <ngeoffray@google.com> |
Implement double and float support for arm in register allocator.
The basic approach is:
- An instruction that needs two registers gets two intervals.
- When allocating the low part, we also allocate the high part.
- When splitting a low (or high) interval, we also split the high
(or low) equivalent.
- Allocation follows the (S/D register) requirement that low
registers are always even and the high equivalent is low + 1.
Change-Id: I06a5148e05a2ffc7e7555d08e871ed007b4c2797
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| 52c489645b6e9ae33623f1ec24143cde5444906e |
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16-Dec-2014 |
Calin Juravle <calin@google.com> |
[optimizing compiler] Add support for volatile
- for backends: arm, x86, x86_64
- added necessary instructions to assemblies
- clean up code gen for field set/get
- fixed InstructionDataEquals for some instructions
- fixed comments in compiler_enums
* 003-opcode test verifies basic volatile functionality
Change-Id: I144393efa312dfb2c332cb84056b00edffee338a
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| 3bcc8ea079d867f26622defd0611d134a3b4ae49 |
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28-Nov-2014 |
Nicolas Geoffray <ngeoffray@google.com> |
Don't use CanHoldArm in the code generator.
CanHoldArm was ARM32 specific. Instead use a virtual
Assembler::ShifterOperandCanHold that both thumb2 and arm32
implement.
Change-Id: I33794a93caf02ee5d78d32a8471d9fd6fe4f0a00
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| 981e45424f52735b1c61ae0eac7e299ed313f8db |
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14-Nov-2014 |
Roland Levillain <rpl@google.com> |
Add support for int-to-char in the optimizing compiler.
- Add support for the int-to-char Dex instruction in the
optimizing compiler.
- Implement the ARM and Thumb-2 UBFX instructions and add
tests for them.
- Generate x86, x86-64 and ARM (but not ARM64) code for
byte to char, short to char, int to char (and char to
char!) HTypeConversion nodes.
- Add related tests to test/422-type-conversion.
Change-Id: I5cd4c6d86f0f6a966c059715b98db35cc8f9de76
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| 51d3fc40637fc73d4156ad617cd451b844cbb75e |
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13-Nov-2014 |
Roland Levillain <rpl@google.com> |
Add support for int-to-byte in the optimizing compiler.
- Add support for the int-to-byte Dex instruction in the
optimizing compiler.
- Implement the ARM and Thumb-2 SBFX instructions.
- Generate x86, x86-64 and ARM (but not ARM64) code for
char to byte, short to byte and int to byte
HTypeConversion nodes.
- Add related tests to test/422-type-conversion.
Change-Id: Ic8b8911b90d4b5281fad15bcee96bc3ee85dc577
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| 6a3c1fcb4ba42ad4d5d142c17a3712a6ddd3866f |
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31-Oct-2014 |
Ian Rogers <irogers@google.com> |
Remove -Wno-unused-parameter and -Wno-sign-promo from base cflags.
Fix associated errors about unused paramenters and implict sign conversions.
For sign conversion this was largely in the area of enums, so add ostream
operators for the effected enums and fix tools/generate-operator-out.py.
Tidy arena allocation code and arena allocated data types, rather than fixing
new and delete operators.
Remove dead code.
Change-Id: I5b433e722d2f75baacfacae4d32aef4a828bfe1b
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| 19a19cffd197a28ae4c9c3e59eff6352fd392241 |
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22-Oct-2014 |
Nicolas Geoffray <ngeoffray@google.com> |
Add support for static fields in optimizing compiler.
Change-Id: Id2f010589e2bd6faf42c05bb33abf6816ebe9fa9
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| 13735955f39b3b304c37d2b2840663c131262c18 |
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08-Oct-2014 |
Ian Rogers <irogers@google.com> |
stdint types all the way!
Change-Id: I4e4ef3a2002fc59ebd9097087f150eaf3f2a7e08
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| 96f89a290eb67d7bf4b1636798fa28df14309cc7 |
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11-Jul-2014 |
Nicolas Geoffray <ngeoffray@google.com> |
Add assembly operations with constants in optimizing compiler.
Change-Id: I5bcc35ab50d4457186effef5592a75d7f4e5b65f
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| 45fdb93f04b981f70f7b6d98949ab3986b7331f8 |
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25-Jun-2014 |
Dave Allison <dallison@google.com> |
Support additional instructions in ARM and thumb assemblers
This adds the following support for the ARM and thumb assemblers:
1. Shifting by a register.
2. LDR/STR with a register offset, possibly shifted.
3. LDR(literal).
4. STR PC relative.
Also adds tests for them in the thumb assembler gtest.
Change-Id: Ie467e3c1d06b699cacbdef3482ed9a92e4f1809b
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| 65fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7 |
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28-Apr-2014 |
Dave Allison <dallison@google.com> |
Thumb2 assembler for JNI compiler and optimizing compiler
This provides a programmatic assembler for the thumb2 instruction set for
ARM. The interface is the same as the ARM assembler and the ARM assembler has
been moved into Arm32Assembler. The assembler handles most 16 and 32 bit instructions
and also allows relocations due to branch expansion. It will also rewrite cbz/cbnz
instructions if they go out of range.
It also changes the JNI compiler to use the thumb2 assembler as opposed
to forcing it to use ARM32. The trampoline compiler still uses ARM due to the
way it returns the address of its generated code. A trampoline in thumb2 is the
same size as that in ARM anyway (8 bytes).
Provides gtest for testing the thumb2 instruction output. This gtest only runs
on the host as it uses arm-eabi-objdump to disassemble the generated code. On the
target the output is not checked but the assembler will still be run to perform
all its checks.
Change-Id: Icd9742b6f13541bec5b23097896727392e3a6fb6
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| eb8167a4f4d27fce0530f6724ab8032610cd146b |
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08-May-2014 |
Mathieu Chartier <mathieuc@google.com> |
Add Handle/HandleScope and delete SirtRef.
Delete SirtRef and replaced it with Handle. Handles are value types
which wrap around StackReference*.
Renamed StackIndirectReferenceTable to HandleScope.
Added a scoped handle wrapper which wraps around an Object** and
restores it in its destructor.
Renamed Handle::get -> Get.
Bug: 8473721
Change-Id: Idbfebd4f35af629f0f43931b7c5184b334822c7a
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| dd7624d2b9e599d57762d12031b10b89defc9807 |
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15-Mar-2014 |
Ian Rogers <irogers@google.com> |
Allow mixing of thread offsets between 32 and 64bit architectures.
Begin a more full implementation x86-64 REX prefixes.
Doesn't implement 64bit thread offset support for the JNI compiler.
Change-Id: If9af2f08a1833c21ddb4b4077f9b03add1a05147
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| fca82208f7128fcda09b6a4743199308332558a2 |
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21-Mar-2014 |
Dmitry Petrochenko <dmitry.petrochenko@intel.com> |
x86_64: JNI compiler
Passed all tests from jni_compiler_test and art/test on host with jni_copiler.
Incoming argument spill is enabled, entry_spills refactored. Now each entry spill
contains data type size (4 or 8) and offset which should be used for spill.
Assembler REX support implemented in opcodes used in JNI compiler.
Please note, JNI compiler is not enabled by default yet (see compiler_driver.cc:1875).
Change-Id: I5fd19cca72122b197aec07c3708b1e80c324be44
Signed-off-by: Dmitry Petrochenko <dmitry.petrochenko@intel.com>
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| 834b394ee759ed31c5371d8093d7cd8cd90014a8 |
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31-Jul-2013 |
Brian Carlstrom <bdc@google.com> |
Merge remote-tracking branch 'goog/dalvik-dev' into merge-art-to-dalvik-dev
Change-Id: I323e9e8c29c3e39d50d9aba93121b26266c52a46
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| 166db04e259ca51838c311891598664deeed85ad |
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26-Jul-2013 |
Ian Rogers <irogers@google.com> |
Move assembler out of runtime into compiler/utils.
Other directory layout bits of clean up. There is still work to separate quick
and portable in some files (e.g. argument visitor, proxy..).
Change-Id: If8fecffda8ba5c4c47a035f0c622c538c6b58351
|