/art/runtime/arch/arm64/ |
H A D | memcmp16_arm64.S | 45 #define mask x13 define 79 mov mask, #~0 80 lsl mask, mask, limit 81 bic data1, data1, mask 82 bic data2, data2, mask 93 // Create a 16b mask 94 mov mask, #0xFFFF 99 and data1, data1, mask 100 and data2, data2, mask [all...] |
/art/compiler/dex/quick/ |
H A D | resource_mask.cc | 145 const ResourceMask* ResourceMaskCache::GetMask(const ResourceMask& mask) { argument 153 if ((mask.masks_[0] >> 32) == 0u && (mask.masks_[1] & ~kAllowedSpecialBits.masks_[1]) == 0u) { 155 uint32_t low_regs = static_cast<uint32_t>(mask.masks_[0]); 157 if (low_regs_without_lowest == 0u && IsPowerOfTwo(mask.masks_[1])) { 158 // 0 or 1 register, 0 or 1 bit from kAllowedBits. Use a pre-defined mask. 159 size_t index = (mask.masks_[1] != 0u) ? CLZ(mask.masks_[1]) : 0u; 163 } else if (IsPowerOfTwo(low_regs_without_lowest) && mask.masks_[1] == 0u) { 164 // 2 registers and no other flags. Use predefined mask i [all...] |
H A D | mir_to_lir-inl.h | 145 inline void Mir2Lir::SetupRegMask(ResourceMask* mask, int reg) { argument 149 *mask = mask->Union(reginfo_map_[reg]->DefUseMask()); 155 inline void Mir2Lir::ClearRegMask(ResourceMask* mask, int reg) { argument 159 *mask = mask->ClearBits(reginfo_map_[reg]->DefUseMask()); 163 * Set up the proper fields in the resource mask 187 /* Set up the mask for resources. */
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H A D | codegen_util.cc | 146 ResourceMask mask; local 152 mask = **mask_ptr; 154 mask.ClearBits(kEncodeMem); 159 mask.SetBit(ResourceMask::kLiteral); 162 mask.SetBit(ResourceMask::kDalvikReg); 165 mask.SetBit(ResourceMask::kHeapRef); 170 mask.SetBit(ResourceMask::kMustNotAlias); 175 *mask_ptr = mask_cache_.GetMask(mask);
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H A D | ralloc_util.cc | 45 Mir2Lir::RegisterInfo::RegisterInfo(RegStorage r, const ResourceMask& mask) argument 47 s_reg_(INVALID_SREG), def_use_mask_(mask), master_(this), def_start_(nullptr), 129 // Add an entry for InvalidReg with zero'd mask.
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/art/disassembler/ |
H A D | disassembler_mips.cc | 30 uint32_t mask; member in struct:art::mips::MipsInstruction 36 return (instruction & mask) == value;
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H A D | disassembler_arm.cc | 1826 uint32_t mask = opB; local 1831 size_t count = 3 - CTZ(mask); 1835 bool positive_mask = ((mask & (1 << (3 - i))) != 0);
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/art/runtime/gc/accounting/ |
H A D | space_bitmap-inl.h | 38 const uintptr_t mask = OffsetToMask(offset); local 45 if ((old_word & mask) != 0) { 49 } while (!atomic_entry->CompareExchangeWeakSequentiallyConsistent(old_word, old_word | mask)); 165 const uintptr_t mask = OffsetToMask(offset); local 170 *address = old_word | mask; 172 *address = old_word & ~mask; 175 return (old_word & mask) != 0;
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/art/runtime/gc/allocator/ |
H A D | rosalloc-inl.h | 137 const uint32_t mask = 1U << ffz; local 140 DCHECK_EQ(*alloc_bitmap_ptr & mask, 0U); 141 *alloc_bitmap_ptr |= mask; 142 DCHECK_NE(*alloc_bitmap_ptr & mask, 0U);
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H A D | rosalloc.cc | 900 const uint32_t mask = 1U << vec_off; local 901 DCHECK_NE(*vec & mask, 0U); 902 *vec &= ~mask; 903 DCHECK_EQ(*vec & mask, 0U); 957 // Only not all free if a bit other than the mask bits are set. 1031 const uint32_t mask = 1U << vec_off; local 1032 DCHECK_EQ(*vec & mask, 0U); 1033 *vec |= mask; 1034 DCHECK_NE(*vec & mask, 0U); 1064 // Make sure the last word is equal to the mask, al [all...] |
/art/runtime/ |
H A D | stack_map.cc | 157 void StackMap::SetRegisterMask(const CodeInfo& info, uint32_t mask) { argument 161 mask); 260 // TODO: Display the bit mask of live Dex registers.
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H A D | art_method.h | 148 uint32_t mask = kAccFastNative | kAccNative; local 149 return (GetAccessFlags() & mask) == mask;
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H A D | mem_map.cc | 97 // mask = 0000111111111110000 118 constexpr uintptr_t mask = mask_ones & ~(kPageSize - 1); local 121 return (input & mask) + LOW_MEM_START; 128 // The lower 8B are taken for the stack guard. Use the upper 8B (with mask).
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H A D | stack.cc | 439 uint64_t mask = 0xffffffff; local 441 mask = mask << 32; 445 full_new_value = static_cast<uintptr_t>((old_reg_val_as_wide & mask) | new_vreg_portion);
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/art/compiler/dex/quick/arm/ |
H A D | target_arm.cc | 515 void ArmMir2Lir::DumpResourceMask(LIR* arm_lir, const ResourceMask& mask, const char* prefix) { argument 519 if (mask.Equals(kEncodeAll)) { 526 if (mask.HasBit(i)) { 532 if (mask.HasBit(ResourceMask::kCCode)) { 535 if (mask.HasBit(ResourceMask::kFPStatus)) { 540 if (arm_lir && (mask.HasBit(ResourceMask::kDalvikReg))) { 545 if (mask.HasBit(ResourceMask::kLiteral)) { 549 if (mask.HasBit(ResourceMask::kHeapRef)) { 552 if (mask.HasBit(ResourceMask::kMustNotAlias)) { 615 // Singles should show a single 32-bit mask bi [all...] |
H A D | int_arm.cc | 51 int mask; local 75 mask = (mask3 << 3) | (mask2 << 2) | (mask1 << 1) | 77 return NewLIR2(kThumb2It, code, mask); 81 int mask; local 105 mask = (mask3 << 3) | (mask2 << 2) | (mask1 << 1) | 107 it->operands[1] = mask; 112 // we could check that the number of instructions matches the mask
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/art/compiler/dex/quick/arm64/ |
H A D | target_arm64.cc | 149 // Check if the shape mask is zero (i.e. invalid). 313 unsigned mask = (unsigned)(width - 1); local 314 DCHECK_NE((imm_s & mask), mask); 315 uint64_t bits = bit_mask((imm_s & mask) + 1); 316 return RepeatBitsAcrossReg(is_wide, RotateRight(bits, imm_r & mask, width), width); 546 void Arm64Mir2Lir::DumpResourceMask(LIR* arm_lir, const ResourceMask& mask, const char* prefix) { argument 550 if (mask.Equals(kEncodeAll)) { 557 if (mask.HasBit(i)) { 563 if (mask [all...] |
H A D | utility_arm64.cc | 259 uint64_t mask = (UINT64_C(1) << (width >> 1)) - 1; local 260 if ((value & mask) == ((value >> (width >> 1)) & mask)) {
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/art/compiler/dex/quick/mips/ |
H A D | target_mips.cc | 465 void MipsMir2Lir::DumpResourceMask(LIR *mips_lir, const ResourceMask& mask, const char *prefix) { argument 469 if (mask.Equals(kEncodeAll)) { 476 if (mask.HasBit(i)) { 482 if (mask.HasBit(ResourceMask::kCCode)) { 485 if (mask.HasBit(ResourceMask::kFPStatus)) { 489 if (mips_lir && (mask.HasBit(ResourceMask::kDalvikReg))) { 494 if (mask.HasBit(ResourceMask::kLiteral)) { 498 if (mask.HasBit(ResourceMask::kHeapRef)) { 501 if (mask.HasBit(ResourceMask::kMustNotAlias)) { 701 // Singles should show a single 32-bit mask bi 848 uint32_t mask = core_spill_mask_; local 868 uint32_t mask = core_spill_mask_; local [all...] |
/art/compiler/dex/ |
H A D | type_inference.h | 341 bool MergeBits(Type src_type, uint32_t mask) { argument 342 uint32_t new_bits = raw_bits_ | (src_type.raw_bits_ & mask);
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/art/compiler/optimizing/ |
H A D | code_generator.h | 186 uint32_t mask = 0; local 188 mask |= (1 << registers[i]); 190 return mask;
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H A D | intrinsics_arm.cc | 268 Register mask = locations->GetTemp(0).AsRegister<Register>(); local 278 __ Asr(mask, in_reg_hi, 31); 279 __ adds(out_reg_lo, in_reg_lo, ShifterOperand(mask)); 280 __ adc(out_reg_hi, in_reg_hi, ShifterOperand(mask)); 281 __ eor(out_reg_lo, mask, ShifterOperand(out_reg_lo)); 282 __ eor(out_reg_hi, mask, ShifterOperand(out_reg_hi)); 287 __ Asr(mask, in_reg, 31); 288 __ add(out_reg, in_reg, ShifterOperand(mask)); 289 __ eor(out_reg, mask, ShifterOperand(out_reg));
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H A D | intrinsics_x86.cc | 1643 static void SwapBits(Register reg, Register temp, int32_t shift, int32_t mask, argument 1646 Immediate imm_mask(mask);
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H A D | intrinsics_x86_64.cc | 285 locations->AddTemp(Location::RequiresFpuRegister()); // FP reg to hold mask. 298 // TODO: Can mask directly with constant area using pand if we can guarantee 353 CpuRegister mask = locations->GetTemp(0).AsRegister<CpuRegister>(); local 356 // Create mask. 357 __ movq(mask, out); 358 __ sarq(mask, Immediate(63)); 359 // Add mask. 360 __ addq(out, mask); 361 __ xorq(out, mask); 363 // Create mask 1506 SwapBits(CpuRegister reg, CpuRegister temp, int32_t shift, int32_t mask, X86_64Assembler* assembler) argument 1551 SwapBits64(CpuRegister reg, CpuRegister temp, CpuRegister temp_mask, int32_t shift, int64_t mask, X86_64Assembler* assembler) argument [all...] |
/art/compiler/dex/quick/x86/ |
H A D | target_x86.cc | 422 void X86Mir2Lir::DumpResourceMask(LIR *x86LIR, const ResourceMask& mask, const char *prefix) { argument 426 if (mask.Equals(kEncodeAll)) { 433 if (mask.HasBit(i)) { 439 if (mask.HasBit(ResourceMask::kCCode)) { 443 if (x86LIR && (mask.HasBit(ResourceMask::kDalvikReg))) { 448 if (mask.HasBit(ResourceMask::kLiteral)) { 452 if (mask.HasBit(ResourceMask::kHeapRef)) { 455 if (mask.HasBit(ResourceMask::kMustNotAlias)) { 690 // Singles should show a single 32-bit mask bit, at first referring to the low half. 704 // 32bit W should show a single 32-bit mask bi 740 uint32_t mask = core_spill_mask_ & ~(1 << rs_rRET.GetRegNum()); local 761 uint32_t mask = core_spill_mask_ & ~(1 << rs_rRET.GetRegNum()); local 779 uint32_t mask = fp_spill_mask_; local 795 uint32_t mask = fp_spill_mask_; local 2162 int mask = 0; local [all...] |