Searched refs:cond (Results 1 - 25 of 43) sorted by relevance

12

/art/test/476-checker-ctor-memory-barrier/src/
H A DMain.java32 public ClassWithFinals(boolean cond) { argument
34 if (cond) {
79 public InheritFromClassWithFinals(boolean cond) { argument
80 super(cond);
106 public HaveFinalsAndInheritFromClassWithFinals(boolean cond) { argument
107 super(cond);
/art/compiler/utils/arm/
H A Dassembler_thumb2.h64 void and_(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) OVERRIDE;
66 void eor(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) OVERRIDE;
68 void sub(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) OVERRIDE;
69 void subs(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) OVERRIDE;
71 void rsb(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) OVERRIDE;
72 void rsbs(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) OVERRIDE;
74 void add(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) OVERRIDE;
76 void adds(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) OVERRIDE;
78 void adc(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) OVERRIDE;
80 void sbc(Register rd, Register rn, const ShifterOperand& so, Condition cond
449 CheckCondition(Condition cond) argument
461 CheckConditionLastIt(Condition cond) argument
615 ResetTypeAndCondition(Type type, Condition cond) argument
[all...]
H A Dassembler_arm32.cc60 Condition cond) {
61 EmitType01(cond, so.type(), AND, 0, rn, rd, so);
66 Condition cond) {
67 EmitType01(cond, so.type(), EOR, 0, rn, rd, so);
72 Condition cond) {
73 EmitType01(cond, so.type(), SUB, 0, rn, rd, so);
77 Condition cond) {
78 EmitType01(cond, so.type(), RSB, 0, rn, rd, so);
82 Condition cond) {
83 EmitType01(cond, s
59 and_(Register rd, Register rn, const ShifterOperand& so, Condition cond) argument
65 eor(Register rd, Register rn, const ShifterOperand& so, Condition cond) argument
71 sub(Register rd, Register rn, const ShifterOperand& so, Condition cond) argument
76 rsb(Register rd, Register rn, const ShifterOperand& so, Condition cond) argument
81 rsbs(Register rd, Register rn, const ShifterOperand& so, Condition cond) argument
87 add(Register rd, Register rn, const ShifterOperand& so, Condition cond) argument
93 adds(Register rd, Register rn, const ShifterOperand& so, Condition cond) argument
99 subs(Register rd, Register rn, const ShifterOperand& so, Condition cond) argument
105 adc(Register rd, Register rn, const ShifterOperand& so, Condition cond) argument
111 sbc(Register rd, Register rn, const ShifterOperand& so, Condition cond) argument
117 rsc(Register rd, Register rn, const ShifterOperand& so, Condition cond) argument
123 tst(Register rn, const ShifterOperand& so, Condition cond) argument
129 teq(Register rn, const ShifterOperand& so, Condition cond) argument
135 cmp(Register rn, const ShifterOperand& so, Condition cond) argument
140 cmn(Register rn, const ShifterOperand& so, Condition cond) argument
145 orr(Register rd, Register rn, const ShifterOperand& so, Condition cond) argument
151 orrs(Register rd, Register rn, const ShifterOperand& so, Condition cond) argument
157 mov(Register rd, const ShifterOperand& so, Condition cond) argument
162 movs(Register rd, const ShifterOperand& so, Condition cond) argument
167 bic(Register rd, Register rn, const ShifterOperand& so, Condition cond) argument
173 mvn(Register rd, const ShifterOperand& so, Condition cond) argument
178 mvns(Register rd, const ShifterOperand& so, Condition cond) argument
183 mul(Register rd, Register rn, Register rm, Condition cond) argument
189 mla(Register rd, Register rn, Register rm, Register ra, Condition cond) argument
196 mls(Register rd, Register rn, Register rm, Register ra, Condition cond) argument
203 umull(Register rd_lo, Register rd_hi, Register rn, Register rm, Condition cond) argument
210 sdiv(Register rd, Register rn, Register rm, Condition cond) argument
226 udiv(Register rd, Register rn, Register rm, Condition cond) argument
242 sbfx(Register rd, Register rn, uint32_t lsb, uint32_t width, Condition cond) argument
261 ubfx(Register rd, Register rn, uint32_t lsb, uint32_t width, Condition cond) argument
280 ldr(Register rd, const Address& ad, Condition cond) argument
285 str(Register rd, const Address& ad, Condition cond) argument
290 ldrb(Register rd, const Address& ad, Condition cond) argument
295 strb(Register rd, const Address& ad, Condition cond) argument
300 ldrh(Register rd, const Address& ad, Condition cond) argument
305 strh(Register rd, const Address& ad, Condition cond) argument
310 ldrsb(Register rd, const Address& ad, Condition cond) argument
315 ldrsh(Register rd, const Address& ad, Condition cond) argument
320 ldrd(Register rd, const Address& ad, Condition cond) argument
326 strd(Register rd, const Address& ad, Condition cond) argument
332 ldm(BlockAddressMode am, Register base, RegList regs, Condition cond) argument
340 stm(BlockAddressMode am, Register base, RegList regs, Condition cond) argument
348 vmovs(SRegister sd, SRegister sm, Condition cond) argument
353 vmovd(DRegister dd, DRegister dm, Condition cond) argument
358 vmovs(SRegister sd, float s_imm, Condition cond) argument
373 vmovd(DRegister dd, double d_imm, Condition cond) argument
388 vadds(SRegister sd, SRegister sn, SRegister sm, Condition cond) argument
394 vaddd(DRegister dd, DRegister dn, DRegister dm, Condition cond) argument
400 vsubs(SRegister sd, SRegister sn, SRegister sm, Condition cond) argument
406 vsubd(DRegister dd, DRegister dn, DRegister dm, Condition cond) argument
412 vmuls(SRegister sd, SRegister sn, SRegister sm, Condition cond) argument
418 vmuld(DRegister dd, DRegister dn, DRegister dm, Condition cond) argument
424 vmlas(SRegister sd, SRegister sn, SRegister sm, Condition cond) argument
430 vmlad(DRegister dd, DRegister dn, DRegister dm, Condition cond) argument
436 vmlss(SRegister sd, SRegister sn, SRegister sm, Condition cond) argument
442 vmlsd(DRegister dd, DRegister dn, DRegister dm, Condition cond) argument
448 vdivs(SRegister sd, SRegister sn, SRegister sm, Condition cond) argument
454 vdivd(DRegister dd, DRegister dn, DRegister dm, Condition cond) argument
460 vabss(SRegister sd, SRegister sm, Condition cond) argument
465 vabsd(DRegister dd, DRegister dm, Condition cond) argument
470 vnegs(SRegister sd, SRegister sm, Condition cond) argument
475 vnegd(DRegister dd, DRegister dm, Condition cond) argument
480 vsqrts(SRegister sd, SRegister sm, Condition cond) argument
484 vsqrtd(DRegister dd, DRegister dm, Condition cond) argument
489 vcvtsd(SRegister sd, DRegister dm, Condition cond) argument
494 vcvtds(DRegister dd, SRegister sm, Condition cond) argument
499 vcvtis(SRegister sd, SRegister sm, Condition cond) argument
504 vcvtid(SRegister sd, DRegister dm, Condition cond) argument
509 vcvtsi(SRegister sd, SRegister sm, Condition cond) argument
514 vcvtdi(DRegister dd, SRegister sm, Condition cond) argument
519 vcvtus(SRegister sd, SRegister sm, Condition cond) argument
524 vcvtud(SRegister sd, DRegister dm, Condition cond) argument
529 vcvtsu(SRegister sd, SRegister sm, Condition cond) argument
534 vcvtdu(DRegister dd, SRegister sm, Condition cond) argument
539 vcmps(SRegister sd, SRegister sm, Condition cond) argument
544 vcmpd(DRegister dd, DRegister dm, Condition cond) argument
549 vcmpsz(SRegister sd, Condition cond) argument
554 vcmpdz(DRegister dd, Condition cond) argument
558 b(Label* label, Condition cond) argument
563 bl(Label* label, Condition cond) argument
583 EmitType01(Condition cond, int type, Opcode opcode, int set_cc, Register rn, Register rd, const ShifterOperand& so) argument
603 EmitType5(Condition cond, int offset, bool link) argument
612 EmitMemOp(Condition cond, bool load, bool byte, Register rd, const Address& ad) argument
651 EmitMemOpAddressMode3(Condition cond, int32_t mode, Register rd, const Address& ad) argument
667 EmitMultiMemOp(Condition cond, BlockAddressMode am, bool load, Register base, RegList regs) argument
684 EmitShiftImmediate(Condition cond, Shift opcode, Register rd, Register rm, const ShifterOperand& so) argument
701 EmitShiftRegister(Condition cond, Shift opcode, Register rd, Register rm, const ShifterOperand& so) argument
719 EmitBranch(Condition cond, Label* label, bool link) argument
731 clz(Register rd, Register rm, Condition cond) argument
745 movw(Register rd, uint16_t imm16, Condition cond) argument
754 movt(Register rd, uint16_t imm16, Condition cond) argument
763 EmitMulOp(Condition cond, int32_t opcode, Register rd, Register rn, Register rm, Register rs) argument
782 ldrex(Register rt, Register rn, Condition cond) argument
797 ldrexd(Register rt, Register rt2, Register rn, Condition cond) argument
816 strex(Register rd, Register rt, Register rn, Condition cond) argument
834 strexd(Register rd, Register rt, Register rt2, Register rn, Condition cond) argument
857 clrex(Condition cond) argument
865 nop(Condition cond) argument
873 vmovsr(SRegister sn, Register rt, Condition cond) argument
888 vmovrs(Register rt, SRegister sn, Condition cond) argument
903 vmovsrr(SRegister sm, Register rt, Register rt2, Condition cond) argument
924 vmovrrs(Register rt, Register rt2, SRegister sm, Condition cond) argument
946 vmovdrr(DRegister dm, Register rt, Register rt2, Condition cond) argument
966 vmovrrd(Register rt, Register rt2, DRegister dm, Condition cond) argument
987 vldrs(SRegister sd, const Address& ad, Condition cond) argument
1000 vstrs(SRegister sd, const Address& ad, Condition cond) argument
1014 vldrd(DRegister dd, const Address& ad, Condition cond) argument
1027 vstrd(DRegister dd, const Address& ad, Condition cond) argument
1041 vpushs(SRegister reg, int nregs, Condition cond) argument
1042 EmitVPushPop(static_cast<uint32_t>(reg), nregs, true, false, cond); local
1046 vpushd(DRegister reg, int nregs, Condition cond) argument
1047 EmitVPushPop(static_cast<uint32_t>(reg), nregs, true, true, cond); local
1051 vpops(SRegister reg, int nregs, Condition cond) argument
1052 EmitVPushPop(static_cast<uint32_t>(reg), nregs, false, false, cond); local
1056 vpopd(DRegister reg, int nregs, Condition cond) argument
1057 EmitVPushPop(static_cast<uint32_t>(reg), nregs, false, true, cond); local
1061 EmitVPushPop(uint32_t reg, int nregs, bool push, bool dbl, Condition cond) argument
1087 EmitVFPsss(Condition cond, int32_t opcode, SRegister sd, SRegister sn, SRegister sm) argument
1105 EmitVFPddd(Condition cond, int32_t opcode, DRegister dd, DRegister dn, DRegister dm) argument
1123 EmitVFPsd(Condition cond, int32_t opcode, SRegister sd, DRegister dm) argument
1138 EmitVFPds(Condition cond, int32_t opcode, DRegister dd, SRegister sm) argument
1153 Lsl(Register rd, Register rm, uint32_t shift_imm, bool setcc, Condition cond) argument
1164 Lsr(Register rd, Register rm, uint32_t shift_imm, bool setcc, Condition cond) argument
1176 Asr(Register rd, Register rm, uint32_t shift_imm, bool setcc, Condition cond) argument
1188 Ror(Register rd, Register rm, uint32_t shift_imm, bool setcc, Condition cond) argument
1198 Rrx(Register rd, Register rm, bool setcc, Condition cond) argument
1207 Lsl(Register rd, Register rm, Register rn, bool setcc, Condition cond) argument
1217 Lsr(Register rd, Register rm, Register rn, bool setcc, Condition cond) argument
1227 Asr(Register rd, Register rm, Register rn, bool setcc, Condition cond) argument
1237 Ror(Register rd, Register rm, Register rn, bool setcc, Condition cond) argument
1246 vmstat(Condition cond) argument
1270 blx(Register rm, Condition cond) argument
1280 bx(Register rm, Condition cond) argument
1290 Push(Register rd, Condition cond) argument
1295 Pop(Register rd, Condition cond) argument
1300 PushList(RegList regs, Condition cond) argument
1305 PopList(RegList regs, Condition cond) argument
1310 Mov(Register rd, Register rm, Condition cond) argument
1350 AddConstant(Register rd, int32_t value, Condition cond) argument
1355 AddConstant(Register rd, Register rn, int32_t value, Condition cond) argument
1391 AddConstantSetFlags(Register rd, Register rn, int32_t value, Condition cond) argument
1417 LoadImmediate(Register rd, int32_t value, Condition cond) argument
1435 LoadFromOffset(LoadOperandType type, Register reg, Register base, int32_t offset, Condition cond) argument
1476 LoadSFromOffset(SRegister reg, Register base, int32_t offset, Condition cond) argument
1494 LoadDFromOffset(DRegister reg, Register base, int32_t offset, Condition cond) argument
1512 StoreToOffset(StoreOperandType type, Register reg, Register base, int32_t offset, Condition cond) argument
1548 StoreSToOffset(SRegister reg, Register base, int32_t offset, Condition cond) argument
1566 StoreDToOffset(DRegister reg, Register base, int32_t offset, Condition cond) argument
[all...]
H A Dassembler_arm32.h42 void and_(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) OVERRIDE;
44 void eor(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) OVERRIDE;
46 void sub(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) OVERRIDE;
47 void subs(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) OVERRIDE;
49 void rsb(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) OVERRIDE;
50 void rsbs(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) OVERRIDE;
52 void add(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) OVERRIDE;
54 void adds(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) OVERRIDE;
56 void adc(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) OVERRIDE;
58 void sbc(Register rd, Register rn, const ShifterOperand& so, Condition cond
[all...]
H A Dassembler_arm.h351 virtual void and_(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) = 0;
353 virtual void eor(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) = 0;
355 virtual void sub(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) = 0;
356 virtual void subs(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) = 0;
358 virtual void rsb(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) = 0;
359 virtual void rsbs(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) = 0;
361 virtual void add(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) = 0;
363 virtual void adds(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) = 0;
365 virtual void adc(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) = 0;
367 virtual void sbc(Register rd, Register rn, const ShifterOperand& so, Condition cond
[all...]
H A Dassembler_thumb2.cc55 Condition cond) {
56 EmitDataProcessing(cond, AND, 0, rn, rd, so);
61 Condition cond) {
62 EmitDataProcessing(cond, EOR, 0, rn, rd, so);
67 Condition cond) {
68 EmitDataProcessing(cond, SUB, 0, rn, rd, so);
73 Condition cond) {
74 EmitDataProcessing(cond, RSB, 0, rn, rd, so);
79 Condition cond) {
80 EmitDataProcessing(cond, RS
54 and_(Register rd, Register rn, const ShifterOperand& so, Condition cond) argument
60 eor(Register rd, Register rn, const ShifterOperand& so, Condition cond) argument
66 sub(Register rd, Register rn, const ShifterOperand& so, Condition cond) argument
72 rsb(Register rd, Register rn, const ShifterOperand& so, Condition cond) argument
78 rsbs(Register rd, Register rn, const ShifterOperand& so, Condition cond) argument
84 add(Register rd, Register rn, const ShifterOperand& so, Condition cond) argument
90 adds(Register rd, Register rn, const ShifterOperand& so, Condition cond) argument
96 subs(Register rd, Register rn, const ShifterOperand& so, Condition cond) argument
102 adc(Register rd, Register rn, const ShifterOperand& so, Condition cond) argument
108 sbc(Register rd, Register rn, const ShifterOperand& so, Condition cond) argument
114 rsc(Register rd, Register rn, const ShifterOperand& so, Condition cond) argument
120 tst(Register rn, const ShifterOperand& so, Condition cond) argument
126 teq(Register rn, const ShifterOperand& so, Condition cond) argument
132 cmp(Register rn, const ShifterOperand& so, Condition cond) argument
137 cmn(Register rn, const ShifterOperand& so, Condition cond) argument
142 orr(Register rd, Register rn, const ShifterOperand& so, Condition cond) argument
148 orrs(Register rd, Register rn, const ShifterOperand& so, Condition cond) argument
154 mov(Register rd, const ShifterOperand& so, Condition cond) argument
159 movs(Register rd, const ShifterOperand& so, Condition cond) argument
164 bic(Register rd, Register rn, const ShifterOperand& so, Condition cond) argument
170 mvn(Register rd, const ShifterOperand& so, Condition cond) argument
175 mvns(Register rd, const ShifterOperand& so, Condition cond) argument
180 mul(Register rd, Register rn, Register rm, Condition cond) argument
205 mla(Register rd, Register rn, Register rm, Register ra, Condition cond) argument
223 mls(Register rd, Register rn, Register rm, Register ra, Condition cond) argument
241 umull(Register rd_lo, Register rd_hi, Register rn, Register rm, Condition cond) argument
259 sdiv(Register rd, Register rn, Register rm, Condition cond) argument
276 udiv(Register rd, Register rn, Register rm, Condition cond) argument
293 sbfx(Register rd, Register rn, uint32_t lsb, uint32_t width, Condition cond) argument
314 ubfx(Register rd, Register rn, uint32_t lsb, uint32_t width, Condition cond) argument
335 ldr(Register rd, const Address& ad, Condition cond) argument
340 str(Register rd, const Address& ad, Condition cond) argument
345 ldrb(Register rd, const Address& ad, Condition cond) argument
350 strb(Register rd, const Address& ad, Condition cond) argument
355 ldrh(Register rd, const Address& ad, Condition cond) argument
360 strh(Register rd, const Address& ad, Condition cond) argument
365 ldrsb(Register rd, const Address& ad, Condition cond) argument
370 ldrsh(Register rd, const Address& ad, Condition cond) argument
375 ldrd(Register rd, const Address& ad, Condition cond) argument
380 ldrd(Register rd, Register rd2, const Address& ad, Condition cond) argument
392 strd(Register rd, const Address& ad, Condition cond) argument
397 strd(Register rd, Register rd2, const Address& ad, Condition cond) argument
409 ldm(BlockAddressMode am, Register base, RegList regs, Condition cond) argument
420 ldr(static_cast<Register>(reg), Address(base, kRegisterSize, Address::PostIndex), cond); local
427 stm(BlockAddressMode am, Register base, RegList regs, Condition cond) argument
439 str(static_cast<Register>(reg), Address(base, -kRegisterSize, strmode), cond); local
446 vmovs(SRegister sd, float s_imm, Condition cond) argument
461 vmovd(DRegister dd, double d_imm, Condition cond) argument
476 vmovs(SRegister sd, SRegister sm, Condition cond) argument
481 vmovd(DRegister dd, DRegister dm, Condition cond) argument
486 vadds(SRegister sd, SRegister sn, SRegister sm, Condition cond) argument
492 vaddd(DRegister dd, DRegister dn, DRegister dm, Condition cond) argument
498 vsubs(SRegister sd, SRegister sn, SRegister sm, Condition cond) argument
504 vsubd(DRegister dd, DRegister dn, DRegister dm, Condition cond) argument
510 vmuls(SRegister sd, SRegister sn, SRegister sm, Condition cond) argument
516 vmuld(DRegister dd, DRegister dn, DRegister dm, Condition cond) argument
522 vmlas(SRegister sd, SRegister sn, SRegister sm, Condition cond) argument
528 vmlad(DRegister dd, DRegister dn, DRegister dm, Condition cond) argument
534 vmlss(SRegister sd, SRegister sn, SRegister sm, Condition cond) argument
540 vmlsd(DRegister dd, DRegister dn, DRegister dm, Condition cond) argument
546 vdivs(SRegister sd, SRegister sn, SRegister sm, Condition cond) argument
552 vdivd(DRegister dd, DRegister dn, DRegister dm, Condition cond) argument
558 vabss(SRegister sd, SRegister sm, Condition cond) argument
563 vabsd(DRegister dd, DRegister dm, Condition cond) argument
568 vnegs(SRegister sd, SRegister sm, Condition cond) argument
573 vnegd(DRegister dd, DRegister dm, Condition cond) argument
578 vsqrts(SRegister sd, SRegister sm, Condition cond) argument
582 vsqrtd(DRegister dd, DRegister dm, Condition cond) argument
587 vcvtsd(SRegister sd, DRegister dm, Condition cond) argument
592 vcvtds(DRegister dd, SRegister sm, Condition cond) argument
597 vcvtis(SRegister sd, SRegister sm, Condition cond) argument
602 vcvtid(SRegister sd, DRegister dm, Condition cond) argument
607 vcvtsi(SRegister sd, SRegister sm, Condition cond) argument
612 vcvtdi(DRegister dd, SRegister sm, Condition cond) argument
617 vcvtus(SRegister sd, SRegister sm, Condition cond) argument
622 vcvtud(SRegister sd, DRegister dm, Condition cond) argument
627 vcvtsu(SRegister sd, SRegister sm, Condition cond) argument
632 vcvtdu(DRegister dd, SRegister sm, Condition cond) argument
637 vcmps(SRegister sd, SRegister sm, Condition cond) argument
642 vcmpd(DRegister dd, DRegister dm, Condition cond) argument
647 vcmpsz(SRegister sd, Condition cond) argument
652 vcmpdz(DRegister dd, Condition cond) argument
656 b(Label* label, Condition cond) argument
661 bl(Label* label, Condition cond) argument
885 Emit16BitDataProcessing(Condition cond, Opcode opcode, bool set_cc, Register rn, Register rd, const ShifterOperand& so) argument
1186 EmitDataProcessing(Condition cond, Opcode opcode, bool set_cc, Register rn, Register rd, const ShifterOperand& so) argument
1359 EmitLoadStore(Condition cond, bool load, bool byte, bool half, bool is_signed, Register rd, const Address& ad) argument
1522 EmitMultiMemOp(Condition cond, BlockAddressMode bam, bool load, Register base, RegList regs) argument
1592 EmitBranch(Condition cond, Label* label, bool link, bool x) argument
1636 clz(Register rd, Register rm, Condition cond) argument
1653 movw(Register rd, uint16_t imm16, Condition cond) argument
1682 movt(Register rd, uint16_t imm16, Condition cond) argument
1700 ldrex(Register rt, Register rn, uint16_t imm, Condition cond) argument
1715 ldrex(Register rt, Register rn, Condition cond) argument
1720 strex(Register rd, Register rt, Register rn, uint16_t imm, Condition cond) argument
1740 ldrexd(Register rt, Register rt2, Register rn, Condition cond) argument
1756 strex(Register rd, Register rt, Register rn, Condition cond) argument
1764 strexd(Register rd, Register rt, Register rt2, Register rn, Condition cond) argument
1784 clrex(Condition cond) argument
1797 nop(Condition cond) argument
1805 vmovsr(SRegister sn, Register rt, Condition cond) argument
1820 vmovrs(Register rt, SRegister sn, Condition cond) argument
1835 vmovsrr(SRegister sm, Register rt, Register rt2, Condition cond) argument
1856 vmovrrs(Register rt, Register rt2, SRegister sm, Condition cond) argument
1878 vmovdrr(DRegister dm, Register rt, Register rt2, Condition cond) argument
1898 vmovrrd(Register rt, Register rt2, DRegister dm, Condition cond) argument
1919 vldrs(SRegister sd, const Address& ad, Condition cond) argument
1932 vstrs(SRegister sd, const Address& ad, Condition cond) argument
1946 vldrd(DRegister dd, const Address& ad, Condition cond) argument
1959 vstrd(DRegister dd, const Address& ad, Condition cond) argument
1973 vpushs(SRegister reg, int nregs, Condition cond) argument
1974 EmitVPushPop(static_cast<uint32_t>(reg), nregs, true, false, cond); local
1978 vpushd(DRegister reg, int nregs, Condition cond) argument
1979 EmitVPushPop(static_cast<uint32_t>(reg), nregs, true, true, cond); local
1983 vpops(SRegister reg, int nregs, Condition cond) argument
1984 EmitVPushPop(static_cast<uint32_t>(reg), nregs, false, false, cond); local
1988 vpopd(DRegister reg, int nregs, Condition cond) argument
1989 EmitVPushPop(static_cast<uint32_t>(reg), nregs, false, true, cond); local
1993 EmitVPushPop(uint32_t reg, int nregs, bool push, bool dbl, Condition cond) argument
2019 EmitVFPsss(Condition cond, int32_t opcode, SRegister sd, SRegister sn, SRegister sm) argument
2037 EmitVFPddd(Condition cond, int32_t opcode, DRegister dd, DRegister dn, DRegister dm) argument
2055 EmitVFPsd(Condition cond, int32_t opcode, SRegister sd, DRegister dm) argument
2070 EmitVFPds(Condition cond, int32_t opcode, DRegister dd, SRegister sm) argument
2085 vmstat(Condition cond) argument
2127 SetItCondition(ItState s, Condition cond, uint8_t index) argument
2198 blx(Register rm, Condition cond) argument
2206 bx(Register rm, Condition cond) argument
2214 Push(Register rd, Condition cond) argument
2219 Pop(Register rd, Condition cond) argument
2224 PushList(RegList regs, Condition cond) argument
2229 PopList(RegList regs, Condition cond) argument
2234 Mov(Register rd, Register rm, Condition cond) argument
2269 Condition cond = n ? NE : EQ; local
2320 Lsl(Register rd, Register rm, uint32_t shift_imm, bool setcc, Condition cond) argument
2328 Lsr(Register rd, Register rm, uint32_t shift_imm, bool setcc, Condition cond) argument
2337 Asr(Register rd, Register rm, uint32_t shift_imm, bool setcc, Condition cond) argument
2346 Ror(Register rd, Register rm, uint32_t shift_imm, bool setcc, Condition cond) argument
2354 Rrx(Register rd, Register rm, bool setcc, Condition cond) argument
2360 Lsl(Register rd, Register rm, Register rn, bool setcc, Condition cond) argument
2367 Lsr(Register rd, Register rm, Register rn, bool setcc, Condition cond) argument
2374 Asr(Register rd, Register rm, Register rn, bool setcc, Condition cond) argument
2381 Ror(Register rd, Register rm, Register rn, bool setcc, Condition cond) argument
2455 AddConstant(Register rd, int32_t value, Condition cond) argument
2460 AddConstant(Register rd, Register rn, int32_t value, Condition cond) argument
2496 AddConstantSetFlags(Register rd, Register rn, int32_t value, Condition cond) argument
2523 LoadImmediate(Register rd, int32_t value, Condition cond) argument
2541 LoadFromOffset(LoadOperandType type, Register reg, Register base, int32_t offset, Condition cond) argument
2582 LoadSFromOffset(SRegister reg, Register base, int32_t offset, Condition cond) argument
2600 LoadDFromOffset(DRegister reg, Register base, int32_t offset, Condition cond) argument
2618 StoreToOffset(StoreOperandType type, Register reg, Register base, int32_t offset, Condition cond) argument
2674 StoreSToOffset(SRegister reg, Register base, int32_t offset, Condition cond) argument
2692 StoreDToOffset(DRegister reg, Register base, int32_t offset, Condition cond) argument
[all...]
H A Dassembler_arm_test.h85 std::vector<Cond>& cond = GetConditions(); local
87 WarnOnCombinations(cond.size() * immediates1.size() * immediates2.size() *
92 for (Cond& c : cond) {
176 std::vector<Cond>& cond = GetConditions(); local
178 WarnOnCombinations(cond.size() * immediates.size() * reg1_registers.size() *
183 for (Cond& c : cond) {
261 const std::vector<Cond>& cond,
265 WarnOnCombinations(cond.size() * reg1_registers.size() * reg2_registers.size());
269 for (const Cond& c : cond) {
325 const std::vector<Cond>& cond,
258 RepeatTemplatedRRC(void (Ass::*f)(Reg1, Reg2, Cond), const std::vector<Reg1*>& reg1_registers, const std::vector<Reg2*>& reg2_registers, const std::vector<Cond>& cond, std::string (AssemblerArmTest::*GetName1)(const Reg1&), std::string (AssemblerArmTest::*GetName2)(const Reg2&), std::string fmt) argument
321 RepeatTemplatedRRRC(void (Ass::*f)(Reg1, Reg2, Reg3, Cond), const std::vector<Reg1*>& reg1_registers, const std::vector<Reg2*>& reg2_registers, const std::vector<Reg3*>& reg3_registers, const std::vector<Cond>& cond, std::string (AssemblerArmTest::*GetName1)(const Reg1&), std::string (AssemblerArmTest::*GetName2)(const Reg2&), std::string (AssemblerArmTest::*GetName3)(const Reg3&), std::string fmt) argument
389 RepeatTemplatedRSC(void (Ass::*f)(RegT, SOp, Cond), const std::vector<RegT*>& registers, const std::vector<SOp>& shifts, const std::vector<Cond>& cond, std::string (AssemblerArmTest::*GetName)(const RegT&), std::string fmt) argument
443 RepeatTemplatedRRSC(void (Ass::*f)(Reg1, Reg2, const SOp&, Cond), const std::vector<Reg1*>& reg1_registers, const std::vector<Reg2*>& reg2_registers, const std::vector<SOp>& shifts, const std::vector<Cond>& cond, std::string (AssemblerArmTest::*GetName1)(const Reg1&), std::string (AssemblerArmTest::*GetName2)(const Reg2&), std::string fmt) argument
[all...]
/art/test/112-double-math/src/
H A DMain.java18 public static double cond_neg_double(double value, boolean cond) { argument
19 return cond ? -value : value;
/art/compiler/optimizing/
H A Dboolean_simplifier.cc64 // Returns an instruction with the opposite boolean value from 'cond'.
65 static HInstruction* GetOppositeCondition(HInstruction* cond) { argument
66 HGraph* graph = cond->GetBlock()->GetGraph();
69 if (cond->IsCondition()) {
70 HInstruction* lhs = cond->InputAt(0);
71 HInstruction* rhs = cond->InputAt(1);
72 if (cond->IsEqual()) {
74 } else if (cond->IsNotEqual()) {
76 } else if (cond->IsLessThan()) {
78 } else if (cond
[all...]
H A Dbounds_check_elimination.cc819 HCondition* cond; local
822 cond = new (graph->GetArena()) HGreaterThan(initial_, end_);
824 cond = new (graph->GetArena()) HGreaterThanOrEqual(initial_, end_);
829 cond = new (graph->GetArena()) HLessThan(initial_, end_);
831 cond = new (graph->GetArena()) HLessThanOrEqual(initial_, end_);
834 HIf* h_if = new (graph->GetArena()) HIf(cond);
835 if_block->AddInstruction(cond);
859 HCondition* cond = new (graph->GetArena()) HLessThan(value, const_instr); local
861 HDeoptimize(cond, suspend_check->GetDexPc());
862 deopt_block->InsertInstructionBefore(cond, deopt_bloc
1007 HCondition* cond = new (graph->GetArena()) HGreaterThan(value, added); local
1188 HandleIfBetweenTwoMonotonicValueRanges(HIf* instruction, HInstruction* left, HInstruction* right, IfCondition cond, MonotonicValueRange* left_range, MonotonicValueRange* right_range) argument
1254 HandleIf(HIf* instruction, HInstruction* left, HInstruction* right, IfCondition cond) argument
1531 HCondition* cond = instruction->InputAt(0)->AsCondition(); local
1771 HCondition* cond = new (GetGraph()->GetArena()) HLessThanOrEqual(array_length, const_instr); local
[all...]
H A Dgvn.cc202 // the ones on which 'cond' returns true.
204 void DeleteAllImpureWhich(Functor cond) { argument
215 // Iterate as long as the entries don't satisfy 'cond'.
217 if (cond(node)) {
231 // or we do not own it but no entries matched 'cond'.
238 if (cond(node)) {
H A Dbounds_check_elimination_test.cc366 IfCondition cond = kCondGE) {
401 if (cond == kCondGE) {
404 DCHECK(cond == kCondGT);
501 IfCondition cond = kCondLE) {
539 if (cond == kCondLE) {
542 DCHECK(cond == kCondLT);
629 IfCondition cond) {
663 if (cond == kCondGE) {
666 DCHECK(cond == kCondGT);
744 IfCondition cond
625 BuildSSAGraph3(ArenaAllocator* allocator, HInstruction** bounds_check, int initial, int increment, IfCondition cond) argument
[all...]
/art/test/441-checker-inliner/src/
H A DMain.java147 public static int InlineWithControlFlow(boolean cond) { argument
152 if (cond) {
/art/compiler/dex/
H A Dglobal_value_numbering.cc204 bool GlobalValueNumbering::IsBlockEnteredOnTrue(uint16_t cond, BasicBlockId bb_id) { argument
205 DCHECK_NE(cond, kNoValue);
213 if (operand == cond) {
221 bool GlobalValueNumbering::IsTrueInBlock(uint16_t cond, BasicBlockId bb_id) { argument
224 DCHECK_NE(cond, kNoValue);
225 if (IsBlockEnteredOnTrue(cond, bb_id)) {
230 if (IsBlockEnteredOnTrue(cond, dom_id)) {
H A Dglobal_value_numbering.h205 bool IsBlockEnteredOnTrue(uint16_t cond, BasicBlockId bb_id);
206 bool IsTrueInBlock(uint16_t cond, BasicBlockId bb_id);
/art/test/442-checker-constant-folding/src/
H A DMain.java223 public static int JumpsAndConditionals(boolean cond) { argument
227 if (cond)
/art/disassembler/
H A Ddisassembler_arm.h42 void DumpCond(std::ostream& os, uint32_t cond);
H A Ddisassembler_arm.cc77 void DisassemblerArm::DumpCond(std::ostream& os, uint32_t cond) { argument
78 if (cond < 15) {
79 os << kConditionCodeNames[cond];
81 os << "Unexpected condition: " << cond; local
250 uint32_t cond = (instruction >> 28) & 0xf; local
360 opcode += kConditionCodeNames[cond];
1198 // |111|10|S|cond| imm6 |1|0|J1|0|J2| imm11 |
1204 uint32_t cond = (instr >> 22) & 0xF; local
1208 DumpCond(opcode, cond);
1237 // |111|10|S|cond| imm
1240 uint32_t cond = (instr >> 22) & 0xF; local
1743 uint32_t cond = (instr >> 8) & 0xF; local
[all...]
/art/compiler/dex/quick/
H A Dgen_common.cc351 ConditionCode cond; local
355 cond = kCondEq;
358 cond = kCondNe;
361 cond = kCondLt;
364 cond = kCondGe;
367 cond = kCondGt;
370 cond = kCondLe;
373 cond = static_cast<ConditionCode>(0);
382 cond = FlipComparisonOrder(cond);
414 ConditionCode cond; local
[all...]
/art/compiler/utils/arm64/
H A Dassembler_arm64.h222 void LoadImmediate(XRegister dest, int32_t value, vixl::Condition cond = vixl::al);
229 void AddConstant(XRegister rd, int32_t value, vixl::Condition cond = vixl::al);
230 void AddConstant(XRegister rd, XRegister rn, int32_t value, vixl::Condition cond = vixl::al);
H A Dassembler_arm64.cc75 void Arm64Assembler::AddConstant(XRegister rd, int32_t value, Condition cond) { argument
76 AddConstant(rd, rd, value, cond);
80 Condition cond) {
81 if ((cond == al) || (cond == nv)) {
86 // rd = cond ? temp : rn
91 ___ Csel(reg_x(rd), temp, reg_x(rd), cond); local
200 Condition cond) {
201 if ((cond == al) || (cond
79 AddConstant(XRegister rd, XRegister rn, int32_t value, Condition cond) argument
199 LoadImmediate(XRegister dest, int32_t value, Condition cond) argument
211 ___ Csel(reg_x(dest), temp, reg_x(dest), cond); local
213 ___ Csel(reg_x(dest), reg_x(XZR), reg_x(dest), cond); local
[all...]
/art/compiler/dex/quick/mips/
H A Dint_mips.cc83 LIR* MipsMir2Lir::OpCmpBranch(ConditionCode cond, RegStorage src1, RegStorage src2, LIR* target) { argument
89 switch (cond) {
130 LOG(FATAL) << "No support for ConditionCode: " << cond;
149 LIR* MipsMir2Lir::OpCmpImmBranch(ConditionCode cond, RegStorage reg, int check_value, LIR* target) { argument
155 branch = OpCmpBranch(cond, reg, t_reg, target);
160 switch (cond) {
172 branch = OpCmpBranch(cond, reg, t_reg, target);
478 LIR* MipsMir2Lir::OpIT(ConditionCode cond, const char* guide) { argument
479 UNUSED(cond, guide);
H A Dcodegen_mips.h196 LIR* OpCmpBranch(ConditionCode cond, RegStorage src1, RegStorage src2, LIR* target);
197 LIR* OpCmpImmBranch(ConditionCode cond, RegStorage reg, int check_value, LIR* target);
201 LIR* OpIT(ConditionCode cond, const char* guide);
/art/compiler/dex/quick/arm/
H A Dcodegen_arm.h198 LIR* OpCmpBranch(ConditionCode cond, RegStorage src1, RegStorage src2, LIR* target);
199 LIR* OpCmpImmBranch(ConditionCode cond, RegStorage reg, int check_value, LIR* target);
203 LIR* OpIT(ConditionCode cond, const char* guide);
/art/compiler/dex/quick/arm64/
H A Dcodegen_arm64.h85 LIR* OpCmpMemImmBranch(ConditionCode cond, RegStorage temp_reg, RegStorage base_reg,
202 LIR* OpCmpBranch(ConditionCode cond, RegStorage src1, RegStorage src2, LIR* target) OVERRIDE;
203 LIR* OpCmpImmBranch(ConditionCode cond, RegStorage reg, int check_value, LIR* target) OVERRIDE;
207 LIR* OpIT(ConditionCode cond, const char* guide) OVERRIDE;

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