| 2cebb24bfc3247d3e9be138a3350106737455918 |
|
22-Apr-2015 |
Mathieu Chartier <mathieuc@google.com> |
Replace NULL with nullptr
Also fixed some lines that were too long, and a few other minor
details.
Change-Id: I6efba5fb6e03eb5d0a300fddb2a75bf8e2f175cb
|
| 6f7158927fee233255f8e96719c374694b10cad3 |
|
30-Mar-2015 |
David Srbecky <dsrbecky@google.com> |
Write .debug_line section using the new DWARF library.
Also simplify dex to java mapping and handle mapping
in prologues and epilogues.
Change-Id: I410f06024580f2a8788f2c93fe9bca132805029a
|
| 20f85597828194c12be10d3a927999def066555e |
|
19-Mar-2015 |
Vladimir Marko <vmarko@google.com> |
Fixed layout for dex caches in boot image.
Define a fixed layout for dex cache arrays (type, method,
string and field arrays) for dex caches in the boot image.
This gives those arrays fixed offsets from the boot image
code and allows PC-relative addressing of their elements.
Use the PC-relative load on arm64 for relevant instructions,
i.e. invoke-static, invoke-direct, const-string,
const-class, check-cast and instance-of. This reduces the
arm64 boot.oat on Nexus 9 by 1.1MiB.
This CL provides the infrastructure and shows on the arm64
the gains that we can achieve by having fixed dex cache
arrays' layout. To fully use this for the boot images, we
need to implement the PC-relative addressing for other
architectures. To achieve similar gains for apps, we need
to move the dex cache arrays to a .bss section of the oat
file. These changes will be implemented in subsequent CLs.
(Also remove some compiler_driver.h dependencies to reduce
incremental build times.)
Change-Id: Ib1859fa4452d01d983fd92ae22b611f45a85d69b
|
| f6737f7ed741b15cfd60c2530dab69f897540735 |
|
23-Mar-2015 |
Vladimir Marko <vmarko@google.com> |
Quick: Clean up Mir2Lir codegen.
Clean up WrapPointer()/UnwrapPointer() and OpPcRelLoad().
Change-Id: I1a91f01e1e779599c77f3f6efcac2a6ad34629cf
|
| 335c55527846fc9019246163be0ac1ac02e95057 |
|
04-Feb-2015 |
Ningsheng Jian <ningsheng.jian@arm.com> |
ARM: Fix LIR flags in encoding map.
Also correct memory reference type for PC relative load.
Change-Id: I7a5258f2ed718448dc3e6e7fda6569b3f0c2fe46
|
| a2e18ed9397f21c96eae4a26df9ca35a6a97341d |
|
27-Jan-2015 |
Andreas Gampe <agampe@google.com> |
ART: Fix inlining of Mir2Lir
Missed -inl includes.
Change-Id: I39e6d603c7f5d36693aca3816653594488bff63f
|
| 0b9203e7996ee1856f620f95d95d8a273c43a3df |
|
23-Jan-2015 |
Andreas Gampe <agampe@google.com> |
ART: Some Quick cleanup
Make several fields const in CompilationUnit. May benefit some Mir2Lir
code that repeats tests, and in general immutability is good.
Remove compiler_internals.h and refactor some other headers to reduce
overly broad imports (and thus forced recompiles on changes).
Change-Id: I898405907c68923581373b5981d8a85d2e5d185a
|
| eb54d850cc713a64e8260d12db03bfd15b42584c |
|
10-Dec-2014 |
Ningsheng Jian <ningsheng.jian@arm.com> |
AArch64: Fix incorrect use of preceding LIR.
In Cortex-A53 erratum 835769 fixup, we should check the LIR for
previous emitted instruction, skipping pseudo LIRs and other
non-emitting LIRs.
Change-Id: I908f4c638650d7ad9c91112b74095bba2d81612e
|
| a262f7707330dccfb50af6345813083182b61043 |
|
25-Nov-2014 |
Ningsheng Jian <ningsheng.jian@arm.com> |
ARM: Combine multiply accumulate operations.
Try to combine integer multiply and add(sub) into a MAC operation.
For AArch64, also try to combine long type multiply and add(sub).
Change-Id: Ic85812e941eb5a66abc355cab81a4dd16de1b66e
|
| 65420b244f18a3492a342ee3edaefeb26aed4230 |
|
27-Oct-2014 |
Matteo Franchin <matteo.franchin@arm.com> |
AArch64: Addressing Cortex-A53 erratum 835769.
Some early revisions of the Cortex-A53 have an erratum (835769) whereby
it is possible for a 64-bit multiply-accumulate instruction in AArch64
state to generate an incorrect result. The conditions which a portion
of code must satisfy in order for the issue to be observed are somewhat
complex, but all cases end with a memory (load, store, or prefetch)
instruction followed immediately by the multiply-accumulate operation.
This commit makes sure to insert a nop instruction before a 64-bit msub
instruction, whenever the latter is preceded by a memory instruction.
This behaviour should make it impossible for the Arm64 backend to
generate a sequence of instructions which matches the erratum
conditions.
Change-Id: I0022eccd41180183c20231dab6e2671d001a204c
|
| 2431452a13829996a440d7cdc30542e77d622b98 |
|
12-Nov-2014 |
Matteo Franchin <matteo.franchin@arm.com> |
AArch64: Small improvements.
Remove useless branches (branch to the next instruction).
Change the implicit stack overflow check to do a 32-bit rather than a
64-bit load. Also put the result in wzr, as we do not need it.
Change-Id: I2d29fc62cb757ac5443fdd09282871f734deeef9
|
| 277ccbd200ea43590dfc06a93ae184a765327ad0 |
|
04-Nov-2014 |
Andreas Gampe <agampe@google.com> |
ART: More warnings
Enable -Wno-conversion-null, -Wredundant-decls and -Wshadow in general,
and -Wunused-but-set-parameter for GCC builds.
Change-Id: I81bbdd762213444673c65d85edae594a523836e5
|
| 785d2f2116bb57418d81bb55b55a087afee11053 |
|
04-Nov-2014 |
Andreas Gampe <agampe@google.com> |
ART: Replace COMPILE_ASSERT with static_assert (compiler)
Replace all occurrences of COMPILE_ASSERT in the compiler tree.
Change-Id: Icc40a38c8bdeaaf7305ab3352a838a2cd7e7d840
|
| fc787ecd91127b2c8458afd94e5148e2ae51a1f5 |
|
10-Oct-2014 |
Ian Rogers <irogers@google.com> |
Enable -Wimplicit-fallthrough.
Falling through switch cases on a clang build must now annotate the fallthrough
with the FALLTHROUGH_INTENDED macro.
Bug: 17731372
Change-Id: I836451cd5f96b01d1ababdbf9eef677fe8fa8324
|
| 7c2ad5af0bdd3cc1069038f8e3422d99aeb5f44c |
|
24-Sep-2014 |
Vladimir Marko <vmarko@google.com> |
Implement method calls using relative BL on ARM64.
Change-Id: I9e5d0b6c100b6cddd6bbb7ab07cff77ab104ea31
|
| 4163c53ce38a0f1f88bf3e8d26de9914da38498b |
|
15-Jul-2014 |
Matteo Franchin <matteo.franchin@arm.com> |
AArch64: address some outstanding TODOs.
Fix comments in arm64_lir.h. Rename Arm* to A64* and replace FWIDE,
FUNWIDE, ... with WIDE, UNWIDE, ...
Change-Id: I4900902e28463ea5e00e34ea40ddfc15704c0bfa
|
| 5d7cdec7527f8043bf15e23a0041c40156727243 |
|
18-Aug-2014 |
Zheng Xu <zheng.xu@arm.com> |
AArch64: Add tbz/tbnz and tst.
Since the branch offset supported by tbz/tbnz is quite small(-32k ~ +32k),
it will be replaced by tst and beq/bneq in the fix-up stage if the branch
offset is too large.
Change-Id: I4cace06bec6425e0f2e1f5f7c471eec08d06bca6
|
| f29ecd69af2743a425314baa4abd6c44d8d88649 |
|
29-Jul-2014 |
Andreas Gampe <agampe@google.com> |
ART: Rework ARM64 entry sequence
Try to fold one sub of SP in the ARM64 entry sequence. When the
framesize is small, generate a sub over the full frame-size, and
adjust the spill offsets accordingly. If the framesize is too
large, use a pre-indexed store and fill upwards from there.
Change-Id: I1c15ac6276fb62b8164372de02fd92437f605938
|
| 2eba1fa7e9e5f91e18ae3778d529520bd2c78d55 |
|
31-Jul-2014 |
Serban Constantinescu <serban.constantinescu@arm.com> |
AArch64: Add inlining support for ceil(), floor(), rint(), round()
This patch adds inlining support for the following Math, StrictMath
methods in the ARM64 backend:
* double ceil(double)
* double floor(double)
* double rint(double)
* long round(double)
* int round(float)
Also some cleanup.
Change-Id: I9f5a2f4065b1313649f4b0c4380b8176703c3fe1
Signed-off-by: Serban Constantinescu <serban.constantinescu@arm.com>
|
| 63999683329612292d534e6be09dbde9480f1250 |
|
15-Jul-2014 |
Serban Constantinescu <serban.constantinescu@arm.com> |
Revert "Revert "Enable Load Store Elimination for ARM and ARM64""
This patch refactors the implementation of the LoadStoreElimination
optimisation pass. Please note that this pass was disabled and not
functional for any of the backends.
The current implementation tracks aliases and handles DalvikRegs as well
as Heap memory regions. It has been tested and it is known to optimise
out the following:
* Load - Load
* Store - Load
* Store - Store
* Load Literals
Change-Id: I3aadb12a787164146a95bc314e85fa73ad91e12b
|
| c32447bcc8c36ee8ff265ed678c7df86936a9ebe |
|
27-Jul-2014 |
Bill Buzbee <buzbee@android.com> |
Revert "Enable Load Store Elimination for ARM and ARM64"
On extended testing, I'm seeing a CHECK failure at utility_arm.cc:1201.
This reverts commit fcc36ba2a2b8fd10e6eebd21ecb6329606443ded.
Change-Id: Icae3d49cd7c8fcab09f2f989cbcb1d7e5c6d137a
|
| fcc36ba2a2b8fd10e6eebd21ecb6329606443ded |
|
15-Jul-2014 |
Serban Constantinescu <serban.constantinescu@arm.com> |
Enable Load Store Elimination for ARM and ARM64
This patch refactors the implementation of the LoadStoreElimination
optimisation pass. Please note that this pass was disabled and not
functional for any of the backends.
The current implementation tracks aliases and handles DalvikRegs as well
as Heap memory regions. It has been tested and it is known to optimise
out the following:
* Load - Load
* Store - Load
* Store - Store
* Load Literals
Change-Id: Iefae9b696f87f833ef35c451ed4d49c5a1b6fde0
|
| ed7a0f2fb84b200ab6ef34e30dcbba4c0cf8d435 |
|
10-Jun-2014 |
Matteo Franchin <matteo.franchin@arm.com> |
AArch64: improve usage of TargetReg() and friends.
TargetReg(arg1) does now always return a 32-bit register. We also avoid
using this function directly and rather use the two-arguments overload
or TargetPtrReg().
Change-Id: I746b3c29a2a2553b399b5c3e7ee3887c7e7c52c3
|
| 421efca6d71ffe348295872743317bf107a9a94a |
|
11-Jul-2014 |
Zheng Xu <zheng.xu@arm.com> |
AArch64: Fix def use.
Add comment to GenPCUseDefEncoding(). Fix def-use flags for several
instruction encodings.
Change-Id: Ifc5a2484395486c01a64307a4acddc794026d46a
|
| 7c6c2ac4252ac31b42967e0f0233e8d32c5b5abe |
|
01-Jul-2014 |
Matteo Franchin <matteo.franchin@arm.com> |
Aarch64: easy division and remainder for long ints.
Also adding test 701 to test easy division and remainder for int and
long integers.
Change-Id: I8212c84e4d9eb3e9f3f4f1f1c3418537bb13dc55
|
| 873c371eea7d8700c8037d790de168b5ed7c20d0 |
|
11-Jul-2014 |
Stuart Monteith <stuart.monteith@arm.com> |
ART: Fix GenSelect for ARM64
Add CSINV and replace CSNEG in GenSelect.
Some tests were failing in 083-complier-regression as CSNEG
was used instead of CSINV. CSNEG on xzr yields 0, whereas
CSINV negates the bits and yields -1, which was the intention.
Change-Id: I60557e34483f98310f7d33f18d8db203fba6e78f
Signed-off-by: Stuart Monteith <stuart.monteith@arm.com>
|
| 15d7a46d198f8064efbe4ab10696d448ed9dc60f |
|
04-Jul-2014 |
Matteo Franchin <matteo.franchin@arm.com> |
Aarch64: fix encoding map for kA64Fmov2xS.
Change-Id: I5127a4443969dc2322461a4b4a34d6c39a0ffd64
|
| 23abec955e2e733999a1e2c30e4e384e46e5dde4 |
|
02-Jul-2014 |
Serban Constantinescu <serban.constantinescu@arm.com> |
AArch64: Add few more inline functions
This patch adds inlining support for the following functions:
* Math.max/min(long, long)
* Math.max/min(float, float)
* Math.max/min(double, double)
* Integer.reverse(int)
* Long.reverse(long)
Change-Id: Ia2b1619fd052358b3a0d23e5fcbfdb823d2029b9
Signed-off-by: Serban Constantinescu <serban.constantinescu@arm.com>
|
| de68676b24f61a55adc0b22fe828f036a5925c41 |
|
24-Jun-2014 |
Andreas Gampe <agampe@google.com> |
Revert "ART: Split out more cases of Load/StoreRef, volatile as parameter"
This reverts commit 2689fbad6b5ec1ae8f8c8791a80c6fd3cf24144d.
Breaks the build.
Change-Id: I9faad4e9a83b32f5f38b2ef95d6f9a33345efa33
|
| 3c12c512faf6837844d5465b23b9410889e5eb11 |
|
24-Jun-2014 |
Andreas Gampe <agampe@google.com> |
Revert "Revert "ART: Split out more cases of Load/StoreRef, volatile as parameter""
This reverts commit de68676b24f61a55adc0b22fe828f036a5925c41.
Fixes an API comment, and differentiates between inserting and appending.
Change-Id: I0e9a21bb1d25766e3cbd802d8b48633ae251a6bf
|
| 2689fbad6b5ec1ae8f8c8791a80c6fd3cf24144d |
|
23-Jun-2014 |
Andreas Gampe <agampe@google.com> |
ART: Split out more cases of Load/StoreRef, volatile as parameter
Splits out more cases of ref registers being loaded or stored. For
code clarity, adds volatile as a flag parameter instead of a separate
method.
On ARM64, continue cleanup. Add flags to print/fatal on size mismatches.
Change-Id: I30ed88433a6b4ff5399aefffe44c14a5e6f4ca4e
|
| c61b3c984c509d5f7c8eb71b853c81a34b5c28ef |
|
18-Jun-2014 |
Matteo Franchin <matteo.franchin@arm.com> |
AArch64: implement easy division and reminder.
This implements easy division and reminder for integer only (32-bit).
The optimisation applies to div/rem by powers of 2 and to div by small
literals (between 3-15).
Change-Id: I71be7c4de5d2e2e738b88984f13efb08f4388a19
|
| 9f975bfe091e9592a1b6b5b46d224ec04b1183b6 |
|
19-Jun-2014 |
Andreas Gampe <agampe@google.com> |
ART: Change rrr add and sub for ARM64
OpRegRegImm will fall back to loading a constant into a register
and then doing the operation with three registers. That is, for
example, the case when we allocate large stack frames. However,
the currently chosen operations are add/sub shifted, which does
*not* allow to specify SP (x31 will be interpreted as xzr). Switch
to add/sub extended. There won't be a practical difference, as we
do not call with anything other than 0 shift.
Change-Id: I2b78df9f044d2963e3e890777c855b339952f9f4
|
| 47b31aa855379471c06735b738396fa76e7c1988 |
|
19-Jun-2014 |
Andreas Gampe <agampe@google.com> |
ART: Start implementation of OpRegRegRegExtend for ARM64
We need a sign-extending add for packed-switch and sparse-switch,
as the 32b values are signed offsets. This starts an implementation
that is sufficient for the use cases.
Change-Id: Ib5bae24b902077346a97d5e9e061533f9cdfcdb0
|
| 33ae5583bdd69847a7316ab38a8fa8ccd63093ef |
|
12-Jun-2014 |
buzbee <buzbee@google.com> |
Arm64 hard-float
Basic enabling of hard-float for Arm64. In future CLs we'll
consolidate the various targets - there is a lot of overlap.
Compilation remains turned off in this CL, but I expect
to enable a subset shortly. With compilation fully enabled
(including the EXPERIMENTAL opcodes with the exception of
REM and THROW), we get the following run-test results:
003-omnibus-opcode failures:
Classes.checkCast
Classes.arrayInstance
UnresTest2
Haven't gone deep, but these appear to be related to throw/catch and/or
stacktrace.
For REM, the generated code looks reasonable to me - my guess is that
we've got something wrong on the transition to the runtime. Haven't
looked deeper yet, though.
The bulk of the other failure also appear to be related to transitioning
to the runtime system, or handling try/catch.
run-test status:
Status with optimizations disabled, REM_FLOAT/DOUBLE and THROW disabled:
succeeded tests: 94
failed tests: 22
failed: 003-omnibus-opcodes
failed: 004-annotations
failed: 009-instanceof2
failed: 024-illegal-access
failed: 025-access-controller
failed: 031-class-attributes
failed: 044-proxy
failed: 045-reflect-array
failed: 046-reflect
failed: 058-enum-order
failed: 062-character-encodings
failed: 063-process-manager
failed: 064-field-access
failed: 068-classloader
failed: 071-dexfile
failed: 083-compiler-regressions
failed: 084-class-init
failed: 086-null-super
failed: 087-gc-after-link
failed: 100-reflect2
failed: 107-int-math2
failed: 201-built-in-exception-detail-messages
Change-Id: Ib66209285cad8998d77a14781de300af02a96b15
|
| 5aa6e04061ced68cca8111af1e9c19781b8a9c5d |
|
14-Jun-2014 |
Ian Rogers <irogers@google.com> |
Tidy x86 assembler.
Use helper functions to compute when the kind has a SIB, a ModRM and RegReg
form.
Change-Id: I86a5cb944eec62451c63281265e6974cd7a08e07
|
| e2eb29e98be3ba72cce7da40847ab3d605b9455d |
|
12-Jun-2014 |
Zheng Xu <zheng.xu@arm.com> |
AArch64: Enable MOVE_*, some CONST_*, CMP_*.
With the fixes of GenArithImmOpLong, GenShiftOpLong, OpRegImm,
OpRegRegImm, OpRegRegImm64, EncodeLogicalImmediate and fmov.
Change-Id: I8cae4f921d5150a6b8e4803ca4dee553928d1a58
|
| 169489b4f4be8c5dd880ba6f152948324d22ff79 |
|
11-Jun-2014 |
Serban Constantinescu <serban.constantinescu@arm.com> |
AArch64: Add support for inlined methods
This patch adds support for Arm64 inlined methods.
Change-Id: Ic6aeed6d2d32f65cd1e63cf482f83cdcf958798a
|
| ffddfdf6fec0b9d98a692e27242eecb15af5ead2 |
|
03-Jun-2014 |
Tim Murray <timmurray@google.com> |
DO NOT MERGE
Merge ART from AOSP to lmp-preview-dev.
Change-Id: I0f578733a4b8756fd780d4a052ad69b746f687a9
|
| ed65c5e982705defdb597d94d1aa3f2997239c9b |
|
22-May-2014 |
Serban Constantinescu <serban.constantinescu@arm.com> |
AArch64: Enable LONG_* and INT_* opcodes.
This patch fixes some of the issues with LONG and INT opcodes. The patch
has been tested and passes all the dalvik tests except for 018 and 107.
Change-Id: Idd1923ed935ee8236ab0c7e5fa969eaefeea8708
Signed-off-by: Serban Constantinescu <serban.constantinescu@arm.com>
|
| b01bf15d18f9b08d77e7a3c6e2897af0e02bf8ca |
|
14-May-2014 |
buzbee <buzbee@google.com> |
64-bit temp register support.
Add a 64-bit temp register allocation path. The recent physical
register handling rework supports multiple views of the same
physical register (or, such as for Arm's float/double regs,
different parts of the same physical register).
This CL adds a 64-bit core register view for 64-bit targets. In
short, each core register will have a 64-bit name, and a 32-bit
name. The different views will be kept in separate register pools,
but aliasing will be tracked. The core temp register allocation
routines will be largely identical - except for 32-bit targets,
which will continue to use pairs of 32-bit core registers for holding
long values.
Change-Id: I8f118e845eac7903ad8b6dcec1952f185023c053
|
| bc6d197cdb02eeac0c98ec4ed37f530b003a4e7a |
|
13-May-2014 |
Matteo Franchin <matteo.franchin@arm.com> |
AArch64: fixes in A64 code generation.
- Disabled special method compilation, as it requires hard-float ABI,
- Disabled suspend checks, as runtime is not yet ready (e.g. trampolines
are not setting the suspend register, etc),
- Changing definition of zero register (the zero register has now 0x3f
as its register number),
- Fixing some issues with handling of cmp instructions in the assembler:
we now use the shift-register rather than the extended-register variant
of cmp and cmn,
- Partially fixing register setup (register sN is now mapped to dN),
- Fixing and completing implementation of register spills/unspills,
- Fixing LoadBaseDispBody() and StoreBaseDispBody().
Change-Id: Ia49ba48b6ca0f782380066345b7a198cb6c1dc1d
|
| c830430ed65497c2268649d8e78121364e31b184 |
|
15-May-2014 |
Zheng Xu <zheng.xu@arm.com> |
AArch64: Fix quick compiler monitor implementation.
Also with some small fixes :
1. Enable some dex byte code to compile.
2. Copy the register definition from runtime.cc.
3. A quick fix for "cmp Wn, Wm" in the assembler.
4. Optimise GenMoveException a bit by using xzr.
5. Fix improper use of StoreValueWide() on 32-bit value in FlushIns().
6. Fix one debug assert in the assembler.
It can pass all cases in run-all-test, except 044 which also fails with
the interpreter.
Change-Id: I9cc0253f1039c78d5100640235ac33e884b02560
|
| e45fb9e7976c8462b94a58ad60b006b0eacec49f |
|
06-May-2014 |
Matteo Franchin <matteo.franchin@arm.com> |
AArch64: Change arm64 backend to produce A64 code.
The arm backend clone is changed to produce A64 code. At the moment
this backend can only compile simple methods (both leaf and non-leaf).
Most of the work on the assembler (assembler_arm64.cc) has been done.
Some work on the LIR generation layer (functions such as OpRegRegImm
& friends) is still necessary. The register allocator still needs to
be adapted to the A64 instruction set (it is mostly unchanged from
the arm backend). Offsets for helpers in gen_invoke.cc still need to
be changed to work on 64-bit.
Change-Id: I388f99eeb832857981c7d9d5cb5b71af64a4b921
|
| 43ec8737d8356dbff0a90bee521fb0e73438da47 |
|
31-Mar-2014 |
Matteo Franchin <matteo.franchin@arm.com> |
AArch64: Added arm64 quick backend as an arm clone.
Created a new directory arm64 under compiler/dex/quick which contains
a copy of the 32-bit arm backend. In following CLs, this code will
be replaced/modified to support Aarch64.
Change-Id: I06c468db8d588e339eecf4d7d85276d5e334a17a
|