| 41b175aba41c9365a1c53b8a1afbd17129c87c14 |
|
19-May-2015 |
Vladimir Marko <vmarko@google.com> |
ART: Clean up arm64 kNumberOfXRegisters usage.
Avoid undefined behavior for arm64 stemming from 1u << 32 in
loops with upper bound kNumberOfXRegisters.
Create iterators for enumerating bits in an integer either
from high to low or from low to high and use them for
<arch>Context::FillCalleeSaves() on all architectures.
Refactor runtime/utils.{h,cc} by moving all bit-fiddling
functions to runtime/base/bit_utils.{h,cc} (together with
the new bit iterators) and all time-related functions to
runtime/base/time_utils.{h,cc}. Improve test coverage and
fix some corner cases for the bit-fiddling functions.
Bug: 13925192
(cherry picked from commit 80afd02024d20e60b197d3adfbb43cc303cf29e0)
Change-Id: I905257a21de90b5860ebe1e39563758f721eab82
|
| 4af147eb3296a26eea566f53a7f687194638d46b |
|
07-Apr-2015 |
Roland Levillain <rpl@google.com> |
Exercise art::arm::Thumb2Assembler::StoreToOffset for word pairs.
- Augment compiler/utils/arm/assembler_thumb2_test.cc.
- Ensure art::arm::Thumb2Assembler::StoreToOffset properly
handles IP as (implicit) second source register.
- Remove the parity constraint on the first source register
for art::arm::Thumb2Assembler::ldrd and
art::arm::Thumb2Assembler::strd (as they are not required
by the Thumb-2 encoding).
- Introduce additional versions of
art::arm::Thumb2Assembler::ldrd and
art::arm::Thumb2Assembler::strd accepting a second source
register, which is not necessarily the one following the
first source register, as it is allowed by the Thumb-2
encoding.
Change-Id: I7dba168437a96a5cbb117058e9c547fb1ff5c295
|
| 65b798ea10dd716c1bb3dda029f9bf255435af72 |
|
06-Apr-2015 |
Andreas Gampe <agampe@google.com> |
ART: Enable more Clang warnings
Change-Id: Ie6aba02f4223b1de02530e1515c63505f37e184c
|
| ca71458862be8505330b7fd5649a062f31d143dc |
|
04-Apr-2015 |
Andreas Gampe <agampe@google.com> |
ART: Add Clang's -Wused-but-marked-unused
Add detection of wrong unused annotations. Fix our codebase.
Change-Id: I85cc20f2eac71c1ec6c5c7cd6efb08454a629634
|
| ab4a2f5995b79c2b5b28c91b419a2c91cb88e377 |
|
11-Mar-2015 |
Guillaume "Vermeille" Sanchez <guillaumesa@google.com> |
Forbid the use of shifts in ShifterOperand in Thumb2
Change-Id: I4b3b4d90f11f2dd0c9a274b724051fa98982fb19
|
| dc62c48937a6476ed9c0d739f6b3b5c26f758371 |
|
11-Mar-2015 |
Guillaume "Vermeille" Sanchez <guillaumesa@google.com> |
Make subs and adds alter flags when rn is an immediate
Change-Id: I70e0d78f155bf806222ad12a324dbd8c8fe575a1
|
| 2dae78cbd4394a4498a845c6943992b57bd07b6e |
|
17-Mar-2015 |
Calin Juravle <calin@google.com> |
Revert "Make subs alter flags when rn is an immediate"
This reverts commit 8de00e3f5fcb99bfd7e4dc679ab7333549bec2c1.
Change-Id: Ie9da31279f565f165d51d8c0036928377280e3b8
|
| b7f2be9238e49db5d163d23e956d1bbec25da013 |
|
17-Mar-2015 |
Calin Juravle <calin@google.com> |
Revert "Forbid the use of shifts in ShifterOperand in Thumb2"
This reverts commit bada8b0f0a10bd32d6cb87ed4e57f2aa3d7c03c2.
Change-Id: Ic89c76367c8ab91cfb5d1510789ac2e352922da8
|
| 8de00e3f5fcb99bfd7e4dc679ab7333549bec2c1 |
|
11-Mar-2015 |
Guillaume "Vermeille" Sanchez <guillaumesa@google.com> |
Make subs alter flags when rn is an immediate
Change-Id: I7ea84fca5f97713871744b8ac4265a84fd6a5248
|
| bada8b0f0a10bd32d6cb87ed4e57f2aa3d7c03c2 |
|
11-Mar-2015 |
Guillaume "Vermeille" Sanchez <guillaumesa@google.com> |
Forbid the use of shifts in ShifterOperand in Thumb2
Change-Id: Ib141f53e52cce3032a42fbc991303e227c98820b
|
| ab1eb0d1d047e3478ebb891e5259d2f1d1dd78bd |
|
14-Feb-2015 |
Andreas Gampe <agampe@google.com> |
ART: Templatize IsInt & IsUint
Ensure that things are used correctly.
Change-Id: I76f082b32dcee28bbfb4c519daa401ac595873b3
|
| 3d1e788a53cb2eb87a39cf7e1a58be98dc567a67 |
|
03-Feb-2015 |
Nicolas Geoffray <ngeoffray@google.com> |
Fix build by putting ATTRIBUTE_UNUSUED.
Change-Id: If894fa1343a7c8a6456d707e815d803404a171d7
|
| 51fdf43a5a53db624ff637d0aae05e2d47e59af2 |
|
03-Feb-2015 |
Nicolas Geoffray <ngeoffray@google.com> |
Fix thumb2 assembler's ShifterOperandCanHold.
Change-Id: Ica3c5f39d52722950725ba622fc67bd7f634918a
|
| 7b7e524c86a67f7357bbcfd0e7bde07ded50cca2 |
|
03-Feb-2015 |
Andreas Gampe <agampe@google.com> |
ART: Fix assembler_thumb_test
Fix the inconsistent calls. This was bad practice, requiring that
shape meant arm32 and thumb were not interchangeable.
Also fix an error in the assembler itself for tst and teq.
Change-Id: I50242801002aa81cc17bfaa53eb8b7c1d9488fbc
|
| 513ea0c203a86e9d81a8630b56cb62704e126cc2 |
|
02-Feb-2015 |
Andreas Gampe <agampe@google.com> |
ART: Fix thumb2 utils assembler
It didn't correctly put down the 16b variants, as it was not
checking the ShifterOperand correctly.
Add one simple test. TODO: exhaustive testing.
Change-Id: Ied08da115f8417a3ca92bd9967c6dcdc102e7510
|
| 52c489645b6e9ae33623f1ec24143cde5444906e |
|
16-Dec-2014 |
Calin Juravle <calin@google.com> |
[optimizing compiler] Add support for volatile
- for backends: arm, x86, x86_64
- added necessary instructions to assemblies
- clean up code gen for field set/get
- fixed InstructionDataEquals for some instructions
- fixed comments in compiler_enums
* 003-opcode test verifies basic volatile functionality
Change-Id: I144393efa312dfb2c332cb84056b00edffee338a
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| ac0341e4ca2a8f81e846465fb56d49da22b199ed |
|
18-Dec-2014 |
Vladimir Marko <vmarko@google.com> |
Fix Thumb2 Emit16BitAddSub() to keep full immediate.
Change-Id: I2d4b44752150669119ead16e99f7d7a945d2e88f
|
| 5bc561c31d119a964e54cf73b475f8eac044d905 |
|
16-Dec-2014 |
Vladimir Marko <vmarko@google.com> |
Fix Thumb2 assembler to emit 16-bit add/sub SP, #imm.
Also allow 16-bit add rN, SP, #imm.
Change-Id: I50100ad0b0e19a1c855a2319615e86d7a2b66a69
|
| 3bcc8ea079d867f26622defd0611d134a3b4ae49 |
|
28-Nov-2014 |
Nicolas Geoffray <ngeoffray@google.com> |
Don't use CanHoldArm in the code generator.
CanHoldArm was ARM32 specific. Instead use a virtual
Assembler::ShifterOperandCanHold that both thumb2 and arm32
implement.
Change-Id: I33794a93caf02ee5d78d32a8471d9fd6fe4f0a00
|
| ddb7df25af45d7cd19ed1138e537973735cc78a5 |
|
25-Nov-2014 |
Calin Juravle <calin@google.com> |
[optimizing compiler] Add CMP{L,G}_{FLOAT,DOUBLE}
Adds:
- float comparison for arm, x86, x86_64 backends.
- ucomis{s,d} assembly to x86 and x86_64.
- vmstat assebmly for thumb2
- new assembly tests
Change-Id: Ie3e19d0c08b3b875cd0a4be4ee4e9c8a4a076290
|
| e8469c195570ccfda248b4392472421bc0940987 |
|
26-Nov-2014 |
Vladimir Marko <vmarko@google.com> |
Optimizing: Use 16-bit Thumb2 PUSH/POP when possible.
JNI compiler uses the same assembler but always pushes
and pops registers that require the 32-bit PUSH/POP.
Change-Id: I7e857ae799316586cd09d6547cf971ef439af147
|
| 9aec02fc5df5518c16f1e5a9b6cb198a192db973 |
|
19-Nov-2014 |
Calin Juravle <calin@google.com> |
[optimizing compiler] Add shifts
Added SHL, SHR, USHR for arm, x86, x86_64.
Change-Id: I971f594e270179457e6958acf1401ff7630df07e
|
| 8366ca0d7ba3b80a2d5be65ba436446cc32440bd |
|
17-Nov-2014 |
Elliott Hughes <enh@google.com> |
Fix the last users of TARGET_CPU_SMP.
Everyone else assumes SMP.
Change-Id: I7ff7faef46fbec6c67d6e446812d599e473cba39
|
| 981e45424f52735b1c61ae0eac7e299ed313f8db |
|
14-Nov-2014 |
Roland Levillain <rpl@google.com> |
Add support for int-to-char in the optimizing compiler.
- Add support for the int-to-char Dex instruction in the
optimizing compiler.
- Implement the ARM and Thumb-2 UBFX instructions and add
tests for them.
- Generate x86, x86-64 and ARM (but not ARM64) code for
byte to char, short to char, int to char (and char to
char!) HTypeConversion nodes.
- Add related tests to test/422-type-conversion.
Change-Id: I5cd4c6d86f0f6a966c059715b98db35cc8f9de76
|
| 51d3fc40637fc73d4156ad617cd451b844cbb75e |
|
13-Nov-2014 |
Roland Levillain <rpl@google.com> |
Add support for int-to-byte in the optimizing compiler.
- Add support for the int-to-byte Dex instruction in the
optimizing compiler.
- Implement the ARM and Thumb-2 SBFX instructions.
- Generate x86, x86-64 and ARM (but not ARM64) code for
char to byte, short to byte and int to byte
HTypeConversion nodes.
- Add related tests to test/422-type-conversion.
Change-Id: Ic8b8911b90d4b5281fad15bcee96bc3ee85dc577
|
| 277ccbd200ea43590dfc06a93ae184a765327ad0 |
|
04-Nov-2014 |
Andreas Gampe <agampe@google.com> |
ART: More warnings
Enable -Wno-conversion-null, -Wredundant-decls and -Wshadow in general,
and -Wunused-but-set-parameter for GCC builds.
Change-Id: I81bbdd762213444673c65d85edae594a523836e5
|
| 775ef49bad8e8d9d02fc5968858dce6a00a78475 |
|
04-Nov-2014 |
Roland Levillain <rpl@google.com> |
Fix store instructions to large frames in ARM opt. compiler.
When accessing a stack frame at a large offset, use an
additional core register (R5 or R6) as a temporary register
whenever IP contains the value to store (and thus cannot be
used by art::Thumb2Assembler::StoreToOffset as a temporary
register to compute the memory address where the value is
to be stored). The previous value of R5 (or R6) is saved
on the stack before the emission of the store instruction
and restored afterwards.
Change-Id: Ic5fd5ab2c09d8327dd1f0f241d40d2c397ce64cd
|
| 6a3c1fcb4ba42ad4d5d142c17a3712a6ddd3866f |
|
31-Oct-2014 |
Ian Rogers <irogers@google.com> |
Remove -Wno-unused-parameter and -Wno-sign-promo from base cflags.
Fix associated errors about unused paramenters and implict sign conversions.
For sign conversion this was largely in the area of enums, so add ostream
operators for the effected enums and fix tools/generate-operator-out.py.
Tidy arena allocation code and arena allocated data types, rather than fixing
new and delete operators.
Remove dead code.
Change-Id: I5b433e722d2f75baacfacae4d32aef4a828bfe1b
|
| 19a19cffd197a28ae4c9c3e59eff6352fd392241 |
|
22-Oct-2014 |
Nicolas Geoffray <ngeoffray@google.com> |
Add support for static fields in optimizing compiler.
Change-Id: Id2f010589e2bd6faf42c05bb33abf6816ebe9fa9
|
| 2c4257be8191c5eefde744e8965fcefc80a0a97d |
|
24-Oct-2014 |
Ian Rogers <irogers@google.com> |
Tidy logging code not using UNIMPLEMENTED.
Change-Id: I7a79c1671a6ff8b2040887133b3e0925ef9a3cfe
|
| 35c68e3018d0066eec8e374897d5cf07e1360729 |
|
30-Sep-2014 |
Andreas Gampe <agampe@google.com> |
ART: Fix typo
Fixes a miss-translation in the pedantic change.
Change-Id: Ibdce896bf3667e06f10d60f160803451096b08ba
|
| c8ccf68b805c92674545f63e0341ba47e8d9701c |
|
30-Sep-2014 |
Andreas Gampe <agampe@google.com> |
ART: Fix some -Wpedantic errors
Remove extra semicolons.
Dollar signs in C++ identifiers are an extension.
Named variadic macros are an extension.
Binary literals are a C++14 feature.
Enum re-declarations are not allowed.
Overflow.
Change-Id: I7d16b2217b2ef2959ca69de84eaecc754517714a
|
| 3c7bb98698f77af10372cf31824d3bb115d9bf0f |
|
23-Jul-2014 |
Nicolas Geoffray <ngeoffray@google.com> |
Implement array get and array put in optimizing.
Also fix a couple of assembler/disassembler issues.
Change-Id: I705c8572988c1a9c4df3172b304678529636d5f6
|
| 1a43dd78d054dbad8d7af9ba4829ea2f1cb70b53 |
|
17-Jul-2014 |
Nicolas Geoffray <ngeoffray@google.com> |
Add write barriers to optimizing compiler.
Change-Id: I43a40954757f51d49782e70bc28f7c314d6dbe17
|
| 96f89a290eb67d7bf4b1636798fa28df14309cc7 |
|
11-Jul-2014 |
Nicolas Geoffray <ngeoffray@google.com> |
Add assembly operations with constants in optimizing compiler.
Change-Id: I5bcc35ab50d4457186effef5592a75d7f4e5b65f
|
| 8d486731559ba0c5e12c27b4a507181333702b7e |
|
16-Jul-2014 |
Nicolas Geoffray <ngeoffray@google.com> |
Use the thumb2 assembler for the optimizing compiler.
Change-Id: I2b058f4433504dc3299c06f5cb0b5ab12f34aa82
|
| 0bb9ade51635559f991259a7ac90d8570ad886aa |
|
27-Jun-2014 |
Dave Allison <dallison@google.com> |
Fix off-by-one errors in limit checking for ldr/str instructions.
The LDR/STR encoder in the thumb assembler had an off-by-one
error for limit checking for immediates. This resulted in an
assertion failure for things like 'ldr rx,[ry,#128]'
Bug: 15876206
Change-Id: Ic866212e2feae94e0bd4c753724898d84f5cb944
|
| 45fdb93f04b981f70f7b6d98949ab3986b7331f8 |
|
25-Jun-2014 |
Dave Allison <dallison@google.com> |
Support additional instructions in ARM and thumb assemblers
This adds the following support for the ARM and thumb assemblers:
1. Shifting by a register.
2. LDR/STR with a register offset, possibly shifted.
3. LDR(literal).
4. STR PC relative.
Also adds tests for them in the thumb assembler gtest.
Change-Id: Ie467e3c1d06b699cacbdef3482ed9a92e4f1809b
|
| 20dfc797dc631bf8d655dcf123f46f13332d3074 |
|
17-Jun-2014 |
Dave Allison <dallison@google.com> |
Add some more instruction support to optimizing compiler.
This adds a few more DEX instructions to the optimizing compiler's
builder (constants, moves, if_xx, etc).
Also:
* Changes the codegen for IF_XX instructions to use a condition
rather than comparing a value against 0.
* Fixes some instructions in the ARM disassembler.
* Fixes PushList and PopList in the thumb2 assembler.
* Switches the assembler for the optimizing compiler to thumb2
rather than ARM.
Change-Id: Iaafcd02243ccc5b03a054ef7a15285b84c06740f
|
| 65fcc2cf3c5cd97b84330c094908f3a6a7a8d4e7 |
|
28-Apr-2014 |
Dave Allison <dallison@google.com> |
Thumb2 assembler for JNI compiler and optimizing compiler
This provides a programmatic assembler for the thumb2 instruction set for
ARM. The interface is the same as the ARM assembler and the ARM assembler has
been moved into Arm32Assembler. The assembler handles most 16 and 32 bit instructions
and also allows relocations due to branch expansion. It will also rewrite cbz/cbnz
instructions if they go out of range.
It also changes the JNI compiler to use the thumb2 assembler as opposed
to forcing it to use ARM32. The trampoline compiler still uses ARM due to the
way it returns the address of its generated code. A trampoline in thumb2 is the
same size as that in ARM anyway (8 bytes).
Provides gtest for testing the thumb2 instruction output. This gtest only runs
on the host as it uses arm-eabi-objdump to disassemble the generated code. On the
target the output is not checked but the assembler will still be run to perform
all its checks.
Change-Id: Icd9742b6f13541bec5b23097896727392e3a6fb6
|