History log of /art/compiler/utils/arm64/assembler_arm64.cc
Revision Date Author Comments
7f57e8c60ec31461151a8bfdd2b3fabfa78cb3f5 27-Oct-2015 Andreas Gampe <agampe@google.com> [WIP] ART: Write-protect TLS

Change-Id: I6762a3a30d01bd6eb8bb25f23f390c91147fe9b4
3d21bdf8894e780d349c481e5c9e29fe1556051c 22-Apr-2015 Mathieu Chartier <mathieuc@google.com> Move mirror::ArtMethod to native

Optimizing + quick tests are passing, devices boot.

TODO: Test and fix bugs in mips64.

Saves 16 bytes per most ArtMethod, 7.5MB reduction in system PSS.
Some of the savings are from removal of virtual methods and direct
methods object arrays.

Bug: 19264997

(cherry picked from commit e401d146407d61eeb99f8d6176b2ac13c4df1e33)

Change-Id: I622469a0cfa0e7082a2119f3d6a9491eb61e3f3d

Fix some ArtMethod related bugs

Added root visiting for runtime methods, not currently required
since the GcRoots in these methods are null.

Added missing GetInterfaceMethodIfProxy in GetMethodLine, fixes
--trace run-tests 005, 044.

Fixed optimizing compiler bug where we used a normal stack location
instead of double on ARM64, this fixes the debuggable tests.

TODO: Fix JDWP tests.

Bug: 19264997

Change-Id: I7c55f69c61d1b45351fd0dc7185ffe5efad82bd3

ART: Fix casts for 64-bit pointers on 32-bit compiler.

Bug: 19264997
Change-Id: Ief45cdd4bae5a43fc8bfdfa7cf744e2c57529457

Fix JDWP tests after ArtMethod change

Fixes Throwable::GetStackDepth for exception event detection after
internal stack trace representation change.

Adds missing ArtMethod::GetInterfaceMethodIfProxy call in case of
proxy method.

Bug: 19264997
Change-Id: I363e293796848c3ec491c963813f62d868da44d2

Fix accidental IMT and root marking regression

Was always using the conflict trampoline. Also included fix for
regression in GC time caused by extra roots. Most of the regression
was IMT.

Fixed bug in DumpGcPerformanceInfo where we would get SIGABRT due to
detached thread.

EvaluateAndApplyChanges:
From ~2500 -> ~1980
GC time: 8.2s -> 7.2s due to 1s less of MarkConcurrentRoots

Bug: 19264997
Change-Id: I4333e80a8268c2ed1284f87f25b9f113d4f2c7e0

Fix bogus image test assert

Previously we were comparing the size of the non moving space to
size of the image file.

Now we properly compare the size of the image space against the size
of the image file.

Bug: 19264997
Change-Id: I7359f1f73ae3df60c5147245935a24431c04808a

[MIPS64] Fix art_quick_invoke_stub argument offsets.

ArtMethod reference's size got bigger, so we need to move other args
and leave enough space for ArtMethod* and 'this' pointer.

This fixes mips64 boot.

Bug: 19264997
Change-Id: I47198d5f39a4caab30b3b77479d5eedaad5006ab
41b175aba41c9365a1c53b8a1afbd17129c87c14 19-May-2015 Vladimir Marko <vmarko@google.com> ART: Clean up arm64 kNumberOfXRegisters usage.

Avoid undefined behavior for arm64 stemming from 1u << 32 in
loops with upper bound kNumberOfXRegisters.

Create iterators for enumerating bits in an integer either
from high to low or from low to high and use them for
<arch>Context::FillCalleeSaves() on all architectures.

Refactor runtime/utils.{h,cc} by moving all bit-fiddling
functions to runtime/base/bit_utils.{h,cc} (together with
the new bit iterators) and all time-related functions to
runtime/base/time_utils.{h,cc}. Improve test coverage and
fix some corner cases for the bit-fiddling functions.

Bug: 13925192

(cherry picked from commit 80afd02024d20e60b197d3adfbb43cc303cf29e0)

Change-Id: I905257a21de90b5860ebe1e39563758f721eab82
69a503050fb8a7b3a79b2cd2cdc2d8fbc594575d 14-Apr-2015 Zheng Xu <zheng.xu@arm.com> ARM64: Remove suspend register.

It also clean up build/remove frame used by JNI compiler and generates
stp/ldp instead of str/ldr. Also x19 has been unblocked in both quick and
optimizing compiler.

Change-Id: Idbeac0942265f493266b2ef9b7a65bb4054f0e2d
dd97393aca1a3ff2abec4dc4f78d7724300971bc 07-Apr-2015 David Srbecky <dsrbecky@google.com> Implement CFI for JNI.

CFI is necessary for stack unwinding in gdb, lldb, and libunwind.

Change-Id: I37eb7973f99a6975034cf0e699e138c3a9aba10f
7cde48c56df5b57aed524cce44c902bc720f2d6c 20-Jan-2015 Sebastien Hertz <shertz@google.com> Stack support for Optimizing compiler

Allows to read/write DEX registers from physical register or stack
location when the method is compiled with the Optimizing compiler.

Required fixing arm and arm64 JNI compiler by saving floating
point registers.

Bug: 18547544
Change-Id: I401579f251d1c0a130f6cf4a93a960cdcd7518f5
32f5b4d2c8c9b52e9522941c159577b21752d0fa 25-Nov-2014 Serban Constantinescu <serban.constantinescu@arm.com> Vixl: Update the VIXL interface to VIXL 1.7 and enable VIXL debug.

This patch updates the interface to VIXL 1.7 and enables the debug version of
VIXL when ART is built in debug mode.

Change-Id: I443fb941bec3cffefba7038f93bb972e6b7d8db5
Signed-off-by: Serban Constantinescu <serban.constantinescu@arm.com>
8366ca0d7ba3b80a2d5be65ba436446cc32440bd 17-Nov-2014 Elliott Hughes <enh@google.com> Fix the last users of TARGET_CPU_SMP.

Everyone else assumes SMP.

Change-Id: I7ff7faef46fbec6c67d6e446812d599e473cba39
6a3c1fcb4ba42ad4d5d142c17a3712a6ddd3866f 31-Oct-2014 Ian Rogers <irogers@google.com> Remove -Wno-unused-parameter and -Wno-sign-promo from base cflags.

Fix associated errors about unused paramenters and implict sign conversions.
For sign conversion this was largely in the area of enums, so add ostream
operators for the effected enums and fix tools/generate-operator-out.py.
Tidy arena allocation code and arena allocated data types, rather than fixing
new and delete operators.
Remove dead code.

Change-Id: I5b433e722d2f75baacfacae4d32aef4a828bfe1b
37c92df53979f9f6ab83155ab9521d554d717161 17-Oct-2014 Alexandre Rames <alexandre.rames@arm.com> Rename arm64 `Register` to `XRegister`.

This will avoid naming conflicts in the arm64 port of
the optimizing compiler.

Change-Id: Ie736ddd2ddbd2e299058256de28bad5d41c57d6f
cee7524afa53216fcd13df8122ece495548a829c 08-Oct-2014 Alexandre Rames <alexandre.rames@arm.com> ARM64: Update code after the VIXL 1.6 release.

We now leave the assembler buffer management to VIXL.

Change-Id: Ieefe83cf5cf5e1ab8c924b0e7dc03af6a55053ae
b88f0b16dbaff09a140d2a62b66eca2736ff514b 26-Sep-2014 Hiroshi Yamauchi <yamauchi@google.com> Get heap poisoning working in 64-bit.

This adds the reference negate code in arm64 and x86_64 that's used by
the jni compiler.

Bug: 12687968
Bug: 8367515
Change-Id: I28a44bcead1ee613866645620b4eaf54fad6a3aa
ba9388c14381400bcc3f6bc327331fbaca12602a 22-Aug-2014 Alexandre Rames <alexandre.rames@arm.com> ARM64: Avoid the duplication of condition codes.
b551fdcda9eb128c80de37c4fb978968bec6d4b3 25-Jul-2014 Zheng Xu <zheng.xu@arm.com> AArch64: Clean up CalleeSaveMethod frame and the use of temp registers.

CalleeSaveMethod frame size changes :
SaveAll : 368 -> 176
RefOnly : 176 -> 96
RefsAndArgs : 304 -> 224

JNI register spill size changes :
160 -> 88

In the transition assembly, use registers following the rules:
1. x0-x7 as temp/argument registers.
2. IP0, IP1 as scratch registers.
3. After correct type of callee-save-frame has been setup, all registers
are scratch-able(probably except xSELF and xSUSPEND).
4. When restore callee-save-frame, IP0 and IP1 should be untouched.
5. From C to managed code, we assume all callee save register in AAPCS
will be restored by managed code except x19(SUSPEND).

In quick compiler:
1. Use IP0, IP1 as scratch register.
2. Use IP1 as hidden argument register(IP0 will be scratched by
trampoline.)

Change-Id: I05ed9d418b01b9e87218a7608536f57e7a286e4c
094192464e961d5e63c53a9644ba72d79fb56ead 08-May-2014 Serban Constantinescu <serban.constantinescu@arm.com> ART: Fuse compare-with-0-and-branch in Arm64 utils-assembler

This patch squashes the use of cmp + b to cbz.

Change-Id: I3d146a9921c471f08ba7304f1ca1b427d8e7dcf9
Signed-off-by: Serban Constantinescu <serban.constantinescu@arm.com>
ffddfdf6fec0b9d98a692e27242eecb15af5ead2 03-Jun-2014 Tim Murray <timmurray@google.com> DO NOT MERGE

Merge ART from AOSP to lmp-preview-dev.

Change-Id: I0f578733a4b8756fd780d4a052ad69b746f687a9
cf4035a4c41ccfcc3e89a0cee25f5218a11b0705 29-May-2014 Andreas Gampe <agampe@google.com> ART: Use StackReference in Quick Stack Frame

The method reference at the bottom of a quick frame is a stack
reference and not a native pointer. This is important for 64b
architectures, where the notions do not coincide.

Change key methods to have StackReference<mirror::ArtMethod>*
parameter instead of mirror::ArtMethod**. Make changes to
invoke stubs for 64b archs, change the frame setup for JNI code
(both generic JNI and compilers), tie up loose ends.

Tested on x86 and x86-64 with host tests. On x86-64, tests succeed
with jni compiler activated. x86-64 QCG was not tested.

Tested on ARM32 with device tests.

Fix ARM64 not saving x19 (used for wSUSPEND) on upcalls.

Tested on ARM64 in interpreter-only + generic-jni mode.

Fix ARM64 JNI Compiler to work with the CL.

Tested on ARM64 in interpreter-only + jni compiler.

Change-Id: I77931a0cbadd04d163b3eb8d6f6a6f8740578f13
eb8167a4f4d27fce0530f6724ab8032610cd146b 08-May-2014 Mathieu Chartier <mathieuc@google.com> Add Handle/HandleScope and delete SirtRef.

Delete SirtRef and replaced it with Handle. Handles are value types
which wrap around StackReference*.

Renamed StackIndirectReferenceTable to HandleScope.

Added a scoped handle wrapper which wraps around an Object** and
restores it in its destructor.

Renamed Handle::get -> Get.

Bug: 8473721

Change-Id: Idbfebd4f35af629f0f43931b7c5184b334822c7a
0f89dac7336251f7921621a926319d461837840f 08-May-2014 Serban Constantinescu <serban.constantinescu@arm.com> AArch64: Fix the usage of IP0, IP1 as temporary registers

This patch fixes the usage of temporary registers by using VIXL's
UseScratchRegisterScope. For the primitives used by the trampoline
compiler we explicitly exclude IP0, IP1 from the temporary list.

Change-Id: Icf9afbabd93214302891ddd536ce03a9c181463b
Signed-off-by: Serban Constantinescu <serban.constantinescu@arm.com>
63206f3038d3d6e1cb24166726613808a4b0ad8c 07-May-2014 Serban Constantinescu <serban.constantinescu@arm.com> AArch64: Fix the usage of Thread Register for arm64

This patch cleans-up the usage of x18 as TR for Arm64. As described in
the Arm64 Procedure Call Standard, the recommended usage for x18 is to
carry inter-procedural state (i.e. ART thread information).

However, since x18 is a temporary register there is no guarantee that on
calls to external functions x18 is preserved. Thus on JNI calls we need
to save and restore x18 before coming back to managed runtime. For the
JNI compiler trampoline we move x18 (temporary register - caller saved)
to x19 (ETR, callee saved) before calling into native code, and
restore it on the way back.

Change-Id: If24091018d640027a497517a9238bf4a80d013aa
Signed-off-by: Serban Constantinescu <serban.constantinescu@arm.com>
d1104322e5156669767e8b2c3b843ffaff173381 01-May-2014 Andreas Gampe <agampe@google.com> ART: aarch64 jni compiler needs to extend small return types

As aarch64 calling convention does not mandate extension on return
values anymore and leaves the upper bits undefined, the jni compiler
needs to sign- or zero-extend the returned values when necessary.

As three architectures need extension now, refactor this fact into a
flag into a virtual method.

Add tests to JniTest that exercise the required extension.

Change-Id: Idebb7c4dedebb852e58ade63e1c2b1eeced23104
75b9113b2b0a5807043af2a669a93d1579af8e2c 09-Apr-2014 Serban Constantinescu <serban.constantinescu@arm.com> AArch64: Jni compiler fixes

This patch fixes some of the issues with the ARM64 assembler and JNI
compiler.

The JNI compiler is not enabled by default, yet. To enable, change
line 1884 in compiler/driver/compiler_driver.cc, removing kArm64 from
the GenericJNI list.

The compiler passes all tests in jni_compiler_test.

Also change the common_compiler_test instruction-set-features logic.
We allow tests when the build-time features are a subset of the
runtime features.

Dex2oat cross-compiling is now working. A 32b version of dex2oat should
be able to compile correctly.

Change-Id: I51d1c24f2c75d4397a11c54724a8b277ff3b3df8
Signed-off-by: Serban Constantinescu <serban.constantinescu@arm.com>
790a6b7312979513710c366b411ba6791ddf78c2 01-Apr-2014 Ian Rogers <irogers@google.com> Calling convention support for cross 64/32 compilation.

Add REX support for x86-64 operands.

Change-Id: I093ae26fb8c111d54b8c72166f054984564c04c6
dd7624d2b9e599d57762d12031b10b89defc9807 15-Mar-2014 Ian Rogers <irogers@google.com> Allow mixing of thread offsets between 32 and 64bit architectures.

Begin a more full implementation x86-64 REX prefixes.
Doesn't implement 64bit thread offset support for the JNI compiler.

Change-Id: If9af2f08a1833c21ddb4b4077f9b03add1a05147
fca82208f7128fcda09b6a4743199308332558a2 21-Mar-2014 Dmitry Petrochenko <dmitry.petrochenko@intel.com> x86_64: JNI compiler

Passed all tests from jni_compiler_test and art/test on host with jni_copiler.
Incoming argument spill is enabled, entry_spills refactored. Now each entry spill
contains data type size (4 or 8) and offset which should be used for spill.
Assembler REX support implemented in opcodes used in JNI compiler.
Please note, JNI compiler is not enabled by default yet (see compiler_driver.cc:1875).

Change-Id: I5fd19cca72122b197aec07c3708b1e80c324be44
Signed-off-by: Dmitry Petrochenko <dmitry.petrochenko@intel.com>
c6ee54e9a9fd67d24c63bd802ef2fe540a4f86a5 25-Mar-2014 Andreas Gampe <agampe@google.com> Trampoline and assembly fixes for ARM64

Trampolines need a jump, not a call. Expose br in the ARM64
assembler to allow this.

The resolution trampoline is called with the Quick ABI, and will
continue to a Quick ABI function. Then the method pointer must be
in x0.

Change-Id: I4e383b59d6c40a659d324a7faef3fadf0c890178
ed8dd492e43cbaaa435c4892447072c84dbaf2dc 11-Feb-2014 Serban Constantinescu <serban.constantinescu@arm.com> AArch64: Add ARM64 Assembler

This patch adds the ARM64 Assembler and ManagedRegister backend.
The implementation of the Arm64Assembler class is based on VIXL (a
programmatic A64 Assembler - see external/vixl ).

Change-Id: I842fd574637a953c19631eedf26f6c70d9ed7f9e
Signed-off-by: Serban Constantinescu <serban.constantinescu@arm.com>