History log of /external/llvm/lib/Target/ARM/ARMSubtarget.cpp
Revision Date Author Comments (<<< Hide modified files) (Show modified files >>>)
2c3e0051c31c3f5b2328b447eadf1cf9c4427442 06-May-2015 Pirama Arumuga Nainar <pirama@google.com> Update aosp/master LLVM for rebase to r235153

Change-Id: I9bf53792f9fc30570e81a8d80d296c681d005ea7
(cherry picked from commit 0c7f116bb6950ef819323d855415b2f2b0aad987)
/external/llvm/lib/Target/ARM/ARMSubtarget.cpp
4c5e43da7792f75567b693105cc53e3f1992ad98 08-Apr-2015 Pirama Arumuga Nainar <pirama@google.com> Update aosp/master llvm for rebase to r233350

Change-Id: I07d935f8793ee8ec6b7da003f6483046594bca49
/external/llvm/lib/Target/ARM/ARMSubtarget.cpp
ebe69fe11e48d322045d5949c83283927a0d790b 23-Mar-2015 Stephen Hines <srhines@google.com> Update aosp/master LLVM for rebase to r230699.

Change-Id: I2b5be30509658cb8266be782de0ab24f9099f9b9
/external/llvm/lib/Target/ARM/ARMSubtarget.cpp
37ed9c199ca639565f6ce88105f9e39e898d82d0 01-Dec-2014 Stephen Hines <srhines@google.com> Update aosp/master LLVM for rebase to r222494.

Change-Id: Ic787f5e0124df789bd26f3f24680f45e678eef2d
/external/llvm/lib/Target/ARM/ARMSubtarget.cpp
c6a4f5e819217e1e12c458aed8e7b122e23a3a58 21-Jul-2014 Stephen Hines <srhines@google.com> Update LLVM for rebase to r212749.

Includes a cherry-pick of:
r212948 - fixes a small issue with atomic calls

Change-Id: Ib97bd980b59f18142a69506400911a6009d9df18
/external/llvm/lib/Target/ARM/ARMSubtarget.cpp
dce4a407a24b04eebc6a376f8e62b41aaa7b071f 29-May-2014 Stephen Hines <srhines@google.com> Update LLVM for 3.5 rebase (r209712).

Change-Id: I149556c940fb7dc92d075273c87ff584f400941f
/external/llvm/lib/Target/ARM/ARMSubtarget.cpp
36b56886974eae4f9c5ebc96befd3e7bfe5de338 24-Apr-2014 Stephen Hines <srhines@google.com> Update to LLVM 3.5a.

Change-Id: Ifadecab779f128e62e430c2b4f6ddd84953ed617
/external/llvm/lib/Target/ARM/ARMSubtarget.cpp
373aa5c665fe6df6b9c5586d397dc3617f25aab5 07-Feb-2014 Stephen Hines <srhines@google.com> Update LLVM for merge to 3.4.

Update config.h files.

Add RS SubtargetFeature for +long64 on ARM devices.

Adjust Android.mk for added/removed files:

+ Delinearization.cpp
- PathNumbering.cpp
- PathProfileInfo.cpp
- PathProfileVerifier.cpp
- ProfileDataLoader.cpp
- ProfileDataLoaderPass.cpp
- ProfileEstimatorPass.cpp
- ProfileInfo.cpp
- ProfileInfoLoader.cpp
- ProfileInfoLoaderPass.cpp
- ProfileVerifierPass.cpp

+ LiveRegUnits.cpp
- ShrinkWrapping.cpp
+ StackMaps.cpp
- StrongPHIElimination.cpp

+ DIEHash.cpp

+ LegacyPassManager.cpp

+ ELF.cpp

+ Unicode.cpp

- MipsOptimizeMathLibCalls.cpp

- MipsELFStreamer.cpp
+ MipsTargetStreamer.cpp

- EdgeProfiling.cpp
+ DataFlowSanitizer.cpp
+ DebugIR.cpp
- OptimalEdgeProfiling.cpp
- PathProfiling.cpp
- ProfilingUtils.cpp

- BasicBlockPlacement.cpp
+ LoopRerollPass.cpp
+ PartiallyInlineLibCalls.cpp
+ SampleProfile.cpp

+ GlobalStatus.cpp

Change-Id: I17dcf0bf53a1720acd8226ae3e30d84993562a91
/external/llvm/lib/Target/ARM/ARMSubtarget.cpp
ce9904c6ea8fd669978a8eefb854b330eb9828ff 12-Feb-2014 Stephen Hines <srhines@google.com> Merge remote-tracking branch 'upstream/release_34' into merge-20140211

Conflicts:
lib/Linker/LinkModules.cpp
lib/Support/Unix/Signals.inc

Change-Id: Ia54f291fa5dc828052d2412736e8495c1282aa64
929bdb23794b615dc6b0cc59db21f0450c3ce33b 13-Nov-2013 Weiming Zhao <weimingz@codeaurora.org> Enable generating legacy IT block for AArch32

By default, the behavior of IT block generation will be determinated
dynamically base on the arch (armv8 vs armv7). This patch adds backend
options: -arm-restrict-it and -arm-no-restrict-it. The former one
restricts the generation of IT blocks (the same behavior as thumbv8) for
both arches. The later one allows the generation of legacy IT block (the
same behavior as ARMv7 Thumb2) for both arches.

Clang will support -mrestrict-it and -mno-restrict-it, which is
compatible with GCC.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194592 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.cpp
cb01efb7988d119d6e2aedab1740695aa6a9cc0c 03-Nov-2013 Bob Wilson <bob.wilson@apple.com> Enable optimization of sin / cos pair into call to __sincos_stret for iOS7+.

rdar://12856873
Patch by Evan Cheng, with a fix for rdar://13209539 by Tilmann Scheller

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193942 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.cpp
6186de5c54b580414b2d162e0f335b62b3d9812c 01-Nov-2013 Bradley Smith <bradley.smith@arm.com> [ARM] Add Virtualization subtarget feature and more build attributes in this area

Add a Virtualization ARM subtarget feature along with adding proper build
attribute emission for Tag_Virtualization_use (encodes Virtualization and
TrustZone) and Tag_MPextension_use.

Also rework test/CodeGen/ARM/2010-10-19-mc-elf-objheader.ll testcase to
something that is more maintainable. This changes the focus of this
testcase away from testing CPU defaults (which is tested elsewhere), onto
specifically testing that attributes are encoded correctly.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193859 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.cpp
57bca7b26ec916ca1b74b1408608a6c69a1aa422 29-Oct-2013 Amara Emerson <amara.emerson@arm.com> [ARM] Make sure HasCRC is initialized to false in Subtarget.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193624 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.cpp
ca7b2d08d7b918e5e8e921a837623af962b27d00 07-Oct-2013 Amara Emerson <amara.emerson@arm.com> [ARM] Improve build attributes emission.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192111 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.cpp
dfca6eec3171802d6fcb091da01604ef4420fb3b 25-Sep-2013 Andrew Trick <atrick@apple.com> CriticalAntiDepBreaker is no longer needed for armv7 scheduling.

This is being disabled because it is no longer needed for
performance. It is only used by postRAscheduler which is also planned
for removal, and it is implemented with an out-dated view of register
liveness. It consideres aliases instead of register units, assumes
valid kill flags, and assumes implicit uses on partial register
defs. Kill flags and implicit operands are error prone and impossible
to verify. We should gradually eliminate dependence on them in the
postRA phases.

Targets that still benefit from this should move to the MI
scheduler. If that doesn't solve the problem, then we should add a
hook to regalloc to optimize reload placement.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191348 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.cpp
0f22c134be40a337b30e30bdafb9e8b6880dea1e 23-Sep-2013 Amara Emerson <amara.emerson@arm.com> [ARM] Split A/R class into separate subtarget features.

Patch by Bradley Smith.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191202 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.cpp
5df37dab763ce377095389c4ea1cff88db369954 19-Sep-2013 Amara Emerson <amara.emerson@arm.com> [ARMv8] Add support for the v8 cryptography extensions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190996 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.cpp
2a9af9f18eac90b0de739b6ceddf6c2209086303 13-Sep-2013 Joey Gouly <joey.gouly@arm.com> [ARMv8] Change hasV8Fp to hasFPARMv8, and other command line options
to be more consistent.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190692 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.cpp
195dd8a1ce38970e3463ee1425647280373b60a7 02-Sep-2013 Tilmann Scheller <tilmann.scheller@googlemail.com> ARM: Default to the Swift CPU when targeting armv7s/thumbv7s.

Test cases adjusted accordingly.

This fixes rdar://14871821.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189766 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.cpp
5bed440eb13b4104b64fa9c557954f335aac2aab 02-Sep-2013 Tilmann Scheller <tilmann.scheller@googlemail.com> Revert 189756 for now, it doesn't match what rdar://14871821 really wants.

What we really want is to enable Swift by default for *v7s triples (and there already seems to be some logic which attempts to do that). In that case the iOS version doesn't matter.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189763 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.cpp
024e76b69bc46a20e96eba22f2655d249c495d00 02-Sep-2013 Tilmann Scheller <tilmann.scheller@googlemail.com> ARM: Default to Swift when compiling for iOS 6 or later.

Test cases adjusted accordingly.

This fixes rdar://14871821.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189756 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.cpp
14c41370e36068ae25c871d5bd8f99f92bbb7d45 15-Aug-2013 Renato Golin <renato.golin@linaro.org> make arm-use-movt available for all ARM

Before this patch this flag is IOS specific, but is also
useful for bare project like bootloaders / kernels etc,
since movw / movt prevents simple relocation. Therefore
make this flag more commonly available.

note: this patch depends on a similiar rename in clang

Patch by Jeroen Hofstee.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188487 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.cpp
24adc8f60f0a39e45363eef5392fe1a7e27bd12f 15-Aug-2013 Renato Golin <renato.golin@linaro.org> make arm-reserve-r9 available for all ARM

r9 is defined as a platform-specific register in the ARM EABI.
It can be reserved for a special purpose or be used as a general
purpose register. Add support for reserving r9 for all ARM, while
leaving the IOS usage unchanged.

Patch by Jeroen Hofstee.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188485 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.cpp
fab2daa4a1127ecb217abe2b07c1769122b6fee1 08-Aug-2013 Stephen Hines <srhines@google.com> Merge commit '10251753b6897adcd22cc981c0cc42f348c109de' into merge-20130807

Conflicts:
lib/Archive/ArchiveReader.cpp
lib/Support/Unix/PathV2.inc

Change-Id: I29d8c1e321a4a380b6013f00bac6a8e4b593cc4e
31d2f08f8893f38d2d7293195f3707edfefbeeb6 27-Jun-2013 Joey Gouly <joey.gouly@arm.com> Add a Subtarget feature 'v8fp' to the ARM backend.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185073 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.cpp
849eedce9921eb8f285cd0df0ad69ee5133459d1 26-Jun-2013 Joey Gouly <joey.gouly@arm.com> Add a subtarget feature 'v8' to the ARM backend.
This allows for targeting the ARMv8 AArch32 variant.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184967 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.cpp
1878f9a7874b1ff569d745c0269f49d3daf7203d 12-Jun-2013 Stephen Hines <srhines@google.com> Merge commit '100fbdd06be7590b23c4707a98cd605bdb519498' into merge_20130612
b94a353242b26af5c0969926a6b84664e342b586 23-May-2013 Tim Northover <t.p.northover@gmail.com> ARM: Add Performance Monitor Extensions feature

Performance monitors, including a basic cycle counter, are an official
extension in the ARMv7 specification. This adds support for enabling and
disabling them, orthogonally from CPU selection.

rdar://problem/13939186

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182602 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.cpp
bab06ba696694e7f62f964af7ee5290a13f78340 18-May-2013 JF Bastien <jfb@google.com> Support unaligned load/store on more ARM targets

This patch matches GCC behavior: the code used to only allow unaligned
load/store on ARM for v6+ Darwin, it will now allow unaligned load/store
for v6+ Darwin as well as for v7+ on Linux and NaCl.

The distinction is made because v6 doesn't guarantee support (but LLVM
assumes that Apple controls hardware+kernel and therefore have
conformant v6 CPUs), whereas v7 does provide this guarantee (and
Linux/NaCl behave sanely).

The patch keeps the -arm-strict-align command line option, and adds
-arm-no-strict-align. They behave similarly to GCC's -mstrict-align and
-mnostrict-align.

I originally encountered this discrepancy in FastIsel tests which expect
unaligned load/store generation. Overall this should slightly improve
performance in most cases because of reduced I$ pressure.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182175 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.cpp
40df0d7a462c0febccc93f90dee105a0797f8ac6 16-May-2013 Derek Schuff <dschuff@google.com> Revert "Support unaligned load/store on more ARM targets"

This reverts r181898.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181944 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.cpp
6fc631978cdd1128a790854e497e267639d9325d 15-May-2013 Derek Schuff <dschuff@google.com> Support unaligned load/store on more ARM targets

This patch matches GCC behavior: the code used to only allow unaligned
load/store on ARM for v6+ Darwin, it will now allow unaligned load/store for
v6+ Darwin as well as for v7+ on other targets.

The distinction is made because v6 doesn't guarantee support (but LLVM assumes
that Apple controls hardware+kernel and therefore have conformant v6 CPUs),
whereas v7 does provide this guarantee (and Linux behaves sanely).

Overall this should slightly improve performance in most cases because of
reduced I$ pressure.

Patch by JF Bastien

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181897 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.cpp
38578c4919ea18ceb27e29988b2d857afe6215bf 03-May-2013 Stephen Hines <srhines@google.com> Merge remote-tracking branch 'upstream/master' into merge-20130502

Conflicts:
lib/Support/Unix/Signals.inc
unittests/Transforms/Utils/Cloning.cpp

Change-Id: I027581a4390ec3ce4cd8d33da8b5f4c0c7d372c8
8c9e52a9fc1f99cf80c499ef10e6c8a54ef899d4 10-Apr-2013 Tim Northover <Tim.Northover@arm.com> ARM: Make "SMC" instructions conditional on new TrustZone architecture feature.

These instructions aren't universally available, but depend on a specific
extension to the normal ARM architecture (rather than, say, v6/v7/...) so a new
feature is appropriate.

This also enables the feature by default on A-class cores which usually have
these extensions, to avoid breaking existing code and act as a sensible
default.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179171 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.cpp
3382a840747c42c4a98eac802ee7b347a8ded1e4 21-Mar-2013 Renato Golin <renato.golin@linaro.org> Avoid NEON SP-FP unless unsafe-math or Darwin

NEON is not IEEE 754 compliant, so we should avoid lowering single-precision
floating point operations with NEON unless unsafe-math is turned on. The
equivalent VFP instructions are IEEE 754 compliant, but in some cores they're
much slower, so some archs/OSs might still request it to be on by default,
such as Swift and Darwin.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177651 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.cpp
5adb136be579e8fff3734461580cb34d1d2983b8 06-Mar-2013 Stephen Hines <srhines@google.com> Merge commit 'b3201c5cf1e183d840f7c99ff779d57f1549d8e5' into merge_20130226

Conflicts:
include/llvm/Support/ELF.h
lib/Support/DeltaAlgorithm.cpp

Change-Id: I24a4fbce62eb39d924efee3c687b55e1e17b30cd
901d80065c9afa0ba33e8546c2e1e99a00aceb14 16-Feb-2013 Bill Wendling <isanbard@gmail.com> Reinitialize the ivars in the subtarget so that they can be reset with the new features.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175336 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.cpp
ba6867d0ce3de9b7b4385f98d215edfcd36c4b32 16-Feb-2013 Bill Wendling <isanbard@gmail.com> Temporary revert of 175320.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175322 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.cpp
9be8b4fc92e1ace819a78db512c1f945c1471be7 16-Feb-2013 Bill Wendling <isanbard@gmail.com> Reinitialize the ivars in the subtarget.

When we're recalculating the feature set of the subtarget, we need to have the
ivars in their initial state.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175320 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.cpp
4788d14b484ba9e2fe19855fd6c97a3659980fca 15-Feb-2013 Bill Wendling <isanbard@gmail.com> Support changing the subtarget features in ARM.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175315 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.cpp
0f156af8312a0f3ce88e5c006bf2a52691039ceb 30-Jan-2013 Eli Bendersky <eliben@google.com> Add a special ARM trap encoding for NaCl.
More details in this thread: http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20130128/163783.html

Patch by JF Bastien



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173943 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.cpp
059800f9e3fee2852672f846d91a2da14da7783a 21-Jan-2013 Stephen Hines <srhines@google.com> Merge remote-tracking branch 'upstream/master' into merge-llvm

Conflicts:
lib/CodeGen/AsmPrinter/AsmPrinter.cpp
lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp
lib/MC/MCAssembler.cpp
lib/Support/Atomic.cpp
lib/Support/Memory.cpp
lib/Target/ARM/ARMJITInfo.cpp

Change-Id: Ib339baf88df5b04870c8df1bedcfe1f877ccab8d
0b8c9a80f20772c3793201ab5b251d3520b9cea3 02-Jan-2013 Chandler Carruth <chandlerc@gmail.com> Move all of the header files which are involved in modelling the LLVM IR
into their new header subdirectory: include/llvm/IR. This matches the
directory structure of lib, and begins to correct a long standing point
of file layout clutter in LLVM.

There are still more header files to move here, but I wanted to handle
them in separate commits to make tracking what files make sense at each
layer easier.

The only really questionable files here are the target intrinsic
tablegen files. But that's a battle I'd rather not fight today.

I've updated both CMake and Makefile build systems (I think, and my
tests think, but I may have missed something).

I've also re-sorted the includes throughout the project. I'll be
committing updates to Clang, DragonEgg, and Polly momentarily.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171366 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.cpp
139e407d526193017d42473c8d4892933de78f14 20-Dec-2012 Evan Cheng <evan.cheng@apple.com> On some ARM cpus, flags setting movs with shifter operand, i.e. lsl, lsr, asr,
are more expensive than the non-flag setting variant. Teach thumb2 size
reduction pass to avoid generating them unless we are optimizing for size.

rdar://12892707


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170728 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.cpp
d04a8d4b33ff316ca4cf961e06c9e312eff8e64f 03-Dec-2012 Chandler Carruth <chandlerc@gmail.com> Use the new script to sort the includes of every file under lib.

Sooooo many of these had incorrect or strange main module includes.
I have manually inspected all of these, and fixed the main module
include to be the nearest plausible thing I could find. If you own or
care about any of these source files, I encourage you to take some time
and check that these edits were sensible. I can't have broken anything
(I strictly added headers, and reordered them, never removed), but they
may not be the headers you'd really like to identify as containing the
API being implemented.

Many forward declarations and missing includes were added to a header
files to allow them to parse cleanly when included first. The main
module rule does in fact have its merits. =]

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169131 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.cpp
eb1641d54a7eda7717304bc4d55d059208d8ebed 29-Sep-2012 Bob Wilson <bob.wilson@apple.com> Add LLVM support for Swift.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164899 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.cpp
e127dfd0b175b5a336e61fecaad7fc2aec65d95c 18-Sep-2012 Andrew Trick <atrick@apple.com> TableGen subtarget emitter. Initialize MCSubtargetInfo with the new machine model.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164092 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.cpp
e1b53287179b4b9b5c3c549586f688d3fa2ae8ef 18-Sep-2012 Andrew Trick <atrick@apple.com> Revert r164061-r164067. Most of the new subtarget emitter.

I have to work out the Target/CodeGen header dependencies
before putting this back.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164072 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.cpp
db7afac4575168c239ac9c570cb7897808f12e30 18-Sep-2012 Andrew Trick <atrick@apple.com> TableGen subtarget emitter. Initialize MCSubtargetInfo with the new machine model.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164061 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.cpp
31675153bd2d7617db8cb6aeb58054934c7b9f73 24-Aug-2012 Stephen Hines <srhines@google.com> Merge branch 'upstream' into merge_2

Conflicts:
lib/Target/ARM/ARMCodeEmitter.cpp

Change-Id: I6702d340c733e9721499b5d85b13b96ad9c14eb5
d43b5c97cff06d7840b974ca84fa0639d2567968 08-Aug-2012 Andrew Trick <atrick@apple.com> Added MispredictPenalty to SchedMachineModel.

This replaces an existing subtarget hook on ARM and allows standard
CodeGen passes to potentially use the property.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161471 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.cpp
7744acd1ab73b3eec6f1449f47083abe3fb1b527 03-Aug-2012 Shih-wei Liao <sliao@google.com> Merge with LLVM upstream r160668 (Jul 24th 2012)

Conflicts:
include/llvm/Support/ELF.h
lib/CodeGen/AsmPrinter/AsmPrinter.cpp
lib/Support/Memory.cpp
lib/Transforms/Instrumentation/AddressSanitizer.cpp

Change-Id: Iddd658cf2eadc7165b2805b446d31af2c5c9917f
f94f051cf5bb2ffbe08f42d1ad6646c900ed6aaa 05-Jun-2012 Andrew Trick <atrick@apple.com> ARM itinerary properties.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157980 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.cpp
fc992996f751e0941951b6d08d8f1e80ebec1385 05-Jun-2012 Andrew Trick <atrick@apple.com> misched: Added MultiIssueItineraries.

This allows a subtarget to explicitly specify the issue width and
other properties without providing pipeline stage details for every
instruction.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157979 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.cpp
afb3b5ebe61b480527de86311d2a0770fc857d38 27-Apr-2012 Evan Cheng <evan.cheng@apple.com> Implement a bastardized ABI.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155686 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.cpp
e67a4163f5d2ad8e42a3aa0ccdaa27d85f6d5be4 26-Apr-2012 Evan Cheng <evan.cheng@apple.com> If triple is armv7 / thumbv7 and a CPU is specified, do not automatically assume
the feature set of v7a. This comes about if the user specifies something like
-arch armv7 -mcpu=cortex-m3. We shouldn't be generating instructions such as
uxtab in this case.

rdar://11318438


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155601 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.cpp
cf5a1461acaace0f3e7d11fbbcfbf635b8c8ea9d 24-Apr-2012 Shih-wei Liao <sliao@google.com> Merge with LLVM upstream r155090.

Conflicts:
lib/Support/Unix/PathV2.inc

Change-Id: I7b89833849f6cbcfa958a33a971d0f7754c9cb2c
bfae1fd1fce97e73299e8ad67a22ae18de5112e9 22-Apr-2012 Benjamin Kramer <benny.kra@googlemail.com> ARM: Initialize the HasRAS bit.

Found by valgrind.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155313 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.cpp
e15660acc226291da49379051c0bf0a02262deb6 15-Apr-2012 Shih-wei Liao <sliao@google.com> Non-static arm-reserve-r9.

Change-Id: I96d9a7cb594d89e0377616ad613f8201e9aa8136
/external/llvm/lib/Target/ARM/ARMSubtarget.cpp
bee78fe5fcd8464f58bc729dede1a87d763ac3ae 11-Apr-2012 Evan Cheng <evan.cheng@apple.com> Clean up ARM fused multiply + add/sub support some more: rename some isel
predicates.
Also remove NEON2 since it's not really useful and it is confusing. If
NEON + VFP4 implies NEON2 but NEON2 doesn't imply NEON + VFP4, what does it
really mean?

rdar://10139676


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154480 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.cpp
4e02f23de24375294005f88b5254a3775d39fcb2 27-Mar-2012 Craig Topper <craig.topper@gmail.com> Prune some includes

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153502 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.cpp
74bebde7c4e2d1cfd4a16c19ce3c87521df67639 05-Mar-2012 Sebastian Pop <spop@codeaurora.org> updated patch for the ARM fused multiply add/sub

In this update:
- I assumed neon2 does not imply vfpv4, but neon and vfpv4 imply neon2.
- I kept setting .fpu=neon-vfpv4 code attribute because that is what the
assembler understands.

Patch by Ana Pazos <apazos@codeaurora.org>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152036 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.cpp
07043279f60622243d16d8a3f60805960482083c 21-Feb-2012 Evan Cheng <evan.cheng@apple.com> Proper support for a bastardized darwin-eabi hybird ABI.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151083 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.cpp
31d157ae1ac2cd9c787dc3c1d28e64c682803844 18-Feb-2012 Jia Liu <proljc@gmail.com> Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150878 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.cpp
4b4e62219be91839091f9e35d8accf877f925d81 22-Jan-2012 Anton Korobeynikov <asl@math.spbu.ru> Add fused multiple+add instructions from VFPv4.
Patch by Ana Pazos!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148658 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.cpp
afff941211526a31f931aa9fcac84ae42ff60ef0 20-Dec-2011 Evan Cheng <evan.cheng@apple.com> ARM target code clean up. Check for iOS, not Darwin where it makes sense.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146981 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.cpp
928698b14e4bcd0f231dc28e246920a242d81fc1 18-Oct-2011 David Meyer <pdox@google.com> Remove NaClMode

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142338 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.cpp
6d2f9cec715c50bca44816d9bdea97f8b63bf2a0 07-Oct-2011 Bob Wilson <bob.wilson@apple.com> Reenable tail calls for iOS 5.0 and later.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141370 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.cpp
acad68da50581de905a994ed3c6b9c197bcea687 28-Sep-2011 James Molloy <james.molloy@arm.com> Check in a patch that has already been code reviewed by Owen that I'd forgotten to commit.

Build on previous patches to successfully distinguish between an M-series and A/R-series MSR and MRS instruction. These take different mask names and have a *slightly* different opcode format.

Add decoder and disassembler tests.

Improvement on the previous patch - successfully distinguish between valid v6m and v7m masks (one is a subset of the other). The patch had to be edited slightly to apply to ToT.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140696 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.cpp
1fac6b50ea720d75fc2bf01a288e99f239869e90 05-Sep-2011 Nick Lewycky <nicholas@mxc.ca> Add a new MC bit for NaCl (Native Client) mode. NaCl requires that certain
instructions are more aligned than the CPU requires, and adds some additional
directives, to follow in future patches. Patch by David Meyer!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139125 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.cpp
c60f9b752381baa6c4b80c0739034660f1748c84 14-Jul-2011 Evan Cheng <evan.cheng@apple.com> Next round of MC refactoring. This patch factor MC table instantiations, MC
registeration and creation code into XXXMCDesc libraries.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135184 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.cpp
ebdeeab812beec0385b445f3d4c41a114e0d972f 08-Jul-2011 Evan Cheng <evan.cheng@apple.com> Eliminate asm parser's dependency on TargetMachine:
- Each target asm parser now creates its own MCSubtatgetInfo (if needed).
- Changed AssemblerPredicate to take subtarget features which tablegen uses
to generate asm matcher subtarget feature queries. e.g.
"ModeThumb,FeatureThumb2" is translated to
"(Bits & ModeThumb) != 0 && (Bits & FeatureThumb2) != 0".


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134678 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.cpp
963b03c1a9f6a9742671459f103ee9a566c6de58 07-Jul-2011 Evan Cheng <evan.cheng@apple.com> Rename attribute 'thumb' to a more descriptive 'thumb-mode'.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134626 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.cpp
db068738e806753bc5735434cab9b9f930840c7a 07-Jul-2011 Evan Cheng <evan.cheng@apple.com> Sink feature IsThumb into MC layer.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134608 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.cpp
0ddff1b5359433faf2eb1c4ff5320ddcbd42f52f 07-Jul-2011 Evan Cheng <evan.cheng@apple.com> Compute feature bits at time of MCSubtargetInfo initialization.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134606 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.cpp
39dfb0ff848be6b380ca81ff95d4ca4e0ae09c76 07-Jul-2011 Evan Cheng <evan.cheng@apple.com> Change some ARM subtarget features to be single bit yes/no in order to sink them down to MC layer. Also fix tests.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134590 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.cpp
94ca42ff0407d71bacc41de4032d8dbe6358d33d 07-Jul-2011 Evan Cheng <evan.cheng@apple.com> Factor ARM triple parsing out of ARMSubtarget. Another step towards making ARM subtarget info available to MC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134569 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.cpp
385e930d55f3ecd3c9538823dfa5896a12461845 02-Jul-2011 Evan Cheng <evan.cheng@apple.com> Rename XXXGenSubtarget.inc to XXXGenSubtargetInfo.inc for consistency.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134281 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.cpp
a7603982dbf9e240ecc7ed6eddcd1cdb868107ac 01-Jul-2011 Jim Grosbach <grosbach@apple.com> ARMv7M vs. ARMv7E-M support.

The DSP instructions in the Thumb2 instruction set are an optional extension
in the Cortex-M* archtitecture. When present, the implementation is considered
an "ARMv7E-M implementation," and when not, an "ARMv7-M implementation."

Add a subtarget feature hook for the v7e-m instructions and hook it up. The
cortex-m3 cpu is an example of a v7m implementation, while the cortex-m4 is
a v7e-m implementation.

rdar://9572992



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134261 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.cpp
5b1b4489cf3a0f56f8be0673fc5cc380a32d277b 01-Jul-2011 Evan Cheng <evan.cheng@apple.com> Rename TargetSubtarget to TargetSubtargetInfo for consistency.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134259 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.cpp
94214703d97d8d9dfca88174ffc7e94820a85e62 01-Jul-2011 Evan Cheng <evan.cheng@apple.com> - Added MCSubtargetInfo to capture subtarget features and scheduling
itineraries.
- Refactor TargetSubtarget to be based on MCSubtargetInfo.
- Change tablegen generated subtarget info to initialize MCSubtargetInfo
and hide more details from targets.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134257 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.cpp
4cc446bc400b2ff58af81c91f5e145b81d6beb26 30-Jun-2011 Evan Cheng <evan.cheng@apple.com> Fix ARMSubtarget feature parsing.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134129 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.cpp
276365dd4bc0c2160f91fd8062ae1fc90c86c324 30-Jun-2011 Evan Cheng <evan.cheng@apple.com> Fix the ridiculous SubtargetFeatures API where it implicitly expects CPU name to
be the first encoded as the first feature. It then uses the CPU name to look up
features / scheduling itineray even though clients know full well the CPU name
being used to query these properties.

The fix is to just have the clients explictly pass the CPU name!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134127 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.cpp
df214fa51715896d0cd5a407e8e4c57454619fc2 23-Jun-2011 Evan Cheng <evan.cheng@apple.com> Remove TargetOptions.h dependency from ARMSubtarget.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133738 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.cpp
0b65599015f0b51304d941ba4a14aaf0d1734341 20-May-2011 Evan Cheng <evan.cheng@apple.com> Revert accidental commit.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131739 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.cpp
2e6496026f41d2c05ff038d14df9972f8a27fb94 20-May-2011 Evan Cheng <evan.cheng@apple.com> Revert r131664 and fix it in instcombine instead. rdar://9467055

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131708 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.cpp
5dde893c2bac9e1569c38429f756c1d723e8edf2 19-Apr-2011 Bob Wilson <bob.wilson@apple.com> Avoid some 's' 16-bit instruction which partially update CPSR
(and add false dependency) when it isn't dependent on last CPSR defining
instruction. rdar://8928208

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129773 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.cpp
0e3ee43ea058a35ab5ce69cceafd316d49eaad34 01-Apr-2011 Benjamin Kramer <benny.kra@googlemail.com> Initialize HasVMLxForwarding.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128709 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.cpp
af05c69ba024b1838ae6f1071d6fd0f9fe33999f 22-Feb-2011 Evan Cheng <evan.cheng@apple.com> available_externally (hidden or not) GVs are always accessed via stubs. rdar://9027648.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126191 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.cpp
53519f015e3e84e9f57b677cc8724805a6009b73 21-Jan-2011 Evan Cheng <evan.cheng@apple.com> Last round of fixes for movw + movt global address codegen.
1. Fixed ARM pc adjustment.
2. Fixed dynamic-no-pic codegen
3. CSE of pc-relative load of global addresses.

It's now enabled by default for Darwin.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123991 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.cpp
fc8475bde993cc0fa6101427e73e8a9cf7d1c3a4 19-Jan-2011 Evan Cheng <evan.cheng@apple.com> Don't forget to emit the load from indirect symbol when using movw + movt to materialize GA indirect symbols.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123809 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.cpp
5de5d4b6d0eb3fd379fa571d82f6fa764460b3b8 17-Jan-2011 Evan Cheng <evan.cheng@apple.com> Materialize GA addresses with movw + movt pairs for Darwin in PIC mode. e.g.
movw r0, :lower16:(L_foo$non_lazy_ptr-(LPC0_0+4))
movt r0, :upper16:(L_foo$non_lazy_ptr-(LPC0_0+4))
LPC0_0:
add r0, pc, r0

It's not yet enabled by default as some tests are failing. I suspect bugs in
down stream tools.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123619 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.cpp
b72d2a92b75daa9cbac7338aff0cd8ae04c2b4bd 11-Jan-2011 Evan Cheng <evan.cheng@apple.com> Clean up ARM subtarget code by using Triple ADT.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123276 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.cpp
6018deefe823598a3bbe03de9af354d269ae2130 04-Jan-2011 Andrew Trick <atrick@apple.com> Fix the ARM IIC_iCMPsi itinerary and add an important assert.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122794 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.cpp
2da8bc8a5f7705ac131184cd247f48500da0d74e 24-Dec-2010 Andrew Trick <atrick@apple.com> Various bits of framework needed for precise machine-level selection
DAG scheduling during isel. Most new functionality is currently
guarded by -enable-sched-cycles and -enable-sched-hazard.

Added InstrItineraryData::IssueWidth field, currently derived from
ARM itineraries, but could be initialized differently on other targets.

Added ScheduleHazardRecognizer::MaxLookAhead to indicate whether it is
active, and if so how many cycles of state it holds.

Added SchedulingPriorityQueue::HasReadyFilter to allowing gating entry
into the scheduler's available queue.

ScoreboardHazardRecognizer now accesses the ScheduleDAG in order to
get information about it's SUnits, provides RecedeCycle for bottom-up
scheduling, correctly computes scoreboard depth, tracks IssueCount, and
considers potential stall cycles when checking for hazards.

ScheduleDAGRRList now models machine cycles and hazards (under
flags). It tracks MinAvailableCycle, drives the hazard recognizer and
priority queue's ready filter, manages a new PendingQueue, properly
accounts for stall cycles, etc.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122541 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.cpp
6e8f4c404825b79f9b9176483653f1aa927dfbde 24-Dec-2010 Andrew Trick <atrick@apple.com> whitespace


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122539 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.cpp
48575f6ea7d5cd21ab29ca370f58fcf9ca31400b 05-Dec-2010 Evan Cheng <evan.cheng@apple.com> Making use of VFP / NEON floating point multiply-accumulate / subtraction is
difficult on current ARM implementations for a few reasons.
1. Even though a single vmla has latency that is one cycle shorter than a pair
of vmul + vadd, a RAW hazard during the first (4? on Cortex-a8) can cause
additional pipeline stall. So it's frequently better to single codegen
vmul + vadd.
2. A vmla folowed by a vmul, vmadd, or vsub causes the second fp instruction to
stall for 4 cycles. We need to schedule them apart.
3. A vmla followed vmla is a special case. Obvious issuing back to back RAW
vmla + vmla is very bad. But this isn't ideal either:
vmul
vadd
vmla
Instead, we want to expand the second vmla:
vmla
vmul
vadd
Even with the 4 cycle vmul stall, the second sequence is still 2 cycles
faster.

Up to now, isel simply avoid codegen'ing fp vmla / vmls. This works well enough
but it isn't the optimial solution. This patch attempts to make it possible to
use vmla / vmls in cases where it is profitable.

A. Add missing isel predicates which cause vmla to be codegen'ed.
B. Make sure the fmul in (fadd (fmul)) has a single use. We don't want to
compute a fmul and a fmla.
C. Add additional isel checks for vmla, avoid cases where vmla is feeding into
fp instructions (except for the #3 exceptional case).
D. Add ARM hazard recognizer to model the vmla / vmls hazards.
E. Add a special pre-regalloc case to expand vmla / vmls when it's likely the
vmla / vmls will trigger one of the special hazards.

Work in progress, only A+B are enabled.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120960 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.cpp
66f6c79450a93d979128d8702c83841c8f715dc8 09-Nov-2010 Bob Wilson <bob.wilson@apple.com> Define the subtarget feature for the architecture version,
as derived from the target triple. This is important for enabling
features that are implied based on the architecture version.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118643 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.cpp
dfed19fe2c34c1209108afa58e8ab014ffd894e2 03-Nov-2010 Evan Cheng <evan.cheng@apple.com> Fix preload instruction isel. Only v7 supports pli, and only v7 with mp extension supports pldw. Add subtarget attribute to denote mp extension support and legalize illegal ones to nothing.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118160 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.cpp
77f42b52781b6923924a93b8ab338d183887a592 12-Oct-2010 Bob Wilson <bob.wilson@apple.com> PR8359: The ARM backend may end up allocating registers D16 to D31 when
"-mattr=+vfp3" is specified. However, this will not work for hardware that
only supports 16 registers. Add a new flag to support -"mattr=+vfp3,+d16".
Patch by Jan Voung!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116310 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.cpp
654d5440a477b1f6c89b051107e041a331f78e27 28-Sep-2010 Owen Anderson <resistor@mac.com> Add a subtarget hook for reporting the misprediction penalty. Use this to provide more precise
cost modeling for if-conversion. Now if only we had a way to estimate the misprediction probability.

Adjsut CodeGen/ARM/ifcvt10.ll. The pipeline on Cortex-A8 is long enough that it is still profitable
to predicate an ldm, but the shorter pipeline on Cortex-A9 makes it unprofitable.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114995 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.cpp
02aba73a9ec04d0de9424422249af3948ca9573a 28-Sep-2010 Bob Wilson <bob.wilson@apple.com> Add a command line option "-arm-strict-align" to disallow unaligned memory
accesses for ARM targets that would otherwise allow it. Radar 8465431.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114941 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.cpp
3ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1 10-Sep-2010 Evan Cheng <evan.cheng@apple.com> Teach if-converter to be more careful with predicating instructions that would
take multiple cycles to decode.
For the current if-converter clients (actually only ARM), the instructions that
are predicated on false are not nops. They would still take machine cycles to
decode. Micro-coded instructions such as LDM / STM can potentially take multiple
cycles to decode. If-converter should take treat them as non-micro-coded
simple instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113570 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.cpp
fcba5e6b645df89ae6b93911fe0f80b08fa6b44c 11-Aug-2010 Jim Grosbach <grosbach@apple.com> cortex m4 has floating point support, but only single precision.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110810 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.cpp
7b4d31176efe6894bcfaa05257dd5783acda5ddc 11-Aug-2010 Evan Cheng <evan.cheng@apple.com> Report error if codegen tries to instantiate a ARM target when the cpu does support it. e.g. cortex-m* processors.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110798 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.cpp
11db068721d44fd5f9b0c2a3a4c90f813d2eae9c 11-Aug-2010 Evan Cheng <evan.cheng@apple.com> - Add subtarget feature -mattr=+db which determine whether an ARM cpu has the
memory and synchronization barrier dmb and dsb instructions.
- Change instruction names to something more sensible (matching name of actual
instructions).
- Added tests for memory barrier codegen.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110785 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.cpp
9de1ac267e197d40cec7a14041f2bf69498536c9 09-Aug-2010 Evan Cheng <evan.cheng@apple.com> Explicitly initialize SlowFPBrcc and Pref32BitThumb to false.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110587 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.cpp
29402132f3e890a2771818f44987ede213297431 06-May-2010 Jim Grosbach <grosbach@apple.com> Cleanup of ARMv7M support. Move hardware divide and Thumb2 extract/pack
instructions to subtarget features and update tests to reflect.
PR5717.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103136 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.cpp
b1dc393bd56365ad8fabb51f22c2f3ace707c39a 05-May-2010 Jim Grosbach <grosbach@apple.com> Add initial support for ARMv7M subtarget and cortex-m3 cpu. Patch by
Jordy <snhjordy@gmail.com>.

Followup patches will add some tests and adjust to use Subtarget features
for the instructions.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103119 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.cpp
46510a73e977273ec67747eb34cbdb43f815e451 15-Apr-2010 Dan Gohman <gohman@apple.com> Add const qualifiers to CodeGen's use of LLVM IR constructs.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101334 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.cpp
7ec7a0e96b34fedf11445c1dde27a4fac8e8a1a7 26-Mar-2010 Jim Grosbach <grosbach@apple.com> switch the flag for using NEON for SP floating point to a subtarget 'feature'.

Re-commit. This time complete with testsuite updates.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99570 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.cpp
78e496e165e3093f3d7373e50da1c91b9937bc69 26-Mar-2010 Jim Grosbach <grosbach@apple.com> need to fix 'make check' tests first. revert for a moment.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99569 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.cpp
bd17bc96bf54cc58d91c2d20964c6c5e28bffa57 26-Mar-2010 Jim Grosbach <grosbach@apple.com> switch the flag for using NEON for SP floating point to a subtarget 'feature'

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99568 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.cpp
6b2e8dc9a0e4ebda645ee4eba95711eb630b4edf 26-Mar-2010 Jim Grosbach <grosbach@apple.com> switch the use-vml[as] instructions flag to a subtarget 'feature'

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99565 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.cpp
65cef00142c9a187707c56a293ae794765f7463b 25-Mar-2010 Jim Grosbach <grosbach@apple.com> ARM cortex-a8 doesn't do vmla/vmls well. disable them by default for that cpu

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99549 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.cpp
2676737e5ed3e4b5c89b4d06b60d998e9318eb73 24-Mar-2010 Jim Grosbach <grosbach@apple.com> Make the use of the vmla and vmls VFP instructions controllable via cmd line.
Preliminary testing shows significant performance wins by not using these
instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99436 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.cpp
631379e79c0971c5bac13629b8caf8912ed4c35c 14-Mar-2010 Anton Korobeynikov <asl@math.spbu.ru> Add substarget feature for FP16

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98503 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.cpp
ce7bf1c55f5238870bae2909cd368151f1d813d1 06-Mar-2010 Anton Korobeynikov <asl@math.spbu.ru> Initial bits of ARMv4-only support.
Patch by John Tytgat!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97886 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.cpp
f0356fe140af1a30587b9a86bcfb1b2c51b8ce20 27-Jan-2010 Jeffrey Yasskin <jyasskin@google.com> Kill ModuleProvider and ghost linkage by inverting the relationship between
Modules and ModuleProviders. Because the "ModuleProvider" simply materializes
GlobalValues now, and doesn't provide modules, it's renamed to
"GVMaterializer". Code that used to need a ModuleProvider to materialize
Functions can now materialize the Functions directly. Functions no longer use a
magic linkage to record that they're materializable; they simply ask the
GVMaterializer.

Because the C ABI must never change, we can't remove LLVMModuleProviderRef or
the functions that refer to it. Instead, because Module now exposes the same
functionality ModuleProvider used to, we store a Module* in any
LLVMModuleProviderRef and translate in the wrapper methods. The bindings to
other languages still use the ModuleProvider concept. It would probably be
worth some time to update them to follow the C++ more closely, but I don't
intend to do it.

Fixes http://llvm.org/PR5737 and http://llvm.org/PR5735.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94686 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.cpp
15217e63bce6c161b355b63d6496c7c327d15817 30-Nov-2009 Bob Wilson <bob.wilson@apple.com> Remove isProfitableToDuplicateIndirectBranch target hook. It is profitable
for all the processors where I have tried it, and even when it might not help
performance, the cost is quite low. The opportunities for duplicating
indirect branches are limited by other factors so code size does not change
much due to tail duplicating indirect branches aggressively.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90144 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.cpp
5cdc3a949af0cef7f2163f8a7acbf3049c226321 24-Nov-2009 Anton Korobeynikov <asl@math.spbu.ru> Materialize global addresses via movt/movw pair, this is always better
than doing the same via constpool:
1. Load from constpool costs 3 cycles on A9, movt/movw pair - just 2.
2. Load from constpool might stall up to 300 cycles due to cache miss.
3. Movt/movw does not use load/store unit.
4. Less constpool entries => better compiler performance.

This is only enabled on ELF systems, since darwin does not have needed
relocations (yet).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89720 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.cpp
834b08af8d3d8fc6c76ac6ca40674565689e8d7f 18-Nov-2009 Bob Wilson <bob.wilson@apple.com> Add a target hook to allow changing the tail duplication limit based on the
contents of the block to be duplicated. Use this for ARM Cortex A8/9 to
be more aggressive tail duplicating indirect branches, since it makes it
much more likely that they will be predicted in the branch target buffer.
Testcase coming soon.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89187 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.cpp
87d21b92fc42f6b3bd8567a83fc5b5191c1205e5 13-Nov-2009 David Goodwin <david_goodwin@apple.com> Allow target to specify regclass for which antideps will only be broken along the critical path.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@88682 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.cpp
c2e8a7e8d2ab156afaa8ab0d0317dd9ee3db7d30 10-Nov-2009 David Goodwin <david_goodwin@apple.com> Fixed to address code review. No functional changes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86634 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.cpp
b46aea10324263dd63492fc5c1d54800e980c8f8 16-Oct-2009 Evan Cheng <evan.cheng@apple.com> I am no spelling bee.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84250 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.cpp
d3dd50fec00fbbb76edbfaff4d613f1248d21c9e 16-Oct-2009 Evan Cheng <evan.cheng@apple.com> Enable post-alloc scheduling for all ARM variants except for Thumb1.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84249 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.cpp
fee0c1074c68a61d15899fb8cb31f1902fa9e509 16-Oct-2009 Evan Cheng <evan.cheng@apple.com> Add comment.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84246 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.cpp
9843a93e830e76f96e9a997b3002624a28ca5aa6 02-Oct-2009 David Goodwin <david_goodwin@apple.com> Remove neonfp attribute and instead set default based on CPU string. Add -arm-use-neon-fp to override the default.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83218 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.cpp
471850ab84301dd47cab2bf8d694fcb5766c1169 01-Oct-2009 David Goodwin <david_goodwin@apple.com> Restore the -post-RA-scheduler flag as an override for the target specification. Remove -mattr for setting PostRAScheduler enable and instead use CPU string.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83215 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.cpp
0dad89fa94536284d51f60868326294b725a0c61 30-Sep-2009 David Goodwin <david_goodwin@apple.com> Remove -post-RA-schedule flag and add a TargetSubtarget method to enable post-register-allocation scheduling. By default it is off. For ARM, enable/disable with -mattr=+/-postrasched. Enable by default for cortex-a8.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83122 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.cpp
63476a80404125e5196b6c09113c1d4796da0604 03-Sep-2009 Evan Cheng <evan.cheng@apple.com> Reference to hidden symbols do not have to go through non-lazy pointer in non-pic mode. rdar://7187172.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80904 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.cpp
e4e4ed3b56f63e9343e01bf0b2ecd7c1f45d296c 29-Aug-2009 Evan Cheng <evan.cheng@apple.com> Let Darwin linker auto-synthesize stubs and lazy-pointers. This deletes a bunch of nasty code in ARM asm printer.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80404 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.cpp
e22f4da01d57f51757663fdcae986af0aeca49fe 05-Aug-2009 Daniel Dunbar <daniel@zuster.org> Remove some dead code.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78219 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.cpp
42a83f2d15cbbc08f5be19856198e3c885221e9c 04-Aug-2009 David Goodwin <david_goodwin@apple.com> Initial support for single-precision FP using NEON. Added "neonfp" attribute to enable. Added patterns for some binary FP operations.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78081 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.cpp
3be03406c9c3b2075d5ae416499af2f15f703d6f 03-Aug-2009 Daniel Dunbar <daniel@zuster.org> Normalize Subtarget constructors to take a target triple string instead of
Module*.

Also, dropped uses of TargetMachine where unnecessary. The only target which
still takes a TargetMachine& is Mips, I would appreciate it if someone would
normalize this to match other targets.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77918 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.cpp
b620724e614c6594e7b269b6ea7d8483947ea944 01-Aug-2009 Evan Cheng <evan.cheng@apple.com> Fix Thumb2 function call isel. Thumb1 and Thumb2 should share the same
instructions for calls since BL and BLX are always 32-bit long and BX is always
16-bit long.

Also, we should be using BLX to call external function stubs.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77756 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.cpp
9170ab6685fcd820c6274e761b8c3a71f25ae074 22-Jun-2009 Bob Wilson <bob.wilson@apple.com> Use thumb2 for ARM architectures V6T2 and later. Fix a bug in checking
for "thumb" and add a check for V6T2.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73905 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.cpp
54fc124d72512d65d62565cabcd85c7b07496513 22-Jun-2009 Bob Wilson <bob.wilson@apple.com> For Darwin on ARMv6 and newer, make register r9 available for use as a
caller-saved register.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73901 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.cpp
cd828618b8c6ec58df94aec0f5546f009f2fd0d5 19-Jun-2009 Evan Cheng <evan.cheng@apple.com> Remove UseThumbBacktraces. Just check if subtarget is darwin.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73734 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.cpp
0eebf653a7b2978e7761f8d068b6fbec22aea0f6 09-Jun-2009 Anton Korobeynikov <asl@math.spbu.ru> The attached patches implement most of the ARM AAPCS-VFP hard float
ABI. The missing piece is support for putting "homogeneous aggregates"
into registers.

Patch by Sandeep Patel!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73095 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.cpp
70459bef9ccd73b3a2a44fdd62f2509861112745 01-Jun-2009 Anton Korobeynikov <asl@math.spbu.ru> Implement review feedback. Make thumb2 'normal' subtarget feature

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72698 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.cpp
d4022c3fbb0705abdc8eddc3ee4a5059f5ef8094 30-May-2009 Anton Korobeynikov <asl@math.spbu.ru> Add placeholder for thumb2 stuff

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72593 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.cpp
6d7d2aa38a247426e2ccf53e3c6ad0315c9a4d8c 23-May-2009 Anton Korobeynikov <asl@math.spbu.ru> Add ARMv7 architecture, Cortex processors and different FPU modes handling.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72337 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.cpp
41a024385f1220eadc48b48cb4c044a5fbc1b361 23-May-2009 Anton Korobeynikov <asl@math.spbu.ru> Propagate CPU string out of SubtargetFeatures

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72335 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.cpp
8c6b991635ff589fbe4b8db013bcc1d2ef57a0e0 09-Mar-2009 Evan Cheng <evan.cheng@apple.com> ARM target now also recognize triplets like thumbv6-apple-darwin and set thumb mode and arch subversion. Eventually thumb triplets will go way and replaced with function notes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66435 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.cpp
4b1747430a2d67702958b95d6776396734f184a0 08-Mar-2009 Evan Cheng <evan.cheng@apple.com> Recognize triplets starting with armv5-, armv6- etc. And set the ARM arch version accordingly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66365 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.cpp
4ee451de366474b9c228b4e5fa573795a715216d 29-Dec-2007 Chris Lattner <sabre@nondot.org> Remove attribution from file headers, per discussion on llvmdev.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45418 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.cpp
04321f70f5075673934d5b1ed3353dd15d911183 23-Feb-2007 Evan Cheng <evan.cheng@apple.com> Added -march=thumb; removed -enable-thumb.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34521 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.cpp
3630e78db9268dbe81a9369a33e49b857804f2ec 13-Feb-2007 Lauro Ramos Venancio <lauro.venancio@gmail.com> Add ABI information to ARM subtarget.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34245 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.cpp
1a3771e30e48b9cc21ccdc79fc9cf37ec4104b17 19-Jan-2007 Evan Cheng <evan.cheng@apple.com> Introduce TargetType's ELF and Darwin.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33363 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.cpp
a8e2989ece6dc46df59b0768184028257f913843 19-Jan-2007 Evan Cheng <evan.cheng@apple.com> ARM backend contribution from Apple.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33353 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.cpp