2c3e0051c31c3f5b2328b447eadf1cf9c4427442 |
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06-May-2015 |
Pirama Arumuga Nainar <pirama@google.com> |
Update aosp/master LLVM for rebase to r235153 Change-Id: I9bf53792f9fc30570e81a8d80d296c681d005ea7 (cherry picked from commit 0c7f116bb6950ef819323d855415b2f2b0aad987)
/external/llvm/lib/Target/ARM/ARMSubtarget.h
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4c5e43da7792f75567b693105cc53e3f1992ad98 |
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08-Apr-2015 |
Pirama Arumuga Nainar <pirama@google.com> |
Update aosp/master llvm for rebase to r233350 Change-Id: I07d935f8793ee8ec6b7da003f6483046594bca49
/external/llvm/lib/Target/ARM/ARMSubtarget.h
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ebe69fe11e48d322045d5949c83283927a0d790b |
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23-Mar-2015 |
Stephen Hines <srhines@google.com> |
Update aosp/master LLVM for rebase to r230699. Change-Id: I2b5be30509658cb8266be782de0ab24f9099f9b9
/external/llvm/lib/Target/ARM/ARMSubtarget.h
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37ed9c199ca639565f6ce88105f9e39e898d82d0 |
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01-Dec-2014 |
Stephen Hines <srhines@google.com> |
Update aosp/master LLVM for rebase to r222494. Change-Id: Ic787f5e0124df789bd26f3f24680f45e678eef2d
/external/llvm/lib/Target/ARM/ARMSubtarget.h
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c6a4f5e819217e1e12c458aed8e7b122e23a3a58 |
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21-Jul-2014 |
Stephen Hines <srhines@google.com> |
Update LLVM for rebase to r212749. Includes a cherry-pick of: r212948 - fixes a small issue with atomic calls Change-Id: Ib97bd980b59f18142a69506400911a6009d9df18
/external/llvm/lib/Target/ARM/ARMSubtarget.h
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dce4a407a24b04eebc6a376f8e62b41aaa7b071f |
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29-May-2014 |
Stephen Hines <srhines@google.com> |
Update LLVM for 3.5 rebase (r209712). Change-Id: I149556c940fb7dc92d075273c87ff584f400941f
/external/llvm/lib/Target/ARM/ARMSubtarget.h
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36b56886974eae4f9c5ebc96befd3e7bfe5de338 |
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24-Apr-2014 |
Stephen Hines <srhines@google.com> |
Update to LLVM 3.5a. Change-Id: Ifadecab779f128e62e430c2b4f6ddd84953ed617
/external/llvm/lib/Target/ARM/ARMSubtarget.h
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373aa5c665fe6df6b9c5586d397dc3617f25aab5 |
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07-Feb-2014 |
Stephen Hines <srhines@google.com> |
Update LLVM for merge to 3.4. Update config.h files. Add RS SubtargetFeature for +long64 on ARM devices. Adjust Android.mk for added/removed files: + Delinearization.cpp - PathNumbering.cpp - PathProfileInfo.cpp - PathProfileVerifier.cpp - ProfileDataLoader.cpp - ProfileDataLoaderPass.cpp - ProfileEstimatorPass.cpp - ProfileInfo.cpp - ProfileInfoLoader.cpp - ProfileInfoLoaderPass.cpp - ProfileVerifierPass.cpp + LiveRegUnits.cpp - ShrinkWrapping.cpp + StackMaps.cpp - StrongPHIElimination.cpp + DIEHash.cpp + LegacyPassManager.cpp + ELF.cpp + Unicode.cpp - MipsOptimizeMathLibCalls.cpp - MipsELFStreamer.cpp + MipsTargetStreamer.cpp - EdgeProfiling.cpp + DataFlowSanitizer.cpp + DebugIR.cpp - OptimalEdgeProfiling.cpp - PathProfiling.cpp - ProfilingUtils.cpp - BasicBlockPlacement.cpp + LoopRerollPass.cpp + PartiallyInlineLibCalls.cpp + SampleProfile.cpp + GlobalStatus.cpp Change-Id: I17dcf0bf53a1720acd8226ae3e30d84993562a91
/external/llvm/lib/Target/ARM/ARMSubtarget.h
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929bdb23794b615dc6b0cc59db21f0450c3ce33b |
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13-Nov-2013 |
Weiming Zhao <weimingz@codeaurora.org> |
Enable generating legacy IT block for AArch32 By default, the behavior of IT block generation will be determinated dynamically base on the arch (armv8 vs armv7). This patch adds backend options: -arm-restrict-it and -arm-no-restrict-it. The former one restricts the generation of IT blocks (the same behavior as thumbv8) for both arches. The later one allows the generation of legacy IT block (the same behavior as ARMv7 Thumb2) for both arches. Clang will support -mrestrict-it and -mno-restrict-it, which is compatible with GCC. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194592 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.h
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cb01efb7988d119d6e2aedab1740695aa6a9cc0c |
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03-Nov-2013 |
Bob Wilson <bob.wilson@apple.com> |
Enable optimization of sin / cos pair into call to __sincos_stret for iOS7+. rdar://12856873 Patch by Evan Cheng, with a fix for rdar://13209539 by Tilmann Scheller git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193942 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.h
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6186de5c54b580414b2d162e0f335b62b3d9812c |
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01-Nov-2013 |
Bradley Smith <bradley.smith@arm.com> |
[ARM] Add Virtualization subtarget feature and more build attributes in this area Add a Virtualization ARM subtarget feature along with adding proper build attribute emission for Tag_Virtualization_use (encodes Virtualization and TrustZone) and Tag_MPextension_use. Also rework test/CodeGen/ARM/2010-10-19-mc-elf-objheader.ll testcase to something that is more maintainable. This changes the focus of this testcase away from testing CPU defaults (which is tested elsewhere), onto specifically testing that attributes are encoded correctly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193859 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.h
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47c6d17b1cce85ba30471b2270419e35ba3d5653 |
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29-Oct-2013 |
Bernard Ogden <bogden@arm.com> |
ARM: Add subtarget feature for CRC Adds a subtarget feature for the CRC instructions (optional in v8-A) to the ARM (32-bit) backend. Differential Revision: http://llvm-reviews.chandlerc.com/D2036 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193599 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.h
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214c37d1816b62a25525282817f7088a1e2ed1dc |
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25-Oct-2013 |
Tim Northover <tnorthover@apple.com> |
ARM: don't expand atomicrmw inline on Cortex-M0 There's a barrier instruction so that should still be used, but most actual atomic operations are going to need a platform decision on the correct behaviour (either nop if single-threaded or OS-support otherwise). rdar://problem/15287210 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193399 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.h
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0d1e2aebe641fc26bba5d895bbcadcac6f23aaec |
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14-Oct-2013 |
Bernard Ogden <bogden@arm.com> |
Add Cortex-A57 support git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192591 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.h
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7220572e74844aa37b1b492ef67a8c1b403a254f |
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14-Oct-2013 |
Bernard Ogden <bogden@arm.com> |
Add subtarget feature support for Cortex-A53 Some previous implicit defaults have changed, for example FP and NEON are now on by default. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192590 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.h
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ca7b2d08d7b918e5e8e921a837623af962b27d00 |
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07-Oct-2013 |
Amara Emerson <amara.emerson@arm.com> |
[ARM] Improve build attributes emission. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192111 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.h
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cf3e4cb29a5fd485f11354060bb7a99e8cfdaf09 |
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07-Oct-2013 |
Tim Northover <tnorthover@apple.com> |
ARM: allow cortex-m0 to use hint instructions The hint instructions ("nop", "yield", etc) are mostly Thumb2-only, but have been ported across to the v6M architecture. Fortunately, v6M seems to sit nicely between v6 (thumb-1 only) and v6T2, so we can add a feature for it fairly easily. rdar://problem/15144406 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192097 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.h
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0f22c134be40a337b30e30bdafb9e8b6880dea1e |
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23-Sep-2013 |
Amara Emerson <amara.emerson@arm.com> |
[ARM] Split A/R class into separate subtarget features. Patch by Bradley Smith. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191202 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.h
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5df37dab763ce377095389c4ea1cff88db369954 |
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19-Sep-2013 |
Amara Emerson <amara.emerson@arm.com> |
[ARMv8] Add support for the v8 cryptography extensions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190996 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.h
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2a9af9f18eac90b0de739b6ceddf6c2209086303 |
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13-Sep-2013 |
Joey Gouly <joey.gouly@arm.com> |
[ARMv8] Change hasV8Fp to hasFPARMv8, and other command line options to be more consistent. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190692 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.h
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441c557708b5dbe91f1799baf790ad418c23ea70 |
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29-Aug-2013 |
Cameron Esfahani <dirty@apple.com> |
Clean up some usage of Triple. The base class has methods for determining if the target is iOS and Linux. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189604 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.h
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103ba845f09252d90a05109af7174f54bf412daf |
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16-Jul-2013 |
Renato Golin <renato.golin@linaro.org> |
ARM EABI divmod support This patch enables calls to __aeabi_idivmod when in EABI mode, by using the remainder value returned on registers (R1), enabled by the ARM triple "none-eabi". Note that Darwin and GNUEABI triples will continue lowering on GNU style, that is, using the stack for the remainder. Still need to add SREM/UREM support fix for 64-bit lowering. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186390 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.h
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75f29256f3587b19740398adb9678b6ba376912f |
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28-Jun-2013 |
David Blaikie <dblaikie@gmail.com> |
Remove unused member git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185219 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.h
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31d2f08f8893f38d2d7293195f3707edfefbeeb6 |
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27-Jun-2013 |
Joey Gouly <joey.gouly@arm.com> |
Add a Subtarget feature 'v8fp' to the ARM backend. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185073 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.h
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849eedce9921eb8f285cd0df0ad69ee5133459d1 |
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26-Jun-2013 |
Joey Gouly <joey.gouly@arm.com> |
Add a subtarget feature 'v8' to the ARM backend. This allows for targeting the ARMv8 AArch32 variant. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184967 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.h
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b94a353242b26af5c0969926a6b84664e342b586 |
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23-May-2013 |
Tim Northover <t.p.northover@gmail.com> |
ARM: Add Performance Monitor Extensions feature Performance monitors, including a basic cycle counter, are an official extension in the ARMv7 specification. This adds support for enabling and disabling them, orthogonally from CPU selection. rdar://problem/13939186 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182602 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.h
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bab06ba696694e7f62f964af7ee5290a13f78340 |
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18-May-2013 |
JF Bastien <jfb@google.com> |
Support unaligned load/store on more ARM targets This patch matches GCC behavior: the code used to only allow unaligned load/store on ARM for v6+ Darwin, it will now allow unaligned load/store for v6+ Darwin as well as for v7+ on Linux and NaCl. The distinction is made because v6 doesn't guarantee support (but LLVM assumes that Apple controls hardware+kernel and therefore have conformant v6 CPUs), whereas v7 does provide this guarantee (and Linux/NaCl behave sanely). The patch keeps the -arm-strict-align command line option, and adds -arm-no-strict-align. They behave similarly to GCC's -mstrict-align and -mnostrict-align. I originally encountered this discrepancy in FastIsel tests which expect unaligned load/store generation. Overall this should slightly improve performance in most cases because of reduced I$ pressure. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182175 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.h
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8c9e52a9fc1f99cf80c499ef10e6c8a54ef899d4 |
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10-Apr-2013 |
Tim Northover <Tim.Northover@arm.com> |
ARM: Make "SMC" instructions conditional on new TrustZone architecture feature. These instructions aren't universally available, but depend on a specific extension to the normal ARM architecture (rather than, say, v6/v7/...) so a new feature is appropriate. This also enables the feature by default on A-class cores which usually have these extensions, to avoid breaking existing code and act as a sensible default. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179171 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.h
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3382a840747c42c4a98eac802ee7b347a8ded1e4 |
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21-Mar-2013 |
Renato Golin <renato.golin@linaro.org> |
Avoid NEON SP-FP unless unsafe-math or Darwin NEON is not IEEE 754 compliant, so we should avoid lowering single-precision floating point operations with NEON unless unsafe-math is turned on. The equivalent VFP instructions are IEEE 754 compliant, but in some cores they're much slower, so some archs/OSs might still request it to be on by default, such as Swift and Darwin. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177651 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.h
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b26f98fa1f098b527cc84ef7535fe84d89953c21 |
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16-Feb-2013 |
Renato Golin <renato.golin@linaro.org> |
Typo git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175371 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.h
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901d80065c9afa0ba33e8546c2e1e99a00aceb14 |
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16-Feb-2013 |
Bill Wendling <isanbard@gmail.com> |
Reinitialize the ivars in the subtarget so that they can be reset with the new features. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175336 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.h
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ba6867d0ce3de9b7b4385f98d215edfcd36c4b32 |
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16-Feb-2013 |
Bill Wendling <isanbard@gmail.com> |
Temporary revert of 175320. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175322 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.h
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9be8b4fc92e1ace819a78db512c1f945c1471be7 |
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16-Feb-2013 |
Bill Wendling <isanbard@gmail.com> |
Reinitialize the ivars in the subtarget. When we're recalculating the feature set of the subtarget, we need to have the ivars in their initial state. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175320 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.h
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4788d14b484ba9e2fe19855fd6c97a3659980fca |
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15-Feb-2013 |
Bill Wendling <isanbard@gmail.com> |
Support changing the subtarget features in ARM. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175315 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.h
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0f156af8312a0f3ce88e5c006bf2a52691039ceb |
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30-Jan-2013 |
Eli Bendersky <eliben@google.com> |
Add a special ARM trap encoding for NaCl. More details in this thread: http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20130128/163783.html Patch by JF Bastien git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173943 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.h
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e0f1d712f656d3f958b616013f1d6008c5678949 |
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21-Dec-2012 |
Quentin Colombet <qcolombet@apple.com> |
Add ARM cortex-r5 subtarget. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170840 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.h
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139e407d526193017d42473c8d4892933de78f14 |
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20-Dec-2012 |
Evan Cheng <evan.cheng@apple.com> |
On some ARM cpus, flags setting movs with shifter operand, i.e. lsl, lsr, asr, are more expensive than the non-flag setting variant. Teach thumb2 size reduction pass to avoid generating them unless we are optimizing for size. rdar://12892707 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170728 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.h
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f659c0de6c7a4684a2a30c344ce6827ea87032d8 |
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04-Dec-2012 |
Eli Bendersky <eliben@google.com> |
Make NaCl naming consistent. The triple OSType is called NaCl and is represented textually as NativeClient. Also added a link to the native client project for readers unfamiliar with it. A Clang patch will follow shortly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169291 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.h
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a1514e24cc24b050f53a12650e047799358833a1 |
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04-Dec-2012 |
Chandler Carruth <chandlerc@gmail.com> |
Sort includes for all of the .h files under the 'lib' tree. These were missed in the first pass because the script didn't yet handle include guards. Note that the script is now able to handle all of these headers without manual edits. =] git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169224 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.h
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8facb9ecf21fc97409121842882dbc1dfd87b944 |
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29-Nov-2012 |
Quentin Colombet <qcolombet@apple.com> |
Add cortex-a5 subtarget to the supported ARM architectures git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168933 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.h
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eb1641d54a7eda7717304bc4d55d059208d8ebed |
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29-Sep-2012 |
Bob Wilson <bob.wilson@apple.com> |
Add LLVM support for Swift. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164899 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.h
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616471d4bfe4717fa86259ff4534703357b3b723 |
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13-Sep-2012 |
Silviu Baranga <silviu.baranga@arm.com> |
This patch introduces A15 as a target in LLVM. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163803 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.h
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d43b5c97cff06d7840b974ca84fa0639d2567968 |
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08-Aug-2012 |
Andrew Trick <atrick@apple.com> |
Added MispredictPenalty to SchedMachineModel. This replaces an existing subtarget hook on ARM and allows standard CodeGen passes to potentially use the property. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161471 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.h
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d598bd3aeea64fb0d2d3bd18de739a8a59cf043d |
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08-Aug-2012 |
Andrew Trick <atrick@apple.com> |
whitespace git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161469 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.h
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bee78fe5fcd8464f58bc729dede1a87d763ac3ae |
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11-Apr-2012 |
Evan Cheng <evan.cheng@apple.com> |
Clean up ARM fused multiply + add/sub support some more: rename some isel predicates. Also remove NEON2 since it's not really useful and it is confusing. If NEON + VFP4 implies NEON2 but NEON2 doesn't imply NEON + VFP4, what does it really mean? rdar://10139676 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154480 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.h
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82509e5c62a99912c636b22e227b810eaf6eda78 |
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11-Apr-2012 |
Evan Cheng <evan.cheng@apple.com> |
Fix a number of problems with ARM fused multiply add/subtract instructions. 1. The new instruction itinerary entries are not properly described. 2. The asm parser can't handle vfms and vfnms. 3. There were no assembler, disassembler test cases. 4. HasNEON2 has the wrong assembler predicate. rdar://10139676 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154456 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.h
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74bebde7c4e2d1cfd4a16c19ce3c87521df67639 |
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05-Mar-2012 |
Sebastian Pop <spop@codeaurora.org> |
updated patch for the ARM fused multiply add/sub In this update: - I assumed neon2 does not imply vfpv4, but neon and vfpv4 imply neon2. - I kept setting .fpu=neon-vfpv4 code attribute because that is what the assembler understands. Patch by Ana Pazos <apazos@codeaurora.org> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152036 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.h
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4bfcd4acbc7d12aa55f8de9af84a38422f0f6d83 |
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28-Feb-2012 |
Evan Cheng <evan.cheng@apple.com> |
Re-commit r151623 with fix. Only issue special no-return calls if it's a direct call. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151645 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.h
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20bd5296cec8d8d597ab9db2aca7346a88e580c8 |
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28-Feb-2012 |
Daniel Dunbar <daniel@zuster.org> |
Revert r151623 "Some ARM implementaions, e.g. A-series, does return stack prediction. ...", it is breaking the Clang build during the Compiler-RT part. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151630 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.h
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ec52aaa12f57896fc806e849fa21a61603050ac4 |
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28-Feb-2012 |
Evan Cheng <evan.cheng@apple.com> |
Some ARM implementaions, e.g. A-series, does return stack prediction. That is, the processor keeps a return addresses stack (RAS) which stores the address and the instruction execution state of the instruction after a function-call type branch instruction. Calling a "noreturn" function with normal call instructions (e.g. bl) can corrupt RAS and causes 100% return misprediction so LLVM should use a unconditional branch instead. i.e. mov lr, pc b _foo The "mov lr, pc" is issued in order to get proper backtrace. rdar://8979299 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151623 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.h
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31d157ae1ac2cd9c787dc3c1d28e64c682803844 |
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18-Feb-2012 |
Jia Liu <proljc@gmail.com> |
Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150878 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.h
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4b4e62219be91839091f9e35d8accf877f925d81 |
|
22-Jan-2012 |
Anton Korobeynikov <asl@math.spbu.ru> |
Add fused multiple+add instructions from VFPv4. Patch by Ana Pazos! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148658 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.h
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afff941211526a31f931aa9fcac84ae42ff60ef0 |
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20-Dec-2011 |
Evan Cheng <evan.cheng@apple.com> |
ARM target code clean up. Check for iOS, not Darwin where it makes sense. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146981 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.h
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44ee4714a8c245d4fdfd03840efcf58c3f66c6bc |
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09-Nov-2011 |
Evan Cheng <evan.cheng@apple.com> |
Hide cpu name checking in ARMSubtarget. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144154 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.h
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928698b14e4bcd0f231dc28e246920a242d81fc1 |
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18-Oct-2011 |
David Meyer <pdox@google.com> |
Remove NaClMode git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142338 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.h
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6d2f9cec715c50bca44816d9bdea97f8b63bf2a0 |
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07-Oct-2011 |
Bob Wilson <bob.wilson@apple.com> |
Reenable tail calls for iOS 5.0 and later. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141370 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.h
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acad68da50581de905a994ed3c6b9c197bcea687 |
|
28-Sep-2011 |
James Molloy <james.molloy@arm.com> |
Check in a patch that has already been code reviewed by Owen that I'd forgotten to commit. Build on previous patches to successfully distinguish between an M-series and A/R-series MSR and MRS instruction. These take different mask names and have a *slightly* different opcode format. Add decoder and disassembler tests. Improvement on the previous patch - successfully distinguish between valid v6m and v7m masks (one is a subset of the other). The patch had to be edited slightly to apply to ToT. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140696 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.h
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1fac6b50ea720d75fc2bf01a288e99f239869e90 |
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05-Sep-2011 |
Nick Lewycky <nicholas@mxc.ca> |
Add a new MC bit for NaCl (Native Client) mode. NaCl requires that certain instructions are more aligned than the CPU requires, and adds some additional directives, to follow in future patches. Patch by David Meyer! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139125 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.h
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4761a8d6549125e21d84371a9783bd41de2f55fa |
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07-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
Rewrite comment in English. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134627 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.h
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963b03c1a9f6a9742671459f103ee9a566c6de58 |
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07-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
Rename attribute 'thumb' to a more descriptive 'thumb-mode'. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134626 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.h
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0ddff1b5359433faf2eb1c4ff5320ddcbd42f52f |
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07-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
Compute feature bits at time of MCSubtargetInfo initialization. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134606 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.h
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39dfb0ff848be6b380ca81ff95d4ca4e0ae09c76 |
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07-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
Change some ARM subtarget features to be single bit yes/no in order to sink them down to MC layer. Also fix tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134590 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.h
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94ca42ff0407d71bacc41de4032d8dbe6358d33d |
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07-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
Factor ARM triple parsing out of ARMSubtarget. Another step towards making ARM subtarget info available to MC. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134569 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.h
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385e930d55f3ecd3c9538823dfa5896a12461845 |
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02-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
Rename XXXGenSubtarget.inc to XXXGenSubtargetInfo.inc for consistency. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134281 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.h
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a7603982dbf9e240ecc7ed6eddcd1cdb868107ac |
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01-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARMv7M vs. ARMv7E-M support. The DSP instructions in the Thumb2 instruction set are an optional extension in the Cortex-M* archtitecture. When present, the implementation is considered an "ARMv7E-M implementation," and when not, an "ARMv7-M implementation." Add a subtarget feature hook for the v7e-m instructions and hook it up. The cortex-m3 cpu is an example of a v7m implementation, while the cortex-m4 is a v7e-m implementation. rdar://9572992 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134261 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.h
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5b1b4489cf3a0f56f8be0673fc5cc380a32d277b |
|
01-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
Rename TargetSubtarget to TargetSubtargetInfo for consistency. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134259 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.h
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94214703d97d8d9dfca88174ffc7e94820a85e62 |
|
01-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
- Added MCSubtargetInfo to capture subtarget features and scheduling itineraries. - Refactor TargetSubtarget to be based on MCSubtargetInfo. - Change tablegen generated subtarget info to initialize MCSubtargetInfo and hide more details from targets. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134257 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.h
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276365dd4bc0c2160f91fd8062ae1fc90c86c324 |
|
30-Jun-2011 |
Evan Cheng <evan.cheng@apple.com> |
Fix the ridiculous SubtargetFeatures API where it implicitly expects CPU name to be the first encoded as the first feature. It then uses the CPU name to look up features / scheduling itineray even though clients know full well the CPU name being used to query these properties. The fix is to just have the clients explictly pass the CPU name! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134127 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.h
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ab8be96fd30ca9396e6b84fdddf1ac6208984cad |
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29-Jun-2011 |
Evan Cheng <evan.cheng@apple.com> |
Sink SubtargetFeature and TargetInstrItineraries (renamed MCInstrItineraries) into MC. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134049 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.h
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0b65599015f0b51304d941ba4a14aaf0d1734341 |
|
20-May-2011 |
Evan Cheng <evan.cheng@apple.com> |
Revert accidental commit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131739 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.h
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2e6496026f41d2c05ff038d14df9972f8a27fb94 |
|
20-May-2011 |
Evan Cheng <evan.cheng@apple.com> |
Revert r131664 and fix it in instcombine instead. rdar://9467055 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131708 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.h
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c8578948c9b35080dedd6527abf4f48fc4de43d3 |
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21-Apr-2011 |
Evan Cheng <evan.cheng@apple.com> |
Remove -use-divmod-libcall. Let targets opt in when they are available. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129884 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.h
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912225e18559a73228099330a4c253fdccf9fa3d |
|
19-Apr-2011 |
Daniel Dunbar <daniel@zuster.org> |
ADT/Triple: Move a variety of clients to using isOSDarwin() and isOSWindows() predicates. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129816 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.h
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5dde893c2bac9e1569c38429f756c1d723e8edf2 |
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19-Apr-2011 |
Bob Wilson <bob.wilson@apple.com> |
Avoid some 's' 16-bit instruction which partially update CPSR (and add false dependency) when it isn't dependent on last CPSR defining instruction. rdar://8928208 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129773 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.h
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463d358f1dfdd28a6900f2f109a160be71d2a8ef |
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31-Mar-2011 |
Evan Cheng <evan.cheng@apple.com> |
Distribute (A + B) * C to (A * C) + (B * C) to make use of NEON multiplier accumulator forwarding: vadd d3, d0, d1 vmul d3, d3, d2 => vmul d3, d0, d2 vmla d3, d1, d2 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128665 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.h
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b72d2a92b75daa9cbac7338aff0cd8ae04c2b4bd |
|
11-Jan-2011 |
Evan Cheng <evan.cheng@apple.com> |
Clean up ARM subtarget code by using Triple ADT. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123276 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.h
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2da8bc8a5f7705ac131184cd247f48500da0d74e |
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24-Dec-2010 |
Andrew Trick <atrick@apple.com> |
Various bits of framework needed for precise machine-level selection DAG scheduling during isel. Most new functionality is currently guarded by -enable-sched-cycles and -enable-sched-hazard. Added InstrItineraryData::IssueWidth field, currently derived from ARM itineraries, but could be initialized differently on other targets. Added ScheduleHazardRecognizer::MaxLookAhead to indicate whether it is active, and if so how many cycles of state it holds. Added SchedulingPriorityQueue::HasReadyFilter to allowing gating entry into the scheduler's available queue. ScoreboardHazardRecognizer now accesses the ScheduleDAG in order to get information about it's SUnits, provides RecedeCycle for bottom-up scheduling, correctly computes scoreboard depth, tracks IssueCount, and considers potential stall cycles when checking for hazards. ScheduleDAGRRList now models machine cycles and hazards (under flags). It tracks MinAvailableCycle, drives the hazard recognizer and priority queue's ready filter, manages a new PendingQueue, properly accounts for stall cycles, etc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122541 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.h
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6e8f4c404825b79f9b9176483653f1aa927dfbde |
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24-Dec-2010 |
Andrew Trick <atrick@apple.com> |
whitespace git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122539 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.h
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48575f6ea7d5cd21ab29ca370f58fcf9ca31400b |
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05-Dec-2010 |
Evan Cheng <evan.cheng@apple.com> |
Making use of VFP / NEON floating point multiply-accumulate / subtraction is difficult on current ARM implementations for a few reasons. 1. Even though a single vmla has latency that is one cycle shorter than a pair of vmul + vadd, a RAW hazard during the first (4? on Cortex-a8) can cause additional pipeline stall. So it's frequently better to single codegen vmul + vadd. 2. A vmla folowed by a vmul, vmadd, or vsub causes the second fp instruction to stall for 4 cycles. We need to schedule them apart. 3. A vmla followed vmla is a special case. Obvious issuing back to back RAW vmla + vmla is very bad. But this isn't ideal either: vmul vadd vmla Instead, we want to expand the second vmla: vmla vmul vadd Even with the 4 cycle vmul stall, the second sequence is still 2 cycles faster. Up to now, isel simply avoid codegen'ing fp vmla / vmls. This works well enough but it isn't the optimial solution. This patch attempts to make it possible to use vmla / vmls in cases where it is profitable. A. Add missing isel predicates which cause vmla to be codegen'ed. B. Make sure the fmul in (fadd (fmul)) has a single use. We don't want to compute a fmul and a fmla. C. Add additional isel checks for vmla, avoid cases where vmla is feeding into fp instructions (except for the #3 exceptional case). D. Add ARM hazard recognizer to model the vmla / vmls hazards. E. Add a special pre-regalloc case to expand vmla / vmls when it's likely the vmla / vmls will trigger one of the special hazards. Work in progress, only A+B are enabled. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120960 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.h
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dfed19fe2c34c1209108afa58e8ab014ffd894e2 |
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03-Nov-2010 |
Evan Cheng <evan.cheng@apple.com> |
Fix preload instruction isel. Only v7 supports pli, and only v7 with mp extension supports pldw. Add subtarget attribute to denote mp extension support and legalize illegal ones to nothing. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118160 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.h
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77f42b52781b6923924a93b8ab338d183887a592 |
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12-Oct-2010 |
Bob Wilson <bob.wilson@apple.com> |
PR8359: The ARM backend may end up allocating registers D16 to D31 when "-mattr=+vfp3" is specified. However, this will not work for hardware that only supports 16 registers. Add a new flag to support -"mattr=+vfp3,+d16". Patch by Jan Voung! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116310 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.h
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0febc4657b0edbf16b55ca5365d2b6aab45be7c5 |
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03-Oct-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Jim Asked us to move DataLayout on ARM back to the most specialized classes. Do so and also change X86 for consistency. Investigating if this can be improved a bit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115469 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.h
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7122ba7efb5430d724ed3a0ac86fa7f7185b43ba |
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29-Sep-2010 |
Bob Wilson <bob.wilson@apple.com> |
Increase ARM APCS preferred alignment for i64 and f64 from 32 bits to 64 bits. LDM/STM instructions can run one cycle faster on some ARM processors if the memory address is 64-bit aligned. Radar 8489376. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115047 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.h
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654d5440a477b1f6c89b051107e041a331f78e27 |
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28-Sep-2010 |
Owen Anderson <resistor@mac.com> |
Add a subtarget hook for reporting the misprediction penalty. Use this to provide more precise cost modeling for if-conversion. Now if only we had a way to estimate the misprediction probability. Adjsut CodeGen/ARM/ifcvt10.ll. The pipeline on Cortex-A8 is long enough that it is still profitable to predicate an ldm, but the shorter pipeline on Cortex-A9 makes it unprofitable. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114995 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.h
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02aba73a9ec04d0de9424422249af3948ca9573a |
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28-Sep-2010 |
Bob Wilson <bob.wilson@apple.com> |
Add a command line option "-arm-strict-align" to disallow unaligned memory accesses for ARM targets that would otherwise allow it. Radar 8465431. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114941 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.h
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3b9569e70db0b5a0d1389384a07fecbea8dc7dc2 |
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27-Sep-2010 |
Daniel Dunbar <daniel@zuster.org> |
Hard to imagine there are still people using inferior compilers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114862 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.h
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fd9493d74e5429eab44638cd9badbad9090cd713 |
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27-Sep-2010 |
Rafael Espindola <rafael.espindola@gmail.com> |
Odd additional stub framework for the ARM MC ELF emission. llc now recognizes the "intent" to support MC/obj emission for ARM, but given that they are all stubs, it asserts on --filetype=obj --march=arm Patch by Jason Kim. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114856 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.h
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3ef1c8759a20167457eb7fd82ebcaffe7ccaa1d1 |
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10-Sep-2010 |
Evan Cheng <evan.cheng@apple.com> |
Teach if-converter to be more careful with predicating instructions that would take multiple cycles to decode. For the current if-converter clients (actually only ARM), the instructions that are predicated on false are not nops. They would still take machine cycles to decode. Micro-coded instructions such as LDM / STM can potentially take multiple cycles to decode. If-converter should take treat them as non-micro-coded simple instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113570 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.h
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fcba5e6b645df89ae6b93911fe0f80b08fa6b44c |
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11-Aug-2010 |
Jim Grosbach <grosbach@apple.com> |
cortex m4 has floating point support, but only single precision. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110810 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.h
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7b4d31176efe6894bcfaa05257dd5783acda5ddc |
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11-Aug-2010 |
Evan Cheng <evan.cheng@apple.com> |
Report error if codegen tries to instantiate a ARM target when the cpu does support it. e.g. cortex-m* processors. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110798 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.h
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d6b463225674c10511b00f8f631a89b6da5afc54 |
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11-Aug-2010 |
Evan Cheng <evan.cheng@apple.com> |
Add ARM Archv6M and let it implies FeatureDB (having dmb, etc.) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110795 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.h
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11db068721d44fd5f9b0c2a3a4c90f813d2eae9c |
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11-Aug-2010 |
Evan Cheng <evan.cheng@apple.com> |
- Add subtarget feature -mattr=+db which determine whether an ARM cpu has the memory and synchronization barrier dmb and dsb instructions. - Change instruction names to something more sensible (matching name of actual instructions). - Added tests for memory barrier codegen. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110785 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.h
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e44be6381609d31b2d8879dbd5107e01404fa475 |
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09-Aug-2010 |
Evan Cheng <evan.cheng@apple.com> |
Change -prefer-32bit-thumb to attribute -mattr=+32bit instead to disable more 32-bit to 16-bit optimizations. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110584 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.h
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7a415999625f9791a8a7eea2027e628e29de15c0 |
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13-Jul-2010 |
Evan Cheng <evan.cheng@apple.com> |
Add an ARM "feature". Cortex-a8 fp comparison is very slow (> 20 cycles). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108256 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.h
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eae216c6d3d29cb9024ddf436a8f2ce222bb9ec8 |
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06-May-2010 |
Shantonu Sen <ssen@apple.com> |
Fix "warning: extra ';' inside a struct or union" when building llvm with clang git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103179 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.h
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29402132f3e890a2771818f44987ede213297431 |
|
06-May-2010 |
Jim Grosbach <grosbach@apple.com> |
Cleanup of ARMv7M support. Move hardware divide and Thumb2 extract/pack instructions to subtarget features and update tests to reflect. PR5717. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103136 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.h
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b1dc393bd56365ad8fabb51f22c2f3ace707c39a |
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05-May-2010 |
Jim Grosbach <grosbach@apple.com> |
Add initial support for ARMv7M subtarget and cortex-m3 cpu. Patch by Jordy <snhjordy@gmail.com>. Followup patches will add some tests and adjust to use Subtarget features for the instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103119 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.h
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46510a73e977273ec67747eb34cbdb43f815e451 |
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15-Apr-2010 |
Dan Gohman <gohman@apple.com> |
Add const qualifiers to CodeGen's use of LLVM IR constructs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101334 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.h
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6b2e8dc9a0e4ebda645ee4eba95711eb630b4edf |
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26-Mar-2010 |
Jim Grosbach <grosbach@apple.com> |
switch the use-vml[as] instructions flag to a subtarget 'feature' git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99565 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.h
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2676737e5ed3e4b5c89b4d06b60d998e9318eb73 |
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24-Mar-2010 |
Jim Grosbach <grosbach@apple.com> |
Make the use of the vmla and vmls VFP instructions controllable via cmd line. Preliminary testing shows significant performance wins by not using these instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99436 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.h
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631379e79c0971c5bac13629b8caf8912ed4c35c |
|
14-Mar-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
Add substarget feature for FP16 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98503 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.h
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4d6113ee0699ac1eff46971881179de53e2eb810 |
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11-Mar-2010 |
Bob Wilson <bob.wilson@apple.com> |
Lower small memcpys to load/stores on Thumb2. Radar 7686922. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98210 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.h
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ce7bf1c55f5238870bae2909cd368151f1d813d1 |
|
06-Mar-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
Initial bits of ARMv4-only support. Patch by John Tytgat! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97886 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.h
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15217e63bce6c161b355b63d6496c7c327d15817 |
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30-Nov-2009 |
Bob Wilson <bob.wilson@apple.com> |
Remove isProfitableToDuplicateIndirectBranch target hook. It is profitable for all the processors where I have tried it, and even when it might not help performance, the cost is quite low. The opportunities for duplicating indirect branches are limited by other factors so code size does not change much due to tail duplicating indirect branches aggressively. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90144 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.h
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5cdc3a949af0cef7f2163f8a7acbf3049c226321 |
|
24-Nov-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Materialize global addresses via movt/movw pair, this is always better than doing the same via constpool: 1. Load from constpool costs 3 cycles on A9, movt/movw pair - just 2. 2. Load from constpool might stall up to 300 cycles due to cache miss. 3. Movt/movw does not use load/store unit. 4. Less constpool entries => better compiler performance. This is only enabled on ELF systems, since darwin does not have needed relocations (yet). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89720 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.h
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834b08af8d3d8fc6c76ac6ca40674565689e8d7f |
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18-Nov-2009 |
Bob Wilson <bob.wilson@apple.com> |
Add a target hook to allow changing the tail duplication limit based on the contents of the block to be duplicated. Use this for ARM Cortex A8/9 to be more aggressive tail duplicating indirect branches, since it makes it much more likely that they will be predicted in the branch target buffer. Testcase coming soon. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89187 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.h
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87d21b92fc42f6b3bd8567a83fc5b5191c1205e5 |
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13-Nov-2009 |
David Goodwin <david_goodwin@apple.com> |
Allow target to specify regclass for which antideps will only be broken along the critical path. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@88682 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.h
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c2e8a7e8d2ab156afaa8ab0d0317dd9ee3db7d30 |
|
10-Nov-2009 |
David Goodwin <david_goodwin@apple.com> |
Fixed to address code review. No functional changes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86634 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.h
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0855dee564f80160abf95497475306af38ab7f84 |
|
10-Nov-2009 |
David Goodwin <david_goodwin@apple.com> |
Allow targets to specify register classes whose member registers should not be renamed to break anti-dependencies. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86628 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.h
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2e7be612d5d0eb42ee3ae08194dbb03b750cc6bf |
|
26-Oct-2009 |
David Goodwin <david_goodwin@apple.com> |
Break anti-dependence breaking out into its own class. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85127 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.h
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4c3715c2e5e17d7216a96ac2baf9720630f04408 |
|
23-Oct-2009 |
David Goodwin <david_goodwin@apple.com> |
Allow the target to select the level of anti-dependence breaking that should be performed by the post-RA scheduler. The default is none. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84911 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.h
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fa16354e0370fe884830286923352268b036737d |
|
16-Oct-2009 |
Evan Cheng <evan.cheng@apple.com> |
Change createPostRAScheduler so it can be turned off at llc -O1. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84273 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.h
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0dad89fa94536284d51f60868326294b725a0c61 |
|
30-Sep-2009 |
David Goodwin <david_goodwin@apple.com> |
Remove -post-RA-schedule flag and add a TargetSubtarget method to enable post-register-allocation scheduling. By default it is off. For ARM, enable/disable with -mattr=+/-postrasched. Enable by default for cortex-a8. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83122 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.h
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63476a80404125e5196b6c09113c1d4796da0604 |
|
03-Sep-2009 |
Evan Cheng <evan.cheng@apple.com> |
Reference to hidden symbols do not have to go through non-lazy pointer in non-pic mode. rdar://7187172. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80904 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.h
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e4e4ed3b56f63e9343e01bf0b2ecd7c1f45d296c |
|
29-Aug-2009 |
Evan Cheng <evan.cheng@apple.com> |
Let Darwin linker auto-synthesize stubs and lazy-pointers. This deletes a bunch of nasty code in ARM asm printer. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80404 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.h
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764ab52dd80310a205c9888bf166d09dab858f90 |
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11-Aug-2009 |
Jim Grosbach <grosbach@apple.com> |
Whitespace cleanup. Remove trailing whitespace. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78666 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.h
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1f0e404c87675ce75e34bcd91395c660fe1d4ac1 |
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05-Aug-2009 |
David Goodwin <david_goodwin@apple.com> |
By default, for cortex-a8 use NEON for single-precision FP. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78200 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.h
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42a83f2d15cbbc08f5be19856198e3c885221e9c |
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04-Aug-2009 |
David Goodwin <david_goodwin@apple.com> |
Initial support for single-precision FP using NEON. Added "neonfp" attribute to enable. Added patterns for some binary FP operations. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78081 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.h
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3be03406c9c3b2075d5ae416499af2f15f703d6f |
|
03-Aug-2009 |
Daniel Dunbar <daniel@zuster.org> |
Normalize Subtarget constructors to take a target triple string instead of Module*. Also, dropped uses of TargetMachine where unnecessary. The only target which still takes a TargetMachine& is Mips, I would appreciate it if someone would normalize this to match other targets. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77918 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.h
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3147fb2cff9ca0d258f8ab20ff23b9c447024df1 |
|
07-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
isThumb2 really should mean thumb2 only, not thumb2+. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74871 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.h
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d770d9e7d1f5c65b185897dcf226b3fc64598683 |
|
02-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Change the meaning of predicate hasThumb2 to mean thumb2 ISA is available, not that it's in thumb mode and thumb2 is available. Added isThumb2 predicate to replace the old predicate. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74692 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.h
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e481f127497b20d3abe625ca4c086f85bf8b126f |
|
25-Jun-2009 |
Bob Wilson <bob.wilson@apple.com> |
Revert 74164. We'll want to use this method later. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74176 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.h
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c9028e69f11246a051c3de1457cd89d46e82ca60 |
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25-Jun-2009 |
Bob Wilson <bob.wilson@apple.com> |
Remove unused hasV6T2Ops method. We already have a separate feature to identify Thumb2. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74164 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.h
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8557c2bcb8002169d890eb8485e9a1d7219e4343 |
|
19-Jun-2009 |
Evan Cheng <evan.cheng@apple.com> |
Latency information for ARM v6. It's rough and not yet hooked up. Right now we are only using branch latency to determine if-conversion limits. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73747 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.h
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cd828618b8c6ec58df94aec0f5546f009f2fd0d5 |
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19-Jun-2009 |
Evan Cheng <evan.cheng@apple.com> |
Remove UseThumbBacktraces. Just check if subtarget is darwin. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73734 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.h
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bb6296234238aab74a531b382d92342269bea902 |
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15-Jun-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Rename methods for the sake of consistency. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73428 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.h
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fbbf1eeccf0cf469f0d8962b1341c8ba22a9dadb |
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08-Jun-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Separate V6 from V6T2 since the latter has some extra nice instructions git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73085 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.h
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a7b0ded2a26003d91db6c58d6ad945a39f70585c |
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08-Jun-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Add helper for checking of Thumb1 mode git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73080 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.h
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70459bef9ccd73b3a2a44fdd62f2509861112745 |
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01-Jun-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Implement review feedback. Make thumb2 'normal' subtarget feature git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72698 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.h
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d4022c3fbb0705abdc8eddc3ee4a5059f5ef8094 |
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30-May-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Add placeholder for thumb2 stuff git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72593 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.h
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6d7d2aa38a247426e2ccf53e3c6ad0315c9a4d8c |
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23-May-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Add ARMv7 architecture, Cortex processors and different FPU modes handling. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72337 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.h
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41a024385f1220eadc48b48cb4c044a5fbc1b361 |
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23-May-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Propagate CPU string out of SubtargetFeatures git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72335 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.h
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707e0184233f27e0e9f9aee0309f2daab8cfe7f8 |
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12-Apr-2008 |
Dan Gohman <gohman@apple.com> |
Drop ISD::MEMSET, ISD::MEMMOVE, and ISD::MEMCPY, which are not Legal on any current target and aren't optimized in DAGCombiner. Instead of using intermediate nodes, expand the operations, choosing between simple loads/stores, target-specific code, and library calls, immediately. Previously, the code to emit optimized code for these operations was only used at initial SelectionDAG construction time; now it is used at all times. This fixes some cases where rep;movs was being used for small copies where simple loads/stores would be better. This also cleans up code that checks for alignments less than 4; let the targets make that decision instead of doing it in target-independent code. This allows x86 to use rep;movs in low-alignment cases. Also, this fixes a bug that resulted in the use of rep;stos for memsets of 0 with non-constant memory size when the alignment was at least 4. It's better to use the library in this case, which can be significantly faster when the size is large. This also preserves more SourceValue information when memory intrinsics are lowered into simple loads/stores. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49572 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.h
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4ee451de366474b9c228b4e5fa573795a715216d |
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29-Dec-2007 |
Chris Lattner <sabre@nondot.org> |
Remove attribution from file headers, per discussion on llvmdev. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45418 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.h
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e0703c84ddeb1a1276de4e38210c1127ef5df130 |
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31-Oct-2007 |
Rafael Espindola <rafael.espindola@gmail.com> |
Make ARM and X86 LowerMEMCPY identical by moving the isThumb check into getMaxInlineSizeThreshold and by restructuring the X86 version. New I just have to move this to a common place :-) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43554 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.h
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fc05f402ea22e8a9ae465d209b65be7e857a89ff |
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31-Oct-2007 |
Rafael Espindola <rafael.espindola@gmail.com> |
Make ARM an X86 memcpy expansion more similar to each other. Now both subtarget define getMaxInlineSizeThreshold and the expansion uses it. This should not change generated code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43552 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.h
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04321f70f5075673934d5b1ed3353dd15d911183 |
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23-Feb-2007 |
Evan Cheng <evan.cheng@apple.com> |
Added -march=thumb; removed -enable-thumb. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34521 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.h
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3630e78db9268dbe81a9369a33e49b857804f2ec |
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13-Feb-2007 |
Lauro Ramos Venancio <lauro.venancio@gmail.com> |
Add ABI information to ARM subtarget. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34245 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.h
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1a3771e30e48b9cc21ccdc79fc9cf37ec4104b17 |
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19-Jan-2007 |
Evan Cheng <evan.cheng@apple.com> |
Introduce TargetType's ELF and Darwin. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33363 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.h
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a8e2989ece6dc46df59b0768184028257f913843 |
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19-Jan-2007 |
Evan Cheng <evan.cheng@apple.com> |
ARM backend contribution from Apple. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33353 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/ARM/ARMSubtarget.h
|