| 4c5e43da7792f75567b693105cc53e3f1992ad98 |
|
08-Apr-2015 |
Pirama Arumuga Nainar <pirama@google.com> |
Update aosp/master llvm for rebase to r233350
Change-Id: I07d935f8793ee8ec6b7da003f6483046594bca49
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.h
|
| ebe69fe11e48d322045d5949c83283927a0d790b |
|
23-Mar-2015 |
Stephen Hines <srhines@google.com> |
Update aosp/master LLVM for rebase to r230699.
Change-Id: I2b5be30509658cb8266be782de0ab24f9099f9b9
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.h
|
| 37ed9c199ca639565f6ce88105f9e39e898d82d0 |
|
01-Dec-2014 |
Stephen Hines <srhines@google.com> |
Update aosp/master LLVM for rebase to r222494.
Change-Id: Ic787f5e0124df789bd26f3f24680f45e678eef2d
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.h
|
| c6a4f5e819217e1e12c458aed8e7b122e23a3a58 |
|
21-Jul-2014 |
Stephen Hines <srhines@google.com> |
Update LLVM for rebase to r212749.
Includes a cherry-pick of:
r212948 - fixes a small issue with atomic calls
Change-Id: Ib97bd980b59f18142a69506400911a6009d9df18
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.h
|
| dce4a407a24b04eebc6a376f8e62b41aaa7b071f |
|
29-May-2014 |
Stephen Hines <srhines@google.com> |
Update LLVM for 3.5 rebase (r209712).
Change-Id: I149556c940fb7dc92d075273c87ff584f400941f
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.h
|
| 36b56886974eae4f9c5ebc96befd3e7bfe5de338 |
|
24-Apr-2014 |
Stephen Hines <srhines@google.com> |
Update to LLVM 3.5a.
Change-Id: Ifadecab779f128e62e430c2b4f6ddd84953ed617
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.h
|
| 354362524a72b3fa43a6c09380b7ae3b2380cbba |
|
19-Nov-2013 |
Juergen Ributzka <juergen@apple.com> |
[weak vtables] Remove a bunch of weak vtables
This patch removes most of the trivial cases of weak vtables by pinning them to
a single object file. The memory leaks in this version have been fixed. Thanks
Alexey for pointing them out.
Differential Revision: http://llvm-reviews.chandlerc.com/D2068
Reviewed by Andy
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195064 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.h
|
| b21ab43cfc3fa0dacf5c95f04e58b6d804b59a16 |
|
18-Nov-2013 |
Alexey Samsonov <samsonov@google.com> |
Revert r194865 and r194874.
This change is incorrect. If you delete virtual destructor of both a base class
and a subclass, then the following code:
Base *foo = new Child();
delete foo;
will not cause the destructor for members of Child class. As a result, I observe
plently of memory leaks. Notable examples I investigated are:
ObjectBuffer and ObjectBufferStream, AttributeImpl and StringSAttributeImpl.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194997 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.h
|
| 5a364c5561ec04e33a6f5d52c14f1bac6f247ea0 |
|
15-Nov-2013 |
Juergen Ributzka <juergen@apple.com> |
[weak vtables] Remove a bunch of weak vtables
This patch removes most of the trivial cases of weak vtables by pinning them to
a single object file.
Differential Revision: http://llvm-reviews.chandlerc.com/D2068
Reviewed by Andy
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194865 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.h
|
| 0187e7a9ba5c50b4559e0c2e0afceb6d5cd32190 |
|
16-Jun-2013 |
David Blaikie <dblaikie@gmail.com> |
DebugInfo: remove target-specific Frame Index handling for DBG_VALUE MachineInstrs
Frame index handling is now target-agnostic, so delete the target hooks
for creation & asm printing of target-specific addressing in DBG_VALUEs
and any related functions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184067 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.h
|
| 860c08cad5b7c1359123bb2b0e74df4b6e48a15c |
|
19-Apr-2013 |
Hal Finkel <hfinkel@anl.gov> |
Implement optimizeCompareInstr for PPC
Many PPC instructions have a so-called 'record form' which stores to a specific
condition register the result of comparing the result of the instruction with
zero (always as a signed comparison). For integer operations on PPC64, this is
always a 64-bit comparison.
This implementation is derived from the implementation in the ARM backend;
there are some differences because PPC condition registers are allocatable
virtual registers (although the record forms always use a specific one), and we
look for a matching subtraction instruction after the compare (but before the
first use) in addition to before it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179802 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.h
|
| da47e17a6f58bb4dae22d3e79c69fcb1d254ba44 |
|
10-Apr-2013 |
Hal Finkel <hfinkel@anl.gov> |
PPC: Don't predicate a diamond with two counter decrements
I've not seen this happen in practice, and probably can't until we start
allowing decrement-counter-based conditional branches to be double predicated,
but just in case, don't allow predication of a diamond in which both sides have
ctr-defining branches. Even though the branching behavior of these can be
predicated, the counter-decrementing behavior cannot be.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179199 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.h
|
| 7eb0d8148e1210d9e31ab471477de47b53bab117 |
|
10-Apr-2013 |
Hal Finkel <hfinkel@anl.gov> |
Allow PPC B and BLR to be if-converted into some predicated forms
This enables us to form predicated branches (which are the same conditional
branches we had before) and also a larger set of predicated returns (including
instructions like bdnzlr which is a conditional return and loop-counter
decrement all in one).
At the moment, if conversion does not capture all possible opportunities. A
simple example is provided in early-ret2.ll, where if conversion forms one
predicated return, and then the PPCEarlyReturn pass picks up the other one. So,
at least for now, we'll keep both mechanisms.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179134 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.h
|
| 839b9096538f790a2bb060547df24703807cb83b |
|
06-Apr-2013 |
Hal Finkel <hfinkel@anl.gov> |
Implement PPCInstrInfo::FoldImmediate
There are certain PPC instructions into which we can fold a zero immediate
operand. We can detect such cases by looking at the register class required
by the using operand (so long as it is not otherwise constrained).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178961 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.h
|
| ff56d1a2011f239e114267c13302ea26db4f8046 |
|
06-Apr-2013 |
Hal Finkel <hfinkel@anl.gov> |
Enable early if conversion on PPC
On cores for which we know the misprediction penalty, and we have
the isel instruction, we can profitably perform early if conversion.
This enables us to replace some small branch sequences with selects
and avoid the potential stalls from mispredicting the branches.
Enabling this feature required implementing canInsertSelect and
insertSelect in PPCInstrInfo; isel code in PPCISelLowering was
refactored to use these functions as well.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178926 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.h
|
| 3f2c047f32c9b488d9c49bb2dc87b979530dab3f |
|
23-Mar-2013 |
Hal Finkel <hfinkel@anl.gov> |
Note in PPCFunctionInfo VRSAVE spills
In preparation for using the new register scavenger capability for providing
more than one register simultaneously, specifically note functions that have
spilled VRSAVE (currently, this can happen only in functions that use the
setjmp intrinsic). As with CR spilling, such functions will need to provide two
emergency spill slots to the scavenger.
No functionality change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177832 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.h
|
| 324972904353594ad4a0cdfc79370f85e9fb9c8f |
|
17-Mar-2013 |
Hal Finkel <hfinkel@anl.gov> |
Improve PPC VR (Altivec) register spilling
This change cleans up two issues with Altivec register spilling:
1. The spilling code was inefficient (using two instructions, and add and a
load, when just one would do)
2. The code assumed that r0 would always be available (true for now, but this
will change)
The new code handles VR spilling just like GPR spills but forced into r+r mode.
As a result, when any VR spills are present, we must now always allocate the
register-scavenger spill slot.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177231 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.h
|
| 7164288c3eb52e20454fc757440f867f04eb13a4 |
|
19-Jun-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Implement PPCInstrInfo::isCoalescableExtInstr().
The PPC::EXTSW instruction preserves the low 32 bits of its input, just
like some of the x86 instructions. Use it to reduce register pressure
when the low 32 bits have multiple uses.
This requires a small change to PeepholeOptimizer since EXTSW takes a
64-bit input register.
This is related to PR5997.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158743 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.h
|
| 79aa3417eb6f58d668aadfedf075240a41d35a26 |
|
17-Mar-2012 |
Craig Topper <craig.topper@gmail.com> |
Reorder includes in Target backends to following coding standards. Remove some superfluous forward declarations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152997 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.h
|
| 31d157ae1ac2cd9c787dc3c1d28e64c682803844 |
|
18-Feb-2012 |
Jia Liu <proljc@gmail.com> |
Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150878 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.h
|
| d21e930eac3d99dd77ee33ea5826700b4bc97ae8 |
|
06-Dec-2011 |
Hal Finkel <hfinkel@anl.gov> |
add RESTORE_CR and support CR unspills
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145961 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.h
|
| 64c34e253563a8ba6b41fbce2bb020632cf65961 |
|
02-Dec-2011 |
Hal Finkel <hfinkel@anl.gov> |
update PPC 940 hazard rec. to function in postRA mode
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145676 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.h
|
| 4db3cffe94a5285239cc0056f939c6b74a5ca0b6 |
|
01-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
Hide the call to InitMCInstrInfo into tblgen generated ctor.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134244 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.h
|
| 2da8bc8a5f7705ac131184cd247f48500da0d74e |
|
24-Dec-2010 |
Andrew Trick <atrick@apple.com> |
Various bits of framework needed for precise machine-level selection
DAG scheduling during isel. Most new functionality is currently
guarded by -enable-sched-cycles and -enable-sched-hazard.
Added InstrItineraryData::IssueWidth field, currently derived from
ARM itineraries, but could be initialized differently on other targets.
Added ScheduleHazardRecognizer::MaxLookAhead to indicate whether it is
active, and if so how many cycles of state it holds.
Added SchedulingPriorityQueue::HasReadyFilter to allowing gating entry
into the scheduler's available queue.
ScoreboardHazardRecognizer now accesses the ScheduleDAG in order to
get information about it's SUnits, provides RecedeCycle for bottom-up
scheduling, correctly computes scoreboard depth, tracks IssueCount, and
considers potential stall cycles when checking for hazards.
ScheduleDAGRRList now models machine cycles and hazards (under
flags). It tracks MinAvailableCycle, drives the hazard recognizer and
priority queue's ready filter, manages a new PendingQueue, properly
accounts for stall cycles, etc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122541 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.h
|
| 6e8f4c404825b79f9b9176483653f1aa927dfbde |
|
24-Dec-2010 |
Andrew Trick <atrick@apple.com> |
whitespace
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122539 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.h
|
| b908258d59745ab9f150c66f94541951cf9c9211 |
|
15-Nov-2010 |
Chris Lattner <sabre@nondot.org> |
implement support for the MO_DARWIN_STUB TargetOperand flag,
and have isel apply to to call operands as required. This allows
us to get $stub suffixes on label references on ppc/tiger with the
new instprinter, fixing two tests. Only 2 to go.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119093 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.h
|
| 78e6e009223a38739797629ca2d217acf86dda93 |
|
17-Jul-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Remove the isMoveInstr() hook.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108567 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.h
|
| 600f171486708734e2b9c9c617528cfc51c16850 |
|
11-Jul-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
RISC architectures get their memory operand folding for free.
The only folding these load/store architectures can do is converting COPY into a
load or store, and the target independent part of foldMemoryOperand already
knows how to do that.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108099 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.h
|
| 27689b0affee8fb1bfbef11dcc84287b7757cfe8 |
|
11-Jul-2010 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Replace copyRegToReg with copyPhysReg for PowerPC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108083 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.h
|
| 3bf912593301152b65accb9d9c37a95172f1df5a |
|
18-Jun-2010 |
Stuart Hastings <stuart@apple.com> |
Add a DebugLoc parameter to TargetInstrInfo::InsertBranch(). This
addresses a longstanding deficiency noted in many FIXMEs scattered
across all the targets.
This effectively moves the problem up one level, replacing eleven
FIXMEs in the targets with eight FIXMEs in CodeGen, plus one path
through FastISel where we actually supply a DebugLoc, fixing Radar
7421831.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106243 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.h
|
| 34dcc6fadca0a1117cdbd0e9b35c991a55b6e556 |
|
06-May-2010 |
Dan Gohman <gohman@apple.com> |
Add a DebugLoc argument to TargetInstrInfo::copyRegToReg, so that it
doesn't have to guess.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103194 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.h
|
| 746ad69e088176819981b4b2c5ac8dcd49f5e60e |
|
06-May-2010 |
Evan Cheng <evan.cheng@apple.com> |
Add argument TargetRegisterInfo to loadRegFromStackSlot and storeRegToStackSlot.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103193 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.h
|
| 8601a3d4decff0a380e059b037dabf71075497d3 |
|
29-Apr-2010 |
Evan Cheng <evan.cheng@apple.com> |
Frame index can be negative.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102577 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.h
|
| 0965217e74fe07f1451350a80114ab566ced5de0 |
|
26-Apr-2010 |
Evan Cheng <evan.cheng@apple.com> |
Add PPC specific emitFrameIndexDebugValue.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102325 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.h
|
| 864e2efce2cb5d02e376933933d96074723fe77c |
|
05-Dec-2009 |
Dan Gohman <gohman@apple.com> |
Remove the target hook TargetInstrInfo::BlockHasNoFallThrough in favor of
MachineBasicBlock::canFallThrough(), which is target-independent and more
thorough.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90634 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.h
|
| 15217e63bce6c161b355b63d6496c7c327d15817 |
|
30-Nov-2009 |
Bob Wilson <bob.wilson@apple.com> |
Remove isProfitableToDuplicateIndirectBranch target hook. It is profitable
for all the processors where I have tried it, and even when it might not help
performance, the cost is quite low. The opportunities for duplicating
indirect branches are limited by other factors so code size does not change
much due to tail duplicating indirect branches aggressively.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90144 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.h
|
| de9b1dae37877f1b31e8cf42a14195c3fffbae3f |
|
25-Nov-2009 |
Bob Wilson <bob.wilson@apple.com> |
Tail duplicate indirect branches for PowerPC, too.
With the testcase for pr3120, the "threaded interpreter" runtime decreases
from 1788 to 1413 with this change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89877 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.h
|
| 3a6b9eb868f579b945aa8ec8fadf65e4dd913555 |
|
12-Oct-2009 |
Dale Johannesen <dalej@apple.com> |
Revert the kludge in 76703. I got a clean
bootstrap of FSF-style PPC, so there is some
reason to believe the original bug (which was
never analyzed) has been fixed, probably by
82266.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83871 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.h
|
| 23ed52752bb40a9085c9d36bbc6603972c3e0080 |
|
24-Jul-2009 |
Eli Friedman <eli.friedman@gmail.com> |
Remove unused member functions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76960 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.h
|
| fc6ad402fb267cba1625801444aad30da43d383a |
|
22-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
Let each target determines whether a machine instruction is dead. If true, that allows late codeine passes to delete it.
This is considered a workaround. The problem is some targets are not modeling side effects correctly. PPC is apparently one of those. This patch allows ppc llvm-gcc to bootstrap on Darwin. Once we find out which instruction definitions are wrong, we can remove the PPCInstrInfo workaround.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76703 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.h
|
| d1c321a89ab999b9bb602b0f398ecd4c2022262c |
|
12-Feb-2009 |
Bill Wendling <isanbard@gmail.com> |
Move debug loc info along when the spiller creates new instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64342 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.h
|
| dc54d317e7a381ef8e4aca80d54ad1466bb85dda |
|
09-Feb-2009 |
Evan Cheng <evan.cheng@apple.com> |
Turns out AnalyzeBranch can modify the mbb being analyzed. This is a nasty
suprise to some callers, e.g. register coalescer. For now, add an parameter
that tells AnalyzeBranch whether it's safe to modify the mbb. A better
solution is out there, but I don't have time to deal with it right now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64124 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.h
|
| 770bcc7b15adbc978800db70dbb1c3c22913b52c |
|
06-Feb-2009 |
Evan Cheng <evan.cheng@apple.com> |
Move getPointerRegClass from TargetInstrInfo to TargetRegisterInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63938 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.h
|
| 04ee5a1d9267e5e6fab8f088095fcb83c3c5cbd1 |
|
20-Jan-2009 |
Evan Cheng <evan.cheng@apple.com> |
Change TargetInstrInfo::isMoveInstr to return source and destination sub-register indices as well.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62600 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.h
|
| c54baa2d43730f1804acfb4f4e738fba72f966bd |
|
03-Dec-2008 |
Dan Gohman <gohman@apple.com> |
Split foldMemoryOperand into public non-virtual and protected virtual
parts, and add target-independent code to add/preserve
MachineMemOperands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60488 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.h
|
| cbad42cfd1cc93a41ff26ea2e8895bfbc09f54f2 |
|
18-Nov-2008 |
Dan Gohman <gohman@apple.com> |
Add more const qualifiers. This fixes build breakage from r59540.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59542 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.h
|
| 8e8b8a223c2b0e69f44c0639f846260c8011668f |
|
16-Oct-2008 |
Dan Gohman <gohman@apple.com> |
Const-ify several TargetInstrInfo methods.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57622 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.h
|
| 940f83e772ca2007d62faffc83094bd7e8da6401 |
|
26-Aug-2008 |
Owen Anderson <resistor@mac.com> |
Make TargetInstrInfo::copyRegToReg return a bool indicating whether the copy requested
was inserted or not. This allows bitcast in fast isel to properly handle the case
where an appropriate reg-to-reg copy is not available.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55375 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.h
|
| 44eb65cf58e3ab9b5621ce72256d1621a18aeed7 |
|
15-Aug-2008 |
Owen Anderson <resistor@mac.com> |
Convert uses of std::vector in TargetInstrInfo to SmallVector. This change had to be propoagated down into all the targets and up into all clients of this API.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54802 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.h
|
| 8e5f2c6f65841542e2a7092553fe42a00048e4c7 |
|
08-Jul-2008 |
Dan Gohman <gohman@apple.com> |
Pool-allocation for MachineInstrs, MachineBasicBlocks, and
MachineMemOperands. The pools are owned by MachineFunctions.
This drastically reduces the number of calls to malloc/free made
during the "Emit" phase of scheduling, as well as later phases
in CodeGen. Combined with other changes, this speeds up the
"instruction selection" phase of CodeGen by 10% in some cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53212 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.h
|
| 58dcb0e0cd3fa973b5fd005aecab1df6aeea5cd6 |
|
16-Jun-2008 |
Evan Cheng <evan.cheng@apple.com> |
Add option to commuteInstruction() which forces it to create a new (commuted) instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52308 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.h
|
| c9f5f3f64f896d0a8c8fa35a1dd98bc57b8960f6 |
|
14-May-2008 |
Dan Gohman <gohman@apple.com> |
Change target-specific classes to use more precise static types.
This eliminates the need for several awkward casts, including
the last dynamic_cast under lib/Target.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51091 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.h
|
| 52e724ad7e679ee590f4bd763d55280586a8f1bc |
|
16-Apr-2008 |
Nicolas Geoffray <nicolas.geoffray@lip6.fr> |
Infrastructure for getting the machine code size of a function and an instruction. X86, PowerPC and ARM are implemented
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49809 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.h
|
| 950a4c40b823cd4f09dc71be635229246dfd6cac |
|
25-Mar-2008 |
Dan Gohman <gohman@apple.com> |
Add explicit keywords.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48801 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.h
|
| 4a66e9a57e679b4f3243bf2061daf53c70102030 |
|
10-Mar-2008 |
Bill Wendling <isanbard@gmail.com> |
Change the "enable/disable" mechanism so that we can enable PPC register
scavenging for 32-bit and 64-bit separately.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48186 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.h
|
| 6f0d024a534af18d9e60b3ea757376cd8a3a980e |
|
10-Feb-2008 |
Dan Gohman <gohman@apple.com> |
Rename MRegisterInfo to TargetRegisterInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46930 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.h
|
| 5fd79d0560570fed977788a86fa038b898564dfa |
|
08-Feb-2008 |
Evan Cheng <evan.cheng@apple.com> |
It's not always safe to fold movsd into xorpd, etc. Check the alignment of the load address first to make sure it's 16 byte aligned.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46893 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.h
|
| 43dbe05279b753aabda571d9c83eaeb36987001a |
|
07-Jan-2008 |
Owen Anderson <resistor@mac.com> |
Move even more functionality from MRegisterInfo into TargetInstrInfo.
Some day I'll get it all moved over...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45672 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.h
|
| f6372aa1cc568df19da7c5023e83c75aa9404a07 |
|
01-Jan-2008 |
Owen Anderson <resistor@mac.com> |
Move some more instruction creation methods from RegisterInfo into InstrInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45484 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.h
|
| 641055225092833197efe8e5bce01d50bcf1daae |
|
01-Jan-2008 |
Chris Lattner <sabre@nondot.org> |
Fix a problem where lib/Target/TargetInstrInfo.h would include and use
a header file from libcodegen. This violates a layering order: codegen
depends on target, not the other way around. The fix to this is to
split TII into two classes, TII and TargetInstrInfoImpl, which defines
stuff that depends on libcodegen. It is defined in libcodegen, where
the base is not.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45475 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.h
|
| d10fd9791c20fd8368fa0ce94b626b769c6c8ba0 |
|
31-Dec-2007 |
Owen Anderson <resistor@mac.com> |
Move copyRegToReg from MRegisterInfo to TargetInstrInfo. This is part of the
Machine-level API cleanup instigated by Chris.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45470 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.h
|
| 4ee451de366474b9c228b4e5fa573795a715216d |
|
29-Dec-2007 |
Chris Lattner <sabre@nondot.org> |
Remove attribution from file headers, per discussion on llvmdev.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45418 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.h
|
| b5cdaa257e167a08a8a54ea9249d847ccc415ce0 |
|
18-May-2007 |
Evan Cheng <evan.cheng@apple.com> |
RemoveBranch() and InsertBranch() now returns number of instructions deleted / inserted.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37192 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.h
|
| 1ee29257428960fede862fcfdbe80d5d007927e9 |
|
26-Jan-2007 |
Jim Laskey <jlaskey@mac.com> |
Make LABEL a builtin opcode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33537 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.h
|
| df4ed6350b2a51f71c0980e86c9078f4046ea706 |
|
17-Nov-2006 |
Chris Lattner <sabre@nondot.org> |
start using PPC predicates more consistently.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31833 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.h
|
| ef13982aa7f3e57e82cd48370e79033dff0da295 |
|
28-Oct-2006 |
Chris Lattner <sabre@nondot.org> |
implement the BlockHasNoFallThrough hook
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31264 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.h
|
| ae1dc403274d3a64bcee31f15e2d25e4b7178811 |
|
18-Oct-2006 |
Chris Lattner <sabre@nondot.org> |
expose DWARF_LABEL opcode# so the branch folder can update debug info properly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31024 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.h
|
| c50e2bcdf7bff1f9681ab80e52691f274950fab5 |
|
13-Oct-2006 |
Chris Lattner <sabre@nondot.org> |
implement branch inspection/modification methods.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30946 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.h
|
| b1d26f66658cff3ceb7d44a72fbc8c8e975532f9 |
|
17-Jun-2006 |
Chris Lattner <sabre@nondot.org> |
Implement the getPointerRegClass method, which is required for the ptr_rc
magic to work.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28847 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.h
|
| d74ea2bbd8bb630331f35ead42d385249bd42af8 |
|
24-May-2006 |
Chris Lattner <sabre@nondot.org> |
Patches to make the LLVM sources more -pedantic clean. Patch provided
by Anton Korobeynikov! This is a step towards closing PR786.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28447 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.h
|
| fd97734f3636f54a86890918096d3d692df0b939 |
|
13-Mar-2006 |
Chris Lattner <sabre@nondot.org> |
Mark instructions that are cracked by the PPC970 decoder as such.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26720 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.h
|
| 88d211f82304e53694ece666d4a2507b170e4582 |
|
12-Mar-2006 |
Chris Lattner <sabre@nondot.org> |
Several big changes:
1. Use flags on the instructions in the .td file to indicate the PPC970 unit
type instead of a table in the .cpp file. Much cleaner.
2. Change the hazard recognizer to build d-groups according to the actual
algorithm used, not my flawed understanding of it.
3. Model "must be in the first slot" and "must be the only instr in a group"
accurately.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26719 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.h
|
| bbf1c72d51a77bf54c9c684b90a78e59f0b70b2f |
|
06-Mar-2006 |
Chris Lattner <sabre@nondot.org> |
implement TII::insertNoop
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26562 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.h
|
| 6524287c53cf727a8ef33517403fcb1bbd7adff9 |
|
02-Feb-2006 |
Chris Lattner <sabre@nondot.org> |
implement isStoreToStackSlot for PPC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25914 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.h
|
| 408396014742a05cad1c91949d2226169e3f9d80 |
|
02-Feb-2006 |
Chris Lattner <sabre@nondot.org> |
Move isLoadFrom/StoreToStackSlot from MRegisterInfo to TargetInstrInfo,a far more logical place. Other methods should also be moved if anyoneis interested. :)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25913 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.h
|
| c16257f05391b8aeccef62d6b543f1cb5a8185fe |
|
18-Jan-2006 |
Chris Lattner <sabre@nondot.org> |
fix out of date comment
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25422 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.h
|
| e44b2d16ee088c44ebbe6f21a2af8b5321b68e48 |
|
18-Jan-2006 |
Chris Lattner <sabre@nondot.org> |
Fix Regression/CodeGen/PowerPC/2006-01-18-InvalidBranchOpcodeAssert.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25421 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.h
|
| 21e463b2bf864671a87ebe386cb100ef9349a540 |
|
16-Oct-2005 |
Nate Begeman <natebegeman@mac.com> |
More PPC32 -> PPC changes, as well as merging some classes that were
redundant after the change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23759 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.h
|
| 16e71f2f70811c69c56052dd146324fe20e31db5 |
|
15-Oct-2005 |
Chris Lattner <sabre@nondot.org> |
Rename PPC32*.h to PPC*.h
This completes the grand PPC file renaming
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23745 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.h
|
| 2668959b8879097db368aec7d76c455260abc75b |
|
15-Oct-2005 |
Chris Lattner <sabre@nondot.org> |
Rename PowerPC*.h to PPC*.h
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23743 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.h
|
| 617742b1b8b7fbb07b4ab5db7c292bff78d709f6 |
|
15-Oct-2005 |
Chris Lattner <sabre@nondot.org> |
Nuke PowerPCInstrFormats.h, its contents are dead. Remove the definitions
from the .td file that correspond to it
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23736 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.h
|
| 043870dd85ea41e8972c304b122070a417c8a4bc |
|
09-Sep-2005 |
Chris Lattner <sabre@nondot.org> |
Teach the code generator that rlwimi is commutable if the rotate amount
is zero. This lets the register allocator elide some copies in some cases.
This implements CodeGen/PowerPC/rlwimi-commute.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23292 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.h
|
| b5f662fa0314f7e7e690aae8ebff7136cc3a5ab0 |
|
22-Apr-2005 |
Misha Brukman <brukman+llvm@gmail.com> |
Remove trailing whitespace
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21425 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.h
|
| f2ccb77ee9d8ab35866dae111fa36929689c7511 |
|
17-Aug-2004 |
Misha Brukman <brukman+llvm@gmail.com> |
PowerPC 32-/64-bit split: Part I, PPC32* bit files, adapted from former PowerPC*
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15850 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstrInfo.h
|