| 36b56886974eae4f9c5ebc96befd3e7bfe5de338 |
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24-Apr-2014 |
Stephen Hines <srhines@google.com> |
Update to LLVM 3.5a.
Change-Id: Ifadecab779f128e62e430c2b4f6ddd84953ed617
/external/llvm/lib/Target/PowerPC/PPCScheduleG5.td
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| 1abaf907b6aff6e468cb838fa40e0ec6cc5ece24 |
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05-Apr-2013 |
Hal Finkel <hfinkel@anl.gov> |
Add a SchedMachineModel for the PPC G5
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178850 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCScheduleG5.td
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| 8dc440a46a5153a1640a3050480cceca9b8af05d |
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28-Aug-2012 |
Hal Finkel <hfinkel@anl.gov> |
Split several PPC instruction classes.
Slight reorganisation of PPC instruction classes for scheduling. No
functionality change for existing subtargets.
- Clearly separate load/store-with-update instructions from regular loads and stores.
- Split IntRotateD -> IntRotateD and IntRotateDI
- Split out fsub and fadd from FPGeneral -> FPAddSub
- Update existing itineraries
Patch by Tobias von Koch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162729 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCScheduleG5.td
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| 16803097fbefa313fdadc3adede659bd0e52cec1 |
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12-Jun-2012 |
Hal Finkel <hfinkel@anl.gov> |
Split out the PPC instruction class IntSimple from IntGeneral.
On the POWER7, adds and logical operations can also be handled
in the load/store pipelines. We'll call these IntSimple.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158366 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCScheduleG5.td
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| 20b529b3f90bf17b6023ed6f8983c53c1f5be1ad |
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01-Apr-2012 |
Hal Finkel <hfinkel@anl.gov> |
Split the LdStGeneral PPC itin. class into LdStLoad and LdStStore.
Loads and stores can have different pipeline behavior, especially on
embedded chips. This change allows those differences to be expressed.
Except for the 440 scheduler, there are no functionality changes.
On the 440, the latency adjustment is only by one cycle, and so this
probably does not affect much. Nevertheless, it will make a larger
difference in the future and this removes a FIXME from the 440 itin.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153821 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCScheduleG5.td
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| 31d157ae1ac2cd9c787dc3c1d28e64c682803844 |
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18-Feb-2012 |
Jia Liu <proljc@gmail.com> |
Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150878 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCScheduleG5.td
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| 63d66eed16a6ee4e838f2f7a4c8299def0722c20 |
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29-Sep-2010 |
Evan Cheng <evan.cheng@apple.com> |
Add support to model pipeline bypass / forwarding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115005 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCScheduleG5.td
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| 928eb49cae286c95dceecf4442997dd561c6e3b7 |
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18-Apr-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
Make processor FUs unique for given itinerary. This extends the limit of 32
FU per CPU arch to 32 per intinerary allowing precise modelling of quite
complex pipelines in the future.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101754 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCScheduleG5.td
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| 4ee451de366474b9c228b4e5fa573795a715216d |
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29-Dec-2007 |
Chris Lattner <sabre@nondot.org> |
Remove attribution from file headers, per discussion on llvmdev.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45418 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCScheduleG5.td
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| 538421411a4a0a070bbd789e88657689ca504dbe |
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19-Oct-2005 |
Jim Laskey <jlaskey@mac.com> |
Added InstrSchedClass to each of the PowerPC Instructions.
Note that when adding new instructions that you should refer to the table at the
bottom of PPCSchedule.td.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23830 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCScheduleG5.td
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| 0de8796e68d49d57f4135aa40a1c72b03aa8ecca |
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19-Oct-2005 |
Jim Laskey <jlaskey@mac.com> |
Push processor descriptions to the top of target and add command line info.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23820 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCScheduleG5.td
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| 21f587ca243c2265e9b8aa81481f9085cd0e7b68 |
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18-Oct-2005 |
Jim Laskey <jlaskey@mac.com> |
Simple edits; remove unimplimented cases and clarify long haul SLU cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23788 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCScheduleG5.td
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| 076866c50f6b6c45271285eb268b585b00bed9dc |
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18-Oct-2005 |
Jim Laskey <jlaskey@mac.com> |
Checking in first round of scheduling tablegen files. Not tied in as yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23786 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCScheduleG5.td
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