4c5e43da7792f75567b693105cc53e3f1992ad98 |
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08-Apr-2015 |
Pirama Arumuga Nainar <pirama@google.com> |
Update aosp/master llvm for rebase to r233350 Change-Id: I07d935f8793ee8ec6b7da003f6483046594bca49
/external/llvm/test/CodeGen/R600/and.ll
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ebe69fe11e48d322045d5949c83283927a0d790b |
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23-Mar-2015 |
Stephen Hines <srhines@google.com> |
Update aosp/master LLVM for rebase to r230699. Change-Id: I2b5be30509658cb8266be782de0ab24f9099f9b9
/external/llvm/test/CodeGen/R600/and.ll
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37ed9c199ca639565f6ce88105f9e39e898d82d0 |
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01-Dec-2014 |
Stephen Hines <srhines@google.com> |
Update aosp/master LLVM for rebase to r222494. Change-Id: Ic787f5e0124df789bd26f3f24680f45e678eef2d
/external/llvm/test/CodeGen/R600/and.ll
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c6a4f5e819217e1e12c458aed8e7b122e23a3a58 |
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21-Jul-2014 |
Stephen Hines <srhines@google.com> |
Update LLVM for rebase to r212749. Includes a cherry-pick of: r212948 - fixes a small issue with atomic calls Change-Id: Ib97bd980b59f18142a69506400911a6009d9df18
/external/llvm/test/CodeGen/R600/and.ll
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86245071b52f1da99ac65157c38bfa5577a80714 |
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12-Nov-2013 |
Matt Arsenault <Matthew.Arsenault@amd.com> |
R600/SI: Change formatting of printed registers. Print the range of registers used with a single letter prefix. This better matches what the shader compiler produces and is overall less obnoxious than concatenating all of the subregister names together. Instead of SGPR0, it will print s0. Instead of SGPR0_SGPR1, it will print s[0:1] and so on. There doesn't appear to be a straightforward way to get the actual register info in the InstPrinter, so this parses the generated name to print with the new syntax. The required test changes are pretty nasty, and register matching regexes are now worse. Since there isn't a way to add to a variable in FileCheck, some of the tests now don't check the exact number of registers used, but I don't think that will be a real problem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194443 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/CodeGen/R600/and.ll
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39867850462b1eefd76510e25bca4f2a51f65a70 |
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10-Oct-2013 |
Tom Stellard <thomas.stellard@amd.com> |
R600/SI: Use -verify-machineinstrs for most tests We can't enable the verifier for tests with SI_IF and SI_ELSE, because these instructions are always followed by a COPY which copies their result to the next basic block. This violates the machine verifier's rule that non-terminators can not folow terminators. Reviewed-by: Vincent Lejeune<vljn at ovi.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192366 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/CodeGen/R600/and.ll
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bb25a01d232257b134f1f6a5810116cbb04b95b1 |
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04-Sep-2013 |
Vincent Lejeune <vljn@ovi.com> |
R600: Non vector only instruction can be scheduled on trans unit git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189980 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/CodeGen/R600/and.ll
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f15dfe4eb48e8e2ff02a30bc8ba9112108f9b83d |
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13-Aug-2013 |
Tom Stellard <thomas.stellard@amd.com> |
R600: Set scheduling preference to Sched::Source R600 doesn't need to do any scheduling on the SelectionDAG now that it has a very good MachineScheduler. Also, using the VLIW SelectionDAG scheduler was having a major impact on compile times. For example with the phatk kernel here are the LLVM IR to machine code compile times: With Sched::VLIW Total Compile Time: 1.4890 Seconds (User + System) SelectionDAG Instruction Scheduling: 1.1670 Seconds (User + System) With Sched::Source Total Compile Time: 0.3330 Seconds (User + System) SelectionDAG Instruction Scheduling: 0.0070 Seconds (User + System) The code ouput was identical with both schedulers. This may not be true for all programs, but it gives me confidence that there won't be much reduction, if any, in code quality by using Sched::Source. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188215 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/CodeGen/R600/and.ll
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6b3f6a744a6d16c5d62dc3477186035e8a74a8e9 |
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31-Jul-2013 |
Tom Stellard <thomas.stellard@amd.com> |
Revert "R600: Non vector only instruction can be scheduled on trans unit" This reverts commit 98ce62780ea7185ba710868bf83c8077e8d7f6d6. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187526 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/CodeGen/R600/and.ll
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98ce62780ea7185ba710868bf83c8077e8d7f6d6 |
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31-Jul-2013 |
Vincent Lejeune <vljn@ovi.com> |
R600: Non vector only instruction can be scheduled on trans unit git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187514 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/CodeGen/R600/and.ll
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e3599ca1915f56ce13139fed58f6daac1cc7ca70 |
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25-Jun-2013 |
Aaron Watry <awatry@gmail.com> |
R600/SI: Expand and of v2i32/v4i32 for SI Also add lit test for both cases on SI, and v2i32 for evergreen. Reviewed-by: Tom Stellard <thomas.stellard@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184837 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/CodeGen/R600/and.ll
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92f24d403f16ab2ee4598e32c926acc9c2344140 |
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02-May-2013 |
Vincent Lejeune <vljn@ovi.com> |
R600: Prettier asmPrint of Alu git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180956 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/CodeGen/R600/and.ll
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3abd23bac565cdb10fe6dc17e4ee0640462b5660 |
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19-Apr-2013 |
Tom Stellard <thomas.stellard@amd.com> |
R600: Reorganize lit tests and document how they should be organized git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179828 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/CodeGen/R600/and.ll
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