| 40c224a573f2b763046001e622aafca90f68c693 |
|
25-May-2012 |
Christoph Bumiller <e0425955@student.tuwien.ac.at> |
nvc0/ir: fix texture barrier insertion to prevent WAW hazards
Fixes, for instance, object highlighting in Diablo 3 (wine).
/external/mesa3d/src/gallium/drivers/nvc0/codegen/nv50_ir_emit_nvc0.cpp
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| 38a20281fcc2ed244aea0aaa268035533f48a183 |
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05-May-2012 |
Christoph Bumiller <e0425955@student.tuwien.ac.at> |
nvc0/ir: fix lowering of textureGrad
/external/mesa3d/src/gallium/drivers/nvc0/codegen/nv50_ir_emit_nvc0.cpp
|
| 1f4c154f0253ed8fb448402532cfa670f74e69cd |
|
28-Apr-2012 |
Christoph Bumiller <e0425955@student.tuwien.ac.at> |
nv50/ir/opt: try to convert ABS(SUB) to SAD
/external/mesa3d/src/gallium/drivers/nvc0/codegen/nv50_ir_emit_nvc0.cpp
|
| d6ab3106cf7475cdaddf788a3e650bdd5833f73c |
|
27-Apr-2012 |
Christoph Bumiller <e0425955@student.tuwien.ac.at> |
nvc0/ir: try to use the optimal texture op mode
Don't really know what they are yet but for groups of textures, the
last one should use mode "p" and the others "t".
/external/mesa3d/src/gallium/drivers/nvc0/codegen/nv50_ir_emit_nvc0.cpp
|
| afcd7b5d1614a8a758ccb4353a9c31a601c9b9b4 |
|
29-Apr-2012 |
Christoph Bumiller <e0425955@student.tuwien.ac.at> |
nvc0/ir: initial implementation of nve4 scheduling hints
/external/mesa3d/src/gallium/drivers/nvc0/codegen/nv50_ir_emit_nvc0.cpp
|
| d9baa004ea814bef70c8c90b342aca2ad992415c |
|
28-Apr-2012 |
Christoph Bumiller <e0425955@student.tuwien.ac.at> |
nvc0/ir/emit: fix emitTXQ 2nd src
/external/mesa3d/src/gallium/drivers/nvc0/codegen/nv50_ir_emit_nvc0.cpp
|
| e44089b2f79aa2dcaacf348911433d1e21235c0c |
|
14-Apr-2012 |
Christoph Bumiller <e0425955@student.tuwien.ac.at> |
nvc0: add initial support for nve4+ (Kepler) chipsets
Most things that work on Fermi should work on Kepler too.
There are a few performance optimizations left to do, like better
placement of texture barriers and adding scheduling data to the
shader instructions (without them, a thread group will be masked
for 32 cycles after each single instruction issue).
/external/mesa3d/src/gallium/drivers/nvc0/codegen/nv50_ir_emit_nvc0.cpp
|
| 322bc7ed68ed92233c97168c036d0aa50c11a20e |
|
14-Apr-2012 |
Christoph Bumiller <e0425955@student.tuwien.ac.at> |
nv50/ir: import nv50 target
/external/mesa3d/src/gallium/drivers/nvc0/codegen/nv50_ir_emit_nvc0.cpp
|
| e43a3a66a9d8a99021d76ff4d07dec7b8cfd62ca |
|
09-Apr-2012 |
Christoph Bumiller <e0425955@student.tuwien.ac.at> |
nv50/ir: rewrite the register allocator as GCRA, with spilling
This is more flexible than the linear scan, and we don't need the
separate allocation pass for constrained values anymore.
/external/mesa3d/src/gallium/drivers/nvc0/codegen/nv50_ir_emit_nvc0.cpp
|
| 12a2f5121d42f6f7cd94fe01f3cabe59280c62f8 |
|
05-Apr-2012 |
Christoph Bumiller <e0425955@student.tuwien.ac.at> |
nvc0: fix emission of 3rd src in SET_AND,OR,XOR
/external/mesa3d/src/gallium/drivers/nvc0/codegen/nv50_ir_emit_nvc0.cpp
|
| 9362d4bc0a03860ec386156cf499e855a9c2d2a5 |
|
09-Apr-2012 |
Christoph Bumiller <e0425955@student.tuwien.ac.at> |
nv50/ir: make Instruction::src/def container private
/external/mesa3d/src/gallium/drivers/nvc0/codegen/nv50_ir_emit_nvc0.cpp
|
| 286abcb51ec2c27970e901ed815a814b3f0bebf6 |
|
06-Apr-2012 |
Christoph Bumiller <e0425955@student.tuwien.ac.at> |
nv50/ir: add isAccessSupported check for memory access coalescing
/external/mesa3d/src/gallium/drivers/nvc0/codegen/nv50_ir_emit_nvc0.cpp
|
| 7c6ca0367bb6e9141e00fa19faabc8441dc05816 |
|
07-Jan-2012 |
Christoph Bumiller <e0425955@student.tuwien.ac.at> |
nvc0/ir/emit: fix modifiers of f32 add with long immediate
/external/mesa3d/src/gallium/drivers/nvc0/codegen/nv50_ir_emit_nvc0.cpp
|
| 9c930639d9f6d713ccfd16b390a41a9f584f348c |
|
11-Oct-2011 |
Christoph Bumiller <e0425955@student.tuwien.ac.at> |
nv50/ir: fix textureGrad with offsets and in non-FPs
/external/mesa3d/src/gallium/drivers/nvc0/codegen/nv50_ir_emit_nvc0.cpp
|
| 0e4e0ca6df52ddecd1bb2fe9a427549d1a82b9f9 |
|
17-Oct-2011 |
Christoph Bumiller <e0425955@student.tuwien.ac.at> |
nv50/ir: add wrap mode for shift operations
D3D1x specifies that only the low 5 bit of the shift are used.
/external/mesa3d/src/gallium/drivers/nvc0/codegen/nv50_ir_emit_nvc0.cpp
|
| 7920c3c192bbccdc48823b02f00d2e1b39f1a9bf |
|
06-Oct-2011 |
Christoph Bumiller <e0425955@student.tuwien.ac.at> |
nvc0/ir: fix emission of cvt when register and type size differ
/external/mesa3d/src/gallium/drivers/nvc0/codegen/nv50_ir_emit_nvc0.cpp
|
| c43b2f6a30dc9d42cb3b19c9396002b6c18a493e |
|
13-Oct-2011 |
Christoph Bumiller <e0425955@student.tuwien.ac.at> |
nvc0/ir: handle levelZero modifier in TEX emission
/external/mesa3d/src/gallium/drivers/nvc0/codegen/nv50_ir_emit_nvc0.cpp
|
| d2d19ea51fa3575a8d014a69a9b835c335728817 |
|
14-Sep-2011 |
Christoph Bumiller <e0425955@student.tuwien.ac.at> |
nv50/ir: add missing license headers
/external/mesa3d/src/gallium/drivers/nvc0/codegen/nv50_ir_emit_nvc0.cpp
|
| 57594065c30feec9376be9b2132659f7d87362ee |
|
14-Sep-2011 |
Christoph Bumiller <e0425955@student.tuwien.ac.at> |
nv50/ir: import new shader backend code
/external/mesa3d/src/gallium/drivers/nvc0/codegen/nv50_ir_emit_nvc0.cpp
|