a56a732c6991f47d63f5ccbb27a45467541c43f8 |
|
08-Jan-2012 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Correct _NEW_TRANSOFORM typos. Using the proper spelling, _NEW_TRANSFORM, makes searching work better. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_clip_state.c
|
c4aaf85285fc9484e95e9cda89db9cc6923259f4 |
|
22-Oct-2011 |
Eric Anholt <eric@anholt.net> |
i965/gen4: Move unit state setup to emit() time. It is only needed in time for brw_psp_urb_cbs(), which is also an emit(). Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Acked-by: Paul Berry <stereotype441@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_clip_state.c
|
47f1d9deffee8aeb2d73d8e06f829d32125f944c |
|
24-Oct-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Remove "single threaded" INTEL_DEBUG mode. According to the docs for 3DSTATE_PS (Gen7+) and 3DSTATE_WM (Gen6), there is a platform dependent value for the minimum number of pixel shader threads. It may also vary based on whether WIZ Hashing is on. For example, Ivybridge requires at least 4 threads if WIZ hashing is disabled, and 8 if it's enabled. Programming it to use less threads is illegal. Sandybridge appears to have similar restrictions. So on newer platforms, INTEL_DEBUG=sing will probably just hang the GPU. Rather than try to patch it up for newer platforms and extend it to support geometry shaders, just remove it as it isn't that useful anyway. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_clip_state.c
|
d375df220fae47f38944c4832bcbd5f5d568884c |
|
23-Jun-2011 |
Eric Anholt <eric@anholt.net> |
i965: Add a type argument to brw_state_batch(). I want to make brw_state_dump.c handle more than just the last statechange, so I want to keep track of what's in the batch state. By using AUB file numbering for most of these packets, this may be reusable for aub dumping. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_clip_state.c
|
c173541d9769d41a85cc899bc49699a3587df4bf |
|
27-Apr-2011 |
Eric Anholt <eric@anholt.net> |
i965: Use state streaming on programs, and state base address on gen5+. There will be a little bit of thrashing of the program cache BO as the cache warms up, but once the application is in steady state, this reduces relocations on gen5 and later. On my T420 laptop, cairogl firefox-talos-gfx performance improves 2.6% +/- 1.3% (n=6). No statistically significant performance difference on nexuiz (n=5).
/external/mesa3d/src/mesa/drivers/dri/i965/brw_clip_state.c
|
8ba0c025a4e0aba97ae596e2121416cf04c0c300 |
|
25-Apr-2011 |
Eric Anholt <eric@anholt.net> |
i965/gen4: Move clip state to state streaming Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_clip_state.c
|
bb1540835056cdea5db6f55b19c0c87358f14cd1 |
|
03-Nov-2010 |
Eric Anholt <eric@anholt.net> |
intel: Annotate debug printout checks with unlikely(). This provides the optimizer with hints about code hotness, which we're quite certain about for debug printouts (or, rather, while we developers often hit the checks for debug printouts, we don't care about performance while doing so).
/external/mesa3d/src/mesa/drivers/dri/i965/brw_clip_state.c
|
f9995b30756140724f41daf963fa06167912be7f |
|
12-Oct-2010 |
Kristian Høgsberg <krh@bitplanet.net> |
Drop GLcontext typedef and use struct gl_context instead
/external/mesa3d/src/mesa/drivers/dri/i965/brw_clip_state.c
|
df3c1a563f3d76b07ab82c7b230b0030452f36ff |
|
07-Jun-2010 |
Eric Anholt <eric@anholt.net> |
intel: Convert remaining dri_bo_emit_reloc to drm_intel_bo_emit_reloc. The new API makes so much more sense, I'd like to forget how the old one worked.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_clip_state.c
|
34474fa4119378ef9fbb9fb557cc19c0a1ca1f7e |
|
07-Jun-2010 |
Eric Anholt <eric@anholt.net> |
intel: Change dri_bo_* to drm_intel_bo* to consistently use new API. The slightly less mechanical change of converting the emit_reloc calls will follow.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_clip_state.c
|
cdcef6cbf4dd80047819e9098e34a3b98bd502a4 |
|
19-Apr-2010 |
Zhenyu Wang <zhenyuw@linux.intel.com> |
intel: Clean up chipset name and gen num for Ironlake Rename old IGDNG to Ironlake, and set 'gen' number for Ironlake as 5, so tracking the features with generation num instead of special is_ironlake flag. Reviewed-by: Eric Anholt <eric@anholt.net> Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_clip_state.c
|
9b22427911ad27efc1f36faee9462c6082d0417c |
|
25-Jan-2010 |
Brian Paul <brianp@vmware.com> |
Merge branch 'mesa_7_7_branch' Conflicts: src/mesa/drivers/dri/intel/intel_screen.c src/mesa/drivers/dri/intel/intel_swapbuffers.c src/mesa/drivers/dri/r300/r300_emit.c src/mesa/drivers/dri/r300/r300_ioctl.c src/mesa/drivers/dri/r300/r300_tex.c src/mesa/drivers/dri/r300/r300_texstate.c
|
634ec5c2abf05a9a8c27d9199ded5d1ad91e538a |
|
23-Jan-2010 |
Vinson Lee <vlee@vmware.com> |
i965: Remove unnecessary headers.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_clip_state.c
|
62a96f74c9a1fd07301d349e4181a7212fc7d45c |
|
18-Jan-2010 |
Eric Anholt <eric@anholt.net> |
i965: Allow for variable-sized auxdata in the state cache. Everything has been constant-sized until now, but constant buffer handling changes will make us want some additional variable sized array.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_clip_state.c
|
0b87f143c466f7e5bd730895ee29f1cd20a68f9b |
|
17-Dec-2009 |
Eric Anholt <eric@anholt.net> |
intel: Replace IS_G4X() across the driver with context structure usage. Saves ~2KB of code.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_clip_state.c
|
1c96e85c9d6b8c636b0636f3320d1057ab5357b3 |
|
16-Dec-2009 |
Eric Anholt <eric@anholt.net> |
intel: Replace IS_IGDNG checks with intel->is_ironlake or needs_ff_sync. Saves ~480 bytes of code.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_clip_state.c
|
0310aafd9ea502e07a86b355cfca902102b9117c |
|
26-Aug-2009 |
Eric Anholt <eric@anholt.net> |
i965: Add support for ARB_depth_clamp.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_clip_state.c
|
2995bf0d68f1b28ba68b81e9dc79e3ab52bc2795 |
|
13-Jul-2009 |
Xiang, Haihao <haihao.xiang@intel.com> |
i965: add support for new chipsets 1. new PCI ids 2. fix some 3D commands on new chipset 3. fix send instruction on new chipset 4. new VUE vertex header 5. ff_sync message (added by Zou Nan Hai <nanhai.zou@intel.com>) 6. the offset in JMPI is in unit of 64bits on new chipset 7. new cube map layout
/external/mesa3d/src/mesa/drivers/dri/i965/brw_clip_state.c
|
82eb7c235db9939d067c4d64e32df96caef939ab |
|
03-Nov-2008 |
Eric Anholt <eric@anholt.net> |
i965: Fix up clip min_nr_entries, preferred_nr_entries, and max_threads. The clip thread could potentially deadlock when processing tristrips since being moved back to dual-thread mode, as the two threads could each have 4 VUEs referenced and not be able to allocate another one since SF processing wasn't able to continue (needing 5 entries before it freed 2). In constrained URB mode, similar deadlock could even have occurred with polygons (so we cut back max_threads if we can't handle it any primitive type).
/external/mesa3d/src/mesa/drivers/dri/i965/brw_clip_state.c
|
34b1776e8d965605d12807884c9c447214d57281 |
|
02-Nov-2008 |
Eric Anholt <eric@anholt.net> |
i965: Merge GM45 into the G4X chipset define. The mobile and desktop chipsets are the same, and having them separate is more typing and more chances to screw up.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_clip_state.c
|
ecadb51bbcb972a79f3ed79e65a7986b9396e757 |
|
18-Sep-2008 |
Brian Paul <brian.paul@tungstengraphics.com> |
mesa: added "main/" prefix to includes, remove some -I paths from Makefile.template
/external/mesa3d/src/mesa/drivers/dri/i965/brw_clip_state.c
|
3628185f566e178a12b493fb89abf52b4b281f99 |
|
06-Sep-2008 |
Eric Anholt <eric@anholt.net> |
intel: track bufmgr move to libdrm_intel and bufmgr_fake irq emit/wait change.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_clip_state.c
|
f75843a517bd188639e6866db2a7b04de3524e16 |
|
24-Aug-2008 |
Dave Airlie <airlied@linux.ie> |
Revert "Revert "Merge branch 'drm-gem'"" This reverts commit 7c81124d7c4a4d1da9f48cbf7e82ab1a3a970a7a.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_clip_state.c
|
7c81124d7c4a4d1da9f48cbf7e82ab1a3a970a7a |
|
24-Aug-2008 |
Dave Airlie <airlied@linux.ie> |
Revert "Merge branch 'drm-gem'" This reverts commit 53675e5c05c0598b7ea206d5c27dbcae786a2c03. Conflicts: src/mesa/drivers/dri/i965/brw_wm_surface_state.c
/external/mesa3d/src/mesa/drivers/dri/i965/brw_clip_state.c
|
d2796939f18815935c8fe1effb01fa9765d6c7d8 |
|
08-Aug-2008 |
Eric Anholt <eric@anholt.net> |
intel-gem: Update to new check_aperture API for classic mode. To do this, I had to clean up some of 965 state upload stuff. We may end up over-emitting state in the aperture overflow case, but that should be rare, and I'd rather have the simplification of state management.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_clip_state.c
|
1e645b365900cf1c71ca5594bd6b549a1f203040 |
|
26-Jul-2008 |
Ian Romanick <ian.d.romanick@intel.com> |
Merge branch 'master' into drm-gem Conflicts: src/mesa/drivers/dri/common/dri_bufmgr.c src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
92c075eeb7c330ea420400d1c2bae57356b19f03 |
|
08-Jul-2008 |
Xiang, Haihao <haihao.xiang@intel.com> |
i965: official name for GM45 chipset
/external/mesa3d/src/mesa/drivers/dri/i965/brw_clip_state.c
|
407ce3da3c53c9ebba0fbf827d7b0f610122d44b |
|
11-Jun-2008 |
Eric Anholt <eric@anholt.net> |
[intel-gem] Chase domain flag renaming in the DRM. This is an API breakage only.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_clip_state.c
|
4b5b008d54e86ac4f0a2176429d062100978ca8c |
|
03-Jun-2008 |
Eric Anholt <eric@anholt.net> |
[intel] Convert drivers to using libdrm bufmgr code.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_clip_state.c
|
ab50ddaa9173ae108833db0edb209045788efc41 |
|
07-May-2008 |
Eric Anholt <eric@anholt.net> |
GEM: Make dri_emit_reloc take GEM domain flags instead of TTM flags. The GEM flags are much more descriptive for what we need. Since this makes bufmgr_fake rather device-specific, move it to the intel common directory. We've wanted to do device-specific stuff to it before.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_clip_state.c
|
008653ac55776d6b1c6d1627ad20937aa1c4dbda |
|
17-Apr-2008 |
Dave Airlie <airlied@redhat.com> |
i965: initial attempt at fixing the aperture overflow Makes state emission into a 2 phase, prepare sets things up and accounts the size of all referenced buffer objects. The emit stage then actually does the batchbuffer touching for emitting the objects. There is an assert in dri_emit_reloc if a reloc occurs for a buffer that hasn't been accounted yet.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_clip_state.c
|
8e444fb9e2685e3eac42beb848b08e91dc20c88a |
|
29-Jan-2008 |
Xiang, Haihao <haihao.xiang@intel.com> |
i965: new integrated graphics chipset support
/external/mesa3d/src/mesa/drivers/dri/i965/brw_clip_state.c
|
faeb1bc9f9c5935ecbd32c17d81507d5061a6270 |
|
17-Jan-2008 |
Eric Anholt <eric@anholt.net> |
[965] Fix whitespace in c9b1fef0c9c5018efd825c42782f19ad0618696a
/external/mesa3d/src/mesa/drivers/dri/i965/brw_clip_state.c
|
c9b1fef0c9c5018efd825c42782f19ad0618696a |
|
17-Jan-2008 |
Xiang, Haihao <haihao.xiang@intel.com> |
i965: always call dri_emit_reloc when creating clip unit state This fix ensures it gets the starting location of the clip program if a clip unit state is same as a unit which is created when metaops is actived and it doesn't impact metaops because the clip state offset isn't emitted when metaops is actived.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_clip_state.c
|
8abffada70fcd62e3c2dcbcdc6d00d258805326b |
|
03-Jan-2008 |
Eric Anholt <eric@anholt.net> |
[intel] Convert relocations to not be cleared out on buffer submit. We have two consumers of relocations. One is static state buffers, which want the same relocation every time. The other is the batchbuffer, which gets thrown out immediately after submit. This lets us reduce repeated computation for static state buffers, and clean up the code by moving relocations nearer to where the state buffer is computed.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_clip_state.c
|
114b802e87bca5edbc2c59fc2c5caad3ec90bca6 |
|
02-Jan-2008 |
Eric Anholt <eric@anholt.net> |
[965] Convert clip unit to use a cache key instead of brw_cache_data.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_clip_state.c
|
38bad7677e57d629eeffd4ef39a7fc254db12735 |
|
14-Dec-2007 |
Eric Anholt <eric@anholt.net> |
[965] Replace the state cache suballocator with direct dri_bufmgr use. The user-space suballocator that was used avoided relocation computations by using the general and surface state base registers and allocating those types of buffers out of pools built on top of single buffer objects. It also avoided calls into the buffer manager for these small state allocations, since only one buffer object was being used. However, the buffer allocation cost appears to be low, and with relocation caching, computing relocations for buffers is essentially free. Additionally, implementing the suballocator required a don't-fence-subdata flag to disable waiting on buffer maps so that writing new data didn't block on rendering using old data, and careful handling when mapping to update old data (which we need to do for unavoidable relocations with FBOs). More importantly, when the suballocator filled, it had no replacement algorithm and just threw out all of the contents and forced them to be recomputed, which is a significant cost. This is the first step, which just changes the buffer type, but doesn't yet improve the hash table to not result in full recompute on overflow. Because the buffers are all allocated out of the general buffer allocator, we can no longer use the general/surface state bases to avoid relocations, and they are set to 0 instead.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_clip_state.c
|
77e0523fb7769df4bf43747e136b1653b2421b97 |
|
04-Oct-2007 |
Eric Anholt <eric@anholt.net> |
[965] Replace various alignment code with a shared ALIGN() macro. In the process, fix some alignment issues: - Scratch space allocation was aligned into units of 1KB, while the allocation wanted units of bytes, so we never allocated enough space for scratch. - GRF register count was programmed as ALIGN(val - 1, 16) / 16 instead of ALIGN(val, 16) / 16 - 1, which overcounted for val != 16n+1.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_clip_state.c
|
b47c9f8c915ae4ca8c7fa5ee3b6b64f17c38b569 |
|
31-Aug-2007 |
Zou Nan hai <nanhai.zou@intel.com> |
optimize 965 clip 1. increase clip thread number to 2 2. do cliptest for -rhw
/external/mesa3d/src/mesa/drivers/dri/i965/brw_clip_state.c
|
16a22a5f4a9e0497164ef0fddcb4fe9ba1f6756e |
|
12-Sep-2006 |
Keith Whitwell <keith@tungstengraphics.com> |
Potential fix for doom3 lockups. Seems that there is a conflict between the vertex cache, the vertex shader and the clipping stages, all of which are competitors for URB entries assigned to the VS unit. This change reduces the maximum number of clip and VS threads by enough to ensure that they cannot consume all the available URB entries, and then reduces the number somewhat more up to an arbitary amount I discovered by trial and error. Unfortunately trial and error solutions don't inspire total confidence...
/external/mesa3d/src/mesa/drivers/dri/i965/brw_clip_state.c
|
9f344b3e7d6e23674dd4747faec253f103563b36 |
|
09-Aug-2006 |
Eric Anholt <anholt@FreeBSD.org> |
Add Intel i965G/Q DRI driver. This driver comes from Tungsten Graphics, with a few further modifications by Intel.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_clip_state.c
|