| 993c52d0be5bdf0e30e64ab4c6e1347c5dcb8e3b |
|
27-Aug-2012 |
Eric Anholt <eric@anholt.net> |
i965: Replace general sw fallback support with a manual check for rendermode.
There were no other cases that set it any more.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw.c
|
| 88edbdf9f0c79e05593a71929f791fa4efb08ffb |
|
14-Aug-2012 |
Chad Versace <chad.versace@linux.intel.com> |
i965: Move hiz resolve to after renderbuffer resizing (v2)
Do all pre-draw hiz resolves *after* the renderbuffers are resized by
intel_prepare_render. Otherwise, we may resolve buffers that are
immediately discarded afterwards.
Fixes the assertion failure below when resizing windows in KDE and under
some unknown circumstance in Chrome OS:
intel_resolve_map.c:46: intel_resolve_map_set: Assertion
`(*tail)->need == need' failed.
Also, remove the comment that "resolves must occur [...] before setting up
any hardware state". That was true when resolves were implemented with
meta-ops, but no longer with blorp.
v2:
- Keep brw_predraw_resolve_buffers in its current position, which is
before any brw_context bits are modified. Instead, move the call to
intel_prepare_render.
Note: This is a candiate for the 8.0 branch.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=52252
Reported-by: Lu Hua <huax.lu@intel.com>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw.c
|
| a2a7e640a4e81c906e42a98602c84757c37ed0b1 |
|
14-Aug-2012 |
Chad Versace <chad.versace@linux.intel.com> |
i965: Remove redundant null check
intel_renderbuffer_resolve_hiz checks if rb->mt is null, so there is no
need for the caller to do so.
Reviewed-by: Paul Berry <stereotype441@gmail.com>
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw.c
|
| 6b56140b4bafcef8bea5ca67cb31023a533c3bd4 |
|
27-Jul-2012 |
Chad Versace <chad.versace@linux.intel.com> |
i965: Mark needed downsamples for msaa winsys buffers
Add function intel_renderbuffer_set_needs_downsample. It is a no-op
except on multisample winsys buffers shared with DRI2.
Mark the needed downsamples with the new function at two locations:
- Immediately after drawing is complete.
- After blitting.
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw.c
|
| 3588098ed85bbd6bacac5a8dd3774569f1314783 |
|
27-May-2012 |
Jordan Justen <jordan.l.justen@intel.com> |
i965: enable ARB_instanced_arrays extension
Set the step_rate value when drawing to implement
ARB_instanced_arrays for gen >= 4.
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw.c
|
| df7d1323de08274c816a8e5fab7e99b6f00f4fa3 |
|
13-May-2012 |
Jordan Justen <jordan.l.justen@intel.com> |
i965: create code path to handle primitive restart in hardware
For newer hardware we disable the VBO module's software handling
of primitive restart. We now handle primitive restarts in
brw_handle_primitive_restart.
The initial version of brw_handle_primitive_restart simply calls
vbo_sw_primitive_restart, and therefore still uses the VBO
module software primitive restart support.
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw.c
|
| 50f7e75f9e945cfbb2ae868cc961a2205a0b6e73 |
|
23-Apr-2012 |
Marek Olšák <maraeo@gmail.com> |
mesa: move gl_client_array*[] from vbo_draw_func into gl_context
In the future we'd like to treat vertex arrays as a state and
not as a parameter to the draw function. This is the first step
towards that goal. Part of the goal is to avoid array re-validation
for every draw call.
This commit adds:
const struct gl_client_array **gl_context::Array::_DrawArrays.
The pointer is changed in:
* vbo_draw_method
* vbo_rebase_prims - unused by gallium
* vbo_split_prims - unused by gallium
* st_RasterPos
Reviewed-by: Brian Paul <brianp@vmware.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw.c
|
| e9bcdc2c37501dc6c7dce8960ec74ccb9f8b09e8 |
|
09-Feb-2012 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Enable the GL_ARB_draw_instanced extension.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw.c
|
| 7b36c68ba6899c7f30fd56b7ef07a78b027771ac |
|
26-Jan-2012 |
Chad Versace <chad.versace@linux.intel.com> |
i965: Rewrite the HiZ op
The HiZ op was implemented as a meta-op. This patch reimplements it by
emitting a special HiZ batch. This fixes several known bugs, and likely
a lot of undiscovered ones too.
==== Why the HiZ meta-op needed to die ====
The HiZ op was implemented as a meta-op, which caused lots of trouble. All
other meta-ops occur as a result of some GL call (for example, glClear and
glGenerateMipmap), but the HiZ meta-op was special. It was called in
places that Mesa (in particular, the vbo and swrast modules) did not
expect---and were not prepared for---state changes to occur (for example:
glDraw; glCallList; within glBegin/End blocks; and within
swrast_prepare_render as a result of intel_miptree_map).
In an attempt to work around these unexpected state changes, I added two
hooks in i965:
- A hook for glDraw, located in brw_predraw_resolve_buffers (which is
called in the glDraw path). This hook detected if a predraw resolve
meta-op had occurred, and would hackishly repropagate some GL state
if necessary. This ensured that the meta-op state changes would not
intefere with the vbo module's subsequent execution of glDraw.
- A hook for glBegin, implemented by brwPrepareExecBegin. This hook
resolved all buffers before entering
a glBegin/End block, thus preventing an infinitely recurring call to
vbo_exec_FlushVertices. The vbo module calls vbo_exec_FlushVertices to
flush its vertex queue in response to GL state changes.
Unfortunately, these hooks were not sufficient. The meta-op state changes
still interacted badly with glPopAttrib (as discovered in bug 44927) and
with swrast rendering (as discovered by debugging gen6's swrast fallback
for glBitmap). I expect there are more undiscovered bugs. Rather than play
whack-a-mole in a minefield, the sane approach is to replace the HiZ
meta-op with something safer.
==== How it was killed ====
This patch consists of several logical components:
1. Rewrite the HiZ op by replacing function gen6_resolve_slice with
gen6_hiz_exec and gen7_hiz_exec. The new functions do not call
a meta-op, but instead manually construct and emit a batch to "draw"
the HiZ op's rectangle primitive. The new functions alter no GL
state.
2. Add fields to brw_context::hiz for the new HiZ op.
3. Emit a workaround flush when toggling 3DSTATE_VS.VsFunctionEnable.
4. Kill all dead HiZ code:
- the function gen6_resolve_slice
- the dirty flag BRW_NEW_HIZ
- the dead fields in brw_context::hiz
- the state packet manipulation triggered by the now removed
brw_context::hiz::op
- the meta-op workaround in brw_predraw_resolve_buffers (discussed
above)
- the meta-op workaround brwPrepareExecBegin (discussed above)
Note: This is a candidate for the 8.0 branch.
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Paul Berry <stereotype441@gmail.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=43327
Reported-by: xunx.fang@intel.com
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=44927
Reported-by: chao.a.chen@intel.com
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw.c
|
| 42d4972bf0b147b0241c2be7e6579fd64cf2c216 |
|
31-Dec-2011 |
Yuanhan Liu <yuanhan.liu@linux.intel.com> |
vbo: introduce vbo_get_minmax_indices function
Introduce vbo_get_minmax_indices() function to handle the min/max index
computation for nr_prims(>= 1). The old code just compute the first
prim's min/max index; this would results an error rendering if user
called functions like glMultiDrawElements(). This patch servers as
fixing this issue.
As when nr_prims = 1, we can pass 1 to paramter nr_prims, thus I made
vbo_get_minmax_index() static.
v2: per Roland's suggestion, put the indices address compuation into
vbo_get_minmax_index() instead.
Also do comination if possible to reduce map/unmap count
v3: per Brian's suggestion, use a pointer for start_prim to avoid
structure copy per loop.
Signed-off-by: Yuanhan Liu <yuanhan.liu@linux.intel.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw.c
|
| 43e0d775973446e84621fdb56af85f0027ed579c |
|
22-Dec-2011 |
Eric Anholt <eric@anholt.net> |
i965/gen7: Make primitives_written counting work.
The code was relying on gs.prog_data's copy of the
number-of-verts-per-prim, which segfaulted on gen7 since it doesn't
make a GS program. We can easily calculate that value right here.
v2: Fix svbi_0_starting_index regression.
Reviewed-by: Paul Berry <stereotype441@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw.c
|
| 772d4fef42d79c5efb3a7eb255ff0e1fdb88ada3 |
|
21-Dec-2011 |
Paul Berry <stereotype441@gmail.com> |
i965 gen6: Implement transform feedback pause/resume functionality.
Although i965 gen6 does not yet support ARB_transform_feedback2 or
NV_transform_feedback2, it needs to support pause/resume functionality
so that meta-ops will work correctly.
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw.c
|
| c59393b7069f59ca2a13bfb6500f2a5360c38031 |
|
15-Dec-2011 |
Paul Berry <stereotype441@gmail.com> |
i965 gen6: Implement transform feedback queries.
This patch adds software-based PRIMITIVES_GENERATED and
TRANSFORM_FEEDBACK_PRIMITIVES_WRITTEN queries that work by keeping
track of the number of primitives that are sent down the pipeline, and
adjusting as necessary to account for the way each primitive type is
tessellated.
In the long run we'll want to replace this with a hardware-based
implementation, because the software approach won't work with geometry
shaders or primitive restart. However, at the moment, we don't have
the necessary kernel support to implement a hardware-based query (we
would need the kernel to save GPU registers when context switching, so
that drawing performed by another process doesn't get counted).
Fixes Piglit tests EXT_transform_feedback/query-primitives_generated-*
and EXT_transform_feedback/query-primitives-written-*.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw.c
|
| f8328c998b4d68c62ba939165390c2c22c5b5740 |
|
19-Dec-2011 |
Paul Berry <stereotype441@gmail.com> |
i965 gen6: Ensure correct transform feedback indices on new batch.
We don't currently have kernel support for saving GPU registers on a
context switch, so if multiple processes are performing transform
feedback at the same time, their SVBI registers will interfere with
each other. To avoid this situation, we keep a software shadow of the
state of the SVBI 0 register (which is the only register we use), and
re-upload it on every new batch.
The function that updates the shadow state of SVBI 0 is called
brw_update_primitive_count, since it will also be used to update the
counters for the PRIMITIVES_GENERATED and
TRANSFORM_FEEDBACK_PRIMITIVES_WRITTEN queries.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw.c
|
| 14bb957b996dcc5392b8fa589bd3ffa5c55cb6b4 |
|
09-Dec-2011 |
Marek Olšák <maraeo@gmail.com> |
mesa: implement DrawTransformFeedback from ARB_transform_feedback2
It's like DrawArrays, but the count is taken from a transform feedback
object.
This removes DrawTransformFeedback from dd_function_table and adds the same
function to GLvertexformat (with the function parameters matching GL).
The vbo_draw_func callback has a new parameter
"struct gl_transform_feedback_object *tfb_vertcount".
The rest of the code just validates states and forwards the transform
feedback object into vbo_draw_func.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw.c
|
| 1b2baf3b08d545c772e9636fb0a0614c489c3916 |
|
16-Nov-2011 |
Chad Versace <chad.versace@linux.intel.com> |
i965: Mark that depth buffer needs depth resolve after drawing
After brw_try_draw_prims() emits a batch, mark that the depth buffer needs
a depth resolve if the buffer was written to and if it has an accompanying
HiZ buffer.
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw.c
|
| 3b0d295e122f8ca6e0ebe4593a1e0660308a18c3 |
|
16-Nov-2011 |
Chad Versace <chad.versace@linux.intel.com> |
i965: Resolve buffers before drawing [v2]
Before emitting primitives in brw_try_draw_prims(), resolve the depth
buffer's HiZ buffer and resolve the depth buffer of each enabled depth
texture.
v2: [anholt] The driver no longer validates drm bo's, so update a comment
to reflect that.
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw.c
|
| 12498553462c7807034814cf843d86d52c407380 |
|
16-Nov-2011 |
Chad Versace <chad.versace@linux.intel.com> |
i965/gen6: Manipulate state batches for HiZ meta-ops [v4]
A lot of the state manipulation is handled by the meta-op state setup.
However, some batches need manual intervention.
v2:
Do not special-case the 3DSTATE_DEPTH_STENCIL.Depth_Test_Enable bit
for HiZ in gen6_upload_depth_stencil(). The HiZ meta-op sets
ctx->Depth.Test, just read the value from that.
v3:
Add a new dirty flag, BRW_STATE_HIZ, for brw_tracked_state. Flag it
immediately before and after executing the HiZ operation in
gen6_resolve_slice(). Add the flag to the the dirty bits for the
following state packets:
gen6_clip_state
gen6_depth_stencil_state
gen6_sf_state
gen6_wm_state
v4:
- Add BRW_NEW_STATE_HIZ to the dirty bit table in brw_state_upload.c.
This is needed for INTEL_DEBUG=state.
- Align brw dirty bit for gen6_depth_stencil_state.
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw.c
|
| 35c7e8cebeaae67c80254224cda46ee17f6d5868 |
|
22-Oct-2011 |
Eric Anholt <eric@anholt.net> |
i965: Merge brw_validate_state() and brw_upload_state() together.
They were called back-to-back at this point.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Paul Berry <stereotype441@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw.c
|
| 78188bc53769384fdeb8d7618af882c86530a4d5 |
|
22-Oct-2011 |
Eric Anholt <eric@anholt.net> |
i965: Check Fallback again after upload.
As we move state to emit() time from prepare() time, a couple of the
places that flag fallbacks will move here.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Paul Berry <stereotype441@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw.c
|
| 3d851ae48865ac6a20a615e6e06d913c2265cda5 |
|
22-Oct-2011 |
Eric Anholt <eric@anholt.net> |
i965: Use the batch save/reset code to avoid needing the BO validate step.
We were doing the BO validate step in prepare() (brw_validate_state())
hooks of atoms so that we could check_aperture before emitting the
relocation trees during brw_upload_state() that would actually make
the batchbuffer reference too much memory to be executed. Now that
all relocations occur in the batchbuffer, we can instead
check_aperture after emitting our state into the batchbuffer, and
easily roll back, flush, and retry if we happened to go over the
limits.
This will let us remove the whole prepare() vs emit() split in our
state atoms, which is a source of tricky dependencies and duplicated
code.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Paul Berry <stereotype441@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw.c
|
| fff693828ed5398ae284fb01c129d0f8986a126e |
|
22-Oct-2011 |
Eric Anholt <eric@anholt.net> |
i965: Add a note about an unsafe-looking state check.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Paul Berry <stereotype441@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw.c
|
| 2e5a1a254ed81b1d3efa6064f48183eefac784d0 |
|
07-Oct-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
intel: Convert from GLboolean to 'bool' from stdbool.h.
I initially produced the patch using this bash command:
for file in {intel,i915,i965}/*.{c,cpp,h}; do [ ! -h $file ] && sed -i
's/GLboolean/bool/g' $file && sed -i 's/GL_TRUE/true/g' $file && sed -i
's/GL_FALSE/false/g' $file; done
Then I manually added #include <stdbool.h> to fix compilation errors,
and converted a few functions back to GLboolean that were used in core
Mesa's function pointer table to avoid "incompatible pointer" warnings.
Finally, I cleaned up some whitespace issues introduced by the change.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Chad Versace <chad@chad-versace.us>
Acked-by: Paul Berry <stereotype441@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw.c
|
| f378e8fea0e6bfda2018ee14a99757bde329e0a7 |
|
27-Sep-2011 |
Chad Versace <chad@chad-versace.us> |
i965: Change type of brw_context.primitive from GLenum to hardware primitive
For example, GL_TRIANLGES is converted to _3DPRIM_TRILIST.
The conversion is necessary because HiZ and MSAA resolve operations emit
a 3DPRIM_RECTLIST, which cannot be conveyed by GLenum.
As a consequence, brw_gs_prog_key.primitive is also converted.
v2
----
- [anholt] Split brw_set_prim into brw/gen6 variants in previous commit,
since not much code is really shared between the two.
- [anholt] Replace switch statements with table lookups, since this is
a hot path.
Reviewed-by: Eric Anholt <eric@anho.net>
Signed-off-by: Chad Versace <chad@chad-versace.us>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw.c
|
| 9559ca600dde0877fe0abd04dd789bd5a3cdfbde |
|
27-Sep-2011 |
Chad Versace <chad@chad-versace.us> |
i965: Split brw_set_prim into brw/gen6 variants
The "slight optimization to avoid the GS program" in brw_set_prim() is not
used by Gen 6, since Gen 6 doesn't use a GS program. Also, Gen 6 doesn't use
reduced primitives.
Also, document that intel_context.reduced_primitive is only used for Gen < 6
Reviewed-by: Eric Anholt <eric@anho.net>
Signed-off-by: Chad Versace <chad@chad-versace.us>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw.c
|
| 6cf3d1cace770a3b4a0bff0d44db3b9e1da4cb09 |
|
22-Jun-2011 |
Eric Anholt <eric@anholt.net> |
i965: Don't bother telling tnl about state updates unless we fall back.
This was sucking up 1% of the CPU on 3DMMES.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw.c
|
| 0ab7d6f437f2f7a1b2d84f30497f3c2013b52791 |
|
18-Jun-2011 |
Eric Anholt <eric@anholt.net> |
i965/gen6: Limit the workaround flush to once per primitive.
We're about to call this function in a bunch of state emits, so let's
not spam the hardware with flushes too hard.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw.c
|
| 836a595594a5500945c5d97d6f63c245ebbe34a8 |
|
25-May-2011 |
Eric Anholt <eric@anholt.net> |
i965: Drop remaining strict conformance fallback for GL_POINT_SMOOTH.
We actually could do this in hardware in the fragment shader using
gl_PointCoord and the point's size.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw.c
|
| e9868979c5373501234392a38a786d5a92dc47b5 |
|
25-May-2011 |
Eric Anholt <eric@anholt.net> |
i965: Drop strict conformance fallback for GL_LINE_STIPPLE.
We implement line stipples, just not *quite* correctly. We have a
piglit testcase to use when we want to fix it, if we do. Until then,
don't lie to our test suites.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw.c
|
| d313346db6b70d27ed985e27df4fbd44f376efa0 |
|
25-May-2011 |
Eric Anholt <eric@anholt.net> |
i965: Drop strict conformance fallback for GL_LINE_SMOOTH.
We do have hardware antialised lines. If we care, we should actually
fix them to be conformant (or as close as possible) instead of using
this knob to fool testcases using swrast.
For some interesting reading on the state of GL_*_SMOOTH across
several drivers, see:
http://homepage.mac.com/arekkusu/bugs/invariance/HWAA.html
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw.c
|
| d8b733643d21001068c25ee9b97a3cd5bb4684a2 |
|
25-May-2011 |
Eric Anholt <eric@anholt.net> |
i965: Drop strict conformance fallback for GL_POLYGON_SMOOTH.
From my reading of the GL 2.1 spec, no antialiasing is strictly
conformant for polygon smoothing. Yes, it's absurd, but then,
hardware doesn't support this so maybe it's not so absurd.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw.c
|
| 3f05374574db7d04ac920a93545734c9013f5ec4 |
|
25-May-2011 |
Eric Anholt <eric@anholt.net> |
i965: Drop INTEL_CONFORMANCE=2 fallback code.
This was just a duplicate of no_rast=true driconf option, which is
relatively standard across drivers.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw.c
|
| b126a0c0cb30b1e2f2df1953fe14d8596d1cf4f7 |
|
02-Nov-2010 |
Eric Anholt <eric@anholt.net> |
i965: Add support for correct GL_CLAMP behavior by clamping coordinates.
This removes the stupid strict-conformance fallback code I broke when
adding ARB_sampler_objects.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=36572
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> (v1)
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw.c
|
| 550ad737f77cfae9abf2db1638711713ad9d920e |
|
12-Apr-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Emit 3DPRIMITIVE Ivybridge-style.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw.c
|
| 5c742ea1ee0cea031cb99651155d0c7521f42b4e |
|
23-Apr-2011 |
Eric Anholt <eric@anholt.net> |
i965: Move sampler state to state streaming.
Overall, across this series since the last set of numbers, gen6 3DMMES
taiji performance has dropped 0.8% +/- 0.3% (n=15), probably due to
the increased reissuing of state from some of the state objects that
otherwise never changed, and increased occurrence of the per-batch
overhead as we've increased how much we put in the batch BO without
increasing the batch BO's size.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw.c
|
| 32cc0c9d8de343f699e80e7e416ea0d7e3121a42 |
|
22-Apr-2011 |
Eric Anholt <eric@anholt.net> |
i965/gen6: Stream the VS push constants.
Improves 3DMMES taiji demo performance by 10.1% +/- 0.9% (n=15).
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw.c
|
| 90c70123b830bead0ac622df94f2809ac056af95 |
|
22-Apr-2011 |
Eric Anholt <eric@anholt.net> |
i965/gen6: Stream the WM push constants.
Improves 3DMMES taiji demo performance by 5.1% +/- 1.9% (n=15), by
reducing CPU time spent thrashing around those tiny little constant BOs.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw.c
|
| 1f32c665c8af0622e2bbf451edb999ffbcd7d0fe |
|
20-Apr-2011 |
Eric Anholt <eric@anholt.net> |
intel: Add support for ARB_sampler_objects.
This extension support consists of replacing
"gl_texture_obj->Sampler." with "_mesa_get_samplerobj(ctx, unit)->".
One instance of referencing the texture's base sampler remains in the
initial miptree allocation, where I'm not sure we have a clear
association with any texture unit.
Tested with piglit ARB_sampler_objects/sampler-objects.
Reviewed-by: Brian Paul <brianp@vmware.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw.c
|
| 1df72402d99145425531297eef6772b88ce5225d |
|
20-Apr-2011 |
Eric Anholt <eric@anholt.net> |
i965: Add support for NV_conditional_render.
Since we lack hardware support for it, this is a simple matter of
checking _mesa_check_conditional_render at the entrypoints, and
suppressing it for the metaops where it doesn't apply.
Reviewed-by: Brian Paul <brianp@vmware.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw.c
|
| ff5dd55e264d8f0282aa3ae3dc4f6ab26d98731d |
|
14-Apr-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Convert 3DPRIMITIVE command from struct-style to OUT_BATCH style.
Most of the newer portions of the code use OUT_BATCH style. I prefer
this style because it offers a clear distinction between a) hardware
messages/structures with a mandatory format, and b) data structures for
our own internal use that we can format however we want.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw.c
|
| ecfaab88b2577bd0395bc05d75a036126806a9c4 |
|
10-Apr-2011 |
Brian Paul <brianp@vmware.com> |
mesa: move sampler state into new gl_sampler_object type
gl_texture_object contains an instance of this type for the regular
texture object sampling state. glGenSamplers() generates new instances
of gl_sampler_object which can override that state with glBindSampler().
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw.c
|
| c625aa19cb53ed27f91bfd16fea6ea727e9a5bbd |
|
18-Feb-2011 |
Chris Wilson <chris@chris-wilson.co.uk> |
intel: extend current vertex buffers
If the next vertex arrays are a (discontiguous) continuation of the
current arrays, such that the new vertices are simply offset from the
start of the current vertex buffer definitions we can reuse those
defintions and avoid the overhead of relocations and invalidations.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw.c
|
| 559435d9152acc7162e4e60aae6591c7c6c8274b |
|
11-Feb-2011 |
Chris Wilson <chris@chris-wilson.co.uk> |
i965: emit one vb packet per vbo
Track reuse of the vertex buffer objects and so minimise the number of
vertex buffers used by the hardware (and their relocations).
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw.c
|
| 8d68a90e225d831a395ba788e425cb717eec1f9a |
|
10-Feb-2011 |
Chris Wilson <chris@chris-wilson.co.uk> |
intel: use pwrite for batch
It's faster. Not only is the memcpy more efficiently performed in the
kernel (making up for the system call overhead), but by not using mmap
we remove the greater overhead of tracking the vma of every batch.
And it means we can read back from the batch buffer without incurring
the cost of a uncached read through the GTT.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw.c
|
| abb37861d9f3310fe2d16194d893682092f41087 |
|
08-Feb-2011 |
Chris Wilson <chris@chris-wilson.co.uk> |
i965: Combine vb upload buffer with the general upload buffer
Reuse the new common upload buffer for uploading temporary indices and
rebuilt vertex arrays.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw.c
|
| c27285610c9f9b50d06bf0f2725da195937cb48d |
|
13-Dec-2010 |
Eric Anholt <eric@anholt.net> |
i965: Add support for using the BLT ring on gen6.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw.c
|
| bb1540835056cdea5db6f55b19c0c87358f14cd1 |
|
03-Nov-2010 |
Eric Anholt <eric@anholt.net> |
intel: Annotate debug printout checks with unlikely().
This provides the optimizer with hints about code hotness, which we're
quite certain about for debug printouts (or, rather, while we
developers often hit the checks for debug printouts, we don't care
about performance while doing so).
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw.c
|
| 338b3f0b90fdd6f5f6a84a7cf7cd6f3c1be65105 |
|
14-Oct-2010 |
Zhenyu Wang <zhenyuw@linux.intel.com> |
Revert "i965: fallback lineloop on sandybridge for now"
This reverts commit 73dab75b4165f7d2214a68d4ba8e3cb7aab9b4ac.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw.c
|
| f9995b30756140724f41daf963fa06167912be7f |
|
12-Oct-2010 |
Kristian Høgsberg <krh@bitplanet.net> |
Drop GLcontext typedef and use struct gl_context instead
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw.c
|
| 43873b53c4d15f10f0321c770b1b8bd537cc226d |
|
12-Oct-2010 |
Eric Anholt <eric@anholt.net> |
i965: Don't rebase the index buffer to min 0 if any arrays are in VBOs.
There was a check to only do the rebase if we didn't have everything
in VBOs, but nexuiz apparently hands us a mix of VBOs and arrays,
resulting in blocking on the GPU to do a rebase.
Improves nexuiz 800x600, high-settings performance on my Ironlake 41%
(+/- 1.3%), from 14.0fps to 19.7fps.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw.c
|
| 73dab75b4165f7d2214a68d4ba8e3cb7aab9b4ac |
|
26-Sep-2010 |
Zhenyu Wang <zhenyuw@linux.intel.com> |
i965: fallback lineloop on sandybridge for now
Until we fixed GS hang issue.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw.c
|
| 3b3278519af67beb3dc9c134a6bd127370cf82f8 |
|
10-Jun-2010 |
Eric Anholt <eric@anholt.net> |
i965: Move no_batch_wrap assertion out across the area we're trying to verify.
It's more likely that we wrap badly in state setup than in the little
primitive packet.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw.c
|
| 34474fa4119378ef9fbb9fb557cc19c0a1ca1f7e |
|
07-Jun-2010 |
Eric Anholt <eric@anholt.net> |
intel: Change dri_bo_* to drm_intel_bo* to consistently use new API.
The slightly less mechanical change of converting the emit_reloc calls
will follow.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw.c
|
| c67d9d84f501f145f841c0b981caff6f4dfd936f |
|
13-May-2010 |
Eric Anholt <eric@anholt.net> |
i965: Reduce a single GL_QUADS to GL_TRIANGLE_FAN.
This is similar to the GL_QUAD_STRIP -> TRIANGLE_STRIP optimization --
the GS usage to split the quads into tris is a huge bottleneck, so a
quick check improves glean blendFunc time massively (width * height of
the window of single-pixel GL_QUADS, many many times). This may also
end up helping with cairo performance, which sometimes ends up drawing
a single quad.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw.c
|
| 298be2b028263b2c343a707662c6fbfa18293cb2 |
|
19-Feb-2010 |
Kristian Høgsberg <krh@bitplanet.net> |
Replace the _mesa_*printf() wrappers with the plain libc versions
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw.c
|
| d449627829e1a4a3250a1a723af2f4e3cd5fd194 |
|
18-Feb-2010 |
Kristian Høgsberg <krh@bitplanet.net> |
intel: Implement the DRI2 invalidate function properly
This uses a stamp mechanisms to mark the DRI drawable as invalid.
Instead of immediately updating the buffers we just bump the drawable
stamp and call out to DRI2GetBuffers "later".
"Later" used to be at LOCK_HARDWARE time, and this patch brings back
callouts at the points where we used to call LOCK_HARDWARE. A new function,
intel_prepare_render(), is called where we used to call LOCK_HARDWARE,
and if the buffers are invalid, we call out to DRI2GetBuffers there.
This lets us invalidate buffers only when notified instead of on
every glViewport() call. If the loader calls the DRI invalidate
entrypoint, we disable viewport triggered buffer invalidation.
Additionally, we can clean up the old viewport mechanism a bit,
since we can just invalidate the buffers and not worry about
reentrancy and whatnot.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw.c
|
| 9b22427911ad27efc1f36faee9462c6082d0417c |
|
25-Jan-2010 |
Brian Paul <brianp@vmware.com> |
Merge branch 'mesa_7_7_branch'
Conflicts:
src/mesa/drivers/dri/intel/intel_screen.c
src/mesa/drivers/dri/intel/intel_swapbuffers.c
src/mesa/drivers/dri/r300/r300_emit.c
src/mesa/drivers/dri/r300/r300_ioctl.c
src/mesa/drivers/dri/r300/r300_tex.c
src/mesa/drivers/dri/r300/r300_texstate.c
|
| 634ec5c2abf05a9a8c27d9199ded5d1ad91e538a |
|
23-Jan-2010 |
Vinson Lee <vlee@vmware.com> |
i965: Remove unnecessary headers.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw.c
|
| 2861d9200be15cc44e8825387d3bd79086523c67 |
|
02-Jan-2010 |
Kristian Høgsberg <krh@bitplanet.net> |
intel: Drop more cliprect bookkeeping
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw.c
|
| 5203b7227ccb6b618fa42f08434d4a3cf123dca2 |
|
02-Jan-2010 |
Kristian Høgsberg <krh@bitplanet.net> |
intel: Drop batchbuffer cliprect_mode tracking
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw.c
|
| 01dc463e5d5513e059eea601710cd4babe02610d |
|
02-Jan-2010 |
Kristian Høgsberg <krh@bitplanet.net> |
intel: Drop LOCK/UNLOCK_HARDWARE()
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw.c
|
| a376e5c48237be0300bce6702ed947086d3ee23f |
|
18-Nov-2009 |
Eric Anholt <eric@anholt.net> |
intel: Consistently use no_batch_wrap in intel_context struct.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw.c
|
| 8e0f40d28777f1ae599a95312788fe29a0515a0d |
|
04-Nov-2009 |
Eric Anholt <eric@anholt.net> |
intel: Use PIPE_CONTROL on gen4 hardware for doing pipeline flushing.
This should do all the things that MI_FLUSH did, but it can be pipelined
so that further rendering isn't blocked on the flush completion unless
necessary.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw.c
|
| 7bf63473623e01933adc0e8f4464eda8f2860564 |
|
09-Sep-2009 |
Brian Paul <brianp@vmware.com> |
Merge branch 'mesa_7_6_branch'
|
| 0c309bb494b6ee1c403442d1207743f749f95b6e |
|
09-Sep-2009 |
Brian Paul <brianp@vmware.com> |
Merge branch 'mesa_7_5_branch' into mesa_7_6_branch
Conflicts:
Makefile
configs/default
progs/glsl/Makefile
src/gallium/auxiliary/util/u_simple_shaders.c
src/gallium/state_trackers/glx/xlib/xm_api.c
src/mesa/drivers/dri/i965/brw_draw_upload.c
src/mesa/drivers/dri/i965/brw_vs_emit.c
src/mesa/drivers/dri/intel/intel_context.h
src/mesa/drivers/dri/intel/intel_pixel.c
src/mesa/drivers/dri/intel/intel_pixel_read.c
src/mesa/main/texenvprogram.c
src/mesa/main/version.h
|
| f959ccdfa6c8accd74b6e33040b716645f0a7057 |
|
27-Aug-2009 |
Eric Anholt <eric@anholt.net> |
intel: Add support for ARB_draw_elements_base_vertex.
On the 965, we just drop the value into the primitive packet. On non-945,
we rely on the sw tnl code handling it.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw.c
|
| b2de02852381dccea6cb9bdca049d5629cca80ef |
|
08-Sep-2009 |
Brian Paul <brianp@vmware.com> |
i965: #include clean-ups
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw.c
|
| 8de625c7cf639c583e8bf43acb1214010989bb64 |
|
08-Sep-2009 |
Brian Paul <brianp@vmware.com> |
i965: fix incorrect test for vertex position attribute
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw.c
|
| 255e5be265133280293bbfd8b2f9b74b2dec50bb |
|
11-Aug-2009 |
Eric Anholt <eric@anholt.net> |
i965: Avoid re-uploading the index buffer when we don't need to.
No performance difference proven at 95% confidence with my GLSL demo (n=10).
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw.c
|
| 2708ddfb06a36d8568e2aa130bf1f7d551fcd309 |
|
11-Aug-2009 |
Eric Anholt <eric@anholt.net> |
vbo: Avoid extra validation of DrawElements.
This saves mapping the index buffer to get a bounds on the indices that
drivers just drop on the floor in the VBO case (cache win), saves a bonus
walk of the indices in the CheckArrayBounds case, and other miscellaneous
validation. On intel it's a particularly a large win (50-100% in my app)
because even though we let the indices stay in both CPU and GPU caches, we
still end up waiting for the GPU to be done with the buffer before reading
from it.
Drivers that want the min/max_index fields must now check index_bounds_valid
and use vbo_get_minmax_index before using them.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw.c
|
| 510c3bd7a1a8f6e350ca7b05ced1f0323098b2eb |
|
07-Jul-2009 |
Eric Anholt <eric@anholt.net> |
i965: Remove BRW_NEW_INPUT_VARYING
This state flag has been unused since the ffvertex_prog move to core.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw.c
|
| 94008088c1e6758a44a2f48c5a94db1f072d255a |
|
29-Jun-2009 |
Eric Anholt <eric@anholt.net> |
intel: Move note_unlock() implementation to the one place it's needed.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw.c
|
| 40bc2748c2781600c748e546160bcc2aab637825 |
|
06-Mar-2009 |
Eric Anholt <eric@anholt.net> |
intel: Add always_flush_batch driconf option for making small batchbuffers.
This can improve debugging with INTEL_DEBUG=batch,sync by giving smaller
batchbuffers.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw.c
|
| f3687284c12f34268172b9c60e2effd697162129 |
|
06-Mar-2009 |
Eric Anholt <eric@anholt.net> |
intel: Add always_flush_cache driconf option for debugging cache flush failure.
I keep wanting to hack this knob in as a one-time thing, so it seemed useful
to have all the time.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw.c
|
| 34683150878e0af0859c94d0c1f0c4bf8395b042 |
|
05-Mar-2009 |
Robert Ellison <papillo@vmware.com> |
i965: add software fallback for conformant 3D textures and GL_CLAMP
The i965 hardware cannot do GL_CLAMP behavior on textures; an earlier
commit forced a software fallback if strict conformance was required
(i.e. the INTEL_STRICT_CONFORMANCE environment variable was set) and
2D textures were used, but it was somewhat flawed - it could trigger
the software fallback even if 2D textures weren't enabled, as long
as one texture unit was enabled.
This fixes that, and adds software fallback for GL_CLAMP behavior with
1D and 3D textures.
It also adds support for a particular setting of the INTEL_STRICT_CONFORMANCE
environment variable, which forces software fallbacks to be taken *all*
the time. This is helpful with debugging. The value is:
export INTEL_STRICT_CONFORMANCE=2
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw.c
|
| 17c7852bf93c4d4edf0c2cf0bdc553d399e2f51a |
|
27-Feb-2009 |
Robert Ellison <papillo@vmware.com> |
i965: texture fixes: bordered textures, fallback rendering
i965 doesn't natively support GL_CLAMP; it treats it like
GL_CLAMP_TO_EDGE, which fails conformance tests.
This fix adds a clause to the check_fallbacks() test to check
whether GL_CLAMP is in use on any enabled 2D texture. If so,
and if strict conformance is required (via INTEL_STRICT_CONFORMANCE),
a software fallback is mandated.
In addition, validate textures *before* checking for fallbacks,
rather than after; otherwise, the texture state is never validated
and can't be trusted. (In particular, if texturing is enabled and
the sampler would access any level beyond level 0 of a texture, the
sampler will segfault, because texture validation sets the firstLevel
and lastLevel fields of a texture object so that the valid levels
will be mapped and accessed correctly. If texture validation doesn't
occur, only level 0 is accessed correctly, and that only because
firstLevel and lastLevel happen to be set to 0.)
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw.c
|
| 73658ff04fd4cb5f492b0477775430efc5f8b4ca |
|
21-Feb-2009 |
Robert Ellison <papillo@vmware.com> |
i965: fix line stipple fallback for GL_LINE_STRIP primitives
When doing line stipple, the stipple count resets on each line segment,
unless the primitive is a GL_LINE_LOOP or a GL_LINE_STRIP.
The existing code correctly identifies the need for a software fallback
to handle conformant line stipple on GL_LINE_LOOP primitives, but
neglects to make the same assessment on GL_LINE_STRIP primitives.
This fixes it so they match.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw.c
|
| 052c1d66a1ab1f2665870dc77dab28d20416cdf1 |
|
30-Jan-2009 |
Eric Anholt <eric@anholt.net> |
i965: Remove brw->attribs now that we can just always look in the GLcontext.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw.c
|
| 14321fcfde9e30d0b9f15aab3c9a057271ae6295 |
|
30-Jan-2009 |
Eric Anholt <eric@anholt.net> |
i965: Delete old metaops code now that there are no remaining consumers.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw.c
|
| 095c3a5cb16dae5c1e4cf85bffd3cb2465ab9e28 |
|
15-Dec-2008 |
Eric Anholt <eric@anholt.net> |
i965: Update state before checking for fallbacks in brw_try_draw_prims.
This got flipped around in 7855b2aef6bd9e9c2d73260b5cd166159b2525c6.
Bug #18907. Thanks to idr for pointing me at a nicer testcase than blender.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw.c
|
| 7855b2aef6bd9e9c2d73260b5cd166159b2525c6 |
|
27-Nov-2008 |
Eric Anholt <eric@anholt.net> |
i965: Reduce fast-pathiness of brw_try_draw_prims, bringing in important checks.
Later primitives, even if they caused a full state validate, wouldn't check
that there was enough space in the batchbuffer, occasionally triggering the
sanity check. We also skipped the aperture space check, even if it would
mean bringing in new programs and associated state.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw.c
|
| c30eb2c104c19c758c0b2a2461ad7f38cfa747d0 |
|
12-Nov-2008 |
Eric Anholt <eric@anholt.net> |
i965: Upload state on primitive switch, don't just prepare it.
This was a regression in 59b2c2adbbece27ccf54e58b598ea29cb3a5aa85 that broke
blender, among other apps.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw.c
|
| 59b2c2adbbece27ccf54e58b598ea29cb3a5aa85 |
|
24-Oct-2008 |
Eric Anholt <eric@anholt.net> |
i965: Fix check_aperture calls to cover everything needed for the prim at once.
Previously, since my check_aperture API change, we would check each piece of
state against the batchbuffer individually, but not all the state against the
batchbuffer at once. In addition to not being terribly useful in assuring
success, it probably also increased CPU load by calling check_aperture many
times per primitive.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw.c
|
| 0cade4de4f74f6b0e86fb6622e2fc370c73fd840 |
|
20-Oct-2008 |
Eric Anholt <eric@anholt.net> |
intel: Don't keep intel->pClipRects, and instead just calculate it when needed.
This avoids issues with dereferencing stale cliprects around intel_draw_buffer
time. Additionally, take advantage of cliprects staying constant for FBOs and
DRI2, and emit cliprects in the batchbuffer instead of having to flush batch
each time they change.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw.c
|
| c157cfc6376f7469ab272b18868183e5ff9ac754 |
|
07-Oct-2008 |
Eric Anholt <eric@anholt.net> |
i965: Add ARB_occlusion_query support.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw.c
|
| 7d99ddcb2bb09f1f54d91e6e20e42d217a5bccdf |
|
26-Sep-2008 |
Eric Anholt <eric@anholt.net> |
intel: Fix a number of memory leaks on context destroy.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw.c
|
| d533da2db873942b3f8676a754b8be3c9718bedf |
|
24-Sep-2008 |
Eric Anholt <eric@anholt.net> |
i965: Cope with batch getting flushed in the middle of batchbuffer emits.
This isn't required for GEM (at least, yet), but the check_aperture code
for non-GEM results in batch getting flushed during emit. brw_state_upload
restarts state emits, but a bunch of the state emit functions were assuming
that they would be called exactly once, after prepare and before new_batch.
Bug #17179.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw.c
|
| ecadb51bbcb972a79f3ed79e65a7986b9396e757 |
|
18-Sep-2008 |
Brian Paul <brian.paul@tungstengraphics.com> |
mesa: added "main/" prefix to includes, remove some -I paths from Makefile.template
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw.c
|
| 35fd72756a05463568d94862f4fcd234903e1204 |
|
08-Sep-2008 |
Eric Anholt <eric@anholt.net> |
intel: track move of bo_exec from drivers to bufmgr.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw.c
|
| f75843a517bd188639e6866db2a7b04de3524e16 |
|
24-Aug-2008 |
Dave Airlie <airlied@linux.ie> |
Revert "Revert "Merge branch 'drm-gem'""
This reverts commit 7c81124d7c4a4d1da9f48cbf7e82ab1a3a970a7a.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw.c
|
| 7c81124d7c4a4d1da9f48cbf7e82ab1a3a970a7a |
|
24-Aug-2008 |
Dave Airlie <airlied@linux.ie> |
Revert "Merge branch 'drm-gem'"
This reverts commit 53675e5c05c0598b7ea206d5c27dbcae786a2c03.
Conflicts:
src/mesa/drivers/dri/i965/brw_wm_surface_state.c
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw.c
|
| d2796939f18815935c8fe1effb01fa9765d6c7d8 |
|
08-Aug-2008 |
Eric Anholt <eric@anholt.net> |
intel-gem: Update to new check_aperture API for classic mode.
To do this, I had to clean up some of 965 state upload stuff. We may end
up over-emitting state in the aperture overflow case, but that should be rare,
and I'd rather have the simplification of state management.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw.c
|
| c6b36e5498cf6593daf001123cacec4ccaf305ca |
|
20-May-2008 |
Xiang, Haihao <haihao.xiang@intel.com> |
i965: Check fallback before accounting for index/vertex buffer size. fix #16028.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw.c
|
| 2fa2dd3908c783663ca421134cde82e9b6a38a0d |
|
05-May-2008 |
Xiang, Haihao <haihao.xiang@intel.com> |
i965: Don't cast the result of brw_prepare_vertices to an unsigned value.
Negative value means other errors, not aperture overflow. fix bug #15752
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw.c
|
| 008653ac55776d6b1c6d1627ad20937aa1c4dbda |
|
17-Apr-2008 |
Dave Airlie <airlied@redhat.com> |
i965: initial attempt at fixing the aperture overflow
Makes state emission into a 2 phase, prepare sets things up and accounts
the size of all referenced buffer objects. The emit stage then actually
does the batchbuffer touching for emitting the objects.
There is an assert in dri_emit_reloc if a reloc occurs for a buffer
that hasn't been accounted yet.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw.c
|
| f7cfc51b057d9d2fa109b32796b992e8f4f3bfcc |
|
18-Mar-2008 |
Zou Nan hai <nanhai.zou@intel.com> |
Revert "[i965] make stipple pattern continue across GL_LINE_LOOP and GL_LINE_STRIP"
There is no information in GS to determinate when to reset line stipple count, still fallback to software
This reverts commit 5a0314b431ab147c6156c3011f4cb54161ba4b25.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw.c
|
| 5a0314b431ab147c6156c3011f4cb54161ba4b25 |
|
18-Mar-2008 |
Zou Nan hai <nanhai.zou@intel.com> |
[i965] make stipple pattern continue across GL_LINE_LOOP and GL_LINE_STRIP
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw.c
|
| 2abcc512a3ce81bc11ff2b45a2208d3400a2385d |
|
03-Feb-2008 |
Eric Anholt <eric@anholt.net> |
[965] Convert brw_draw_upload to managing dri_bos, not gl_buffer_objects.
This helps us avoid a bunch of mess with gl_client_arrays that we filled
with unused data and confused readers.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw.c
|
| 3ad9ca8240ffa32a8dfbfffd0cfb1d0384e04a9f |
|
15-Jan-2008 |
Zou Nan hai <nanhai.zou@intel.com> |
i965: fix an assert fail in brw_new_batch
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw.c
|
| 7fec1eb21ba2121f530cb5412f658303b683e1d3 |
|
12-Jan-2008 |
Eric Anholt <eric@anholt.net> |
[965] Force a new vertex upload buffer at new batch time.
Otherwise, we could choose to upload into the temporary VBO that we just fired
off to the hardware. Good for a 60% OA performance improvement.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw.c
|
| a04b632350e5d0e9994fc667afc59407a39da0ba |
|
10-Jan-2008 |
Eric Anholt <eric@anholt.net> |
[intel] Add more cliprect modes to cover other meanings for batch emits.
The previous change gave us only two modes, one which looped over the batch
per cliprect (3d drawing) and one that didn't (state updeast).
However, we really want 4:
- Batch doesn't care about cliprects (state updates)
- Batch needs DRAWING_RECTANGLE looping per cliprect (3d drawing)
- Batch needs to be executed just once (region fills, copies, etc.)
- Batch already includes cliprect handling, and must be flushed by unlock time
(copybuffers, clears).
All callers should now be fixed to use one of these states for any batchbuffer
emits. Thanks to Keith Whitwell for pointing out the failure.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw.c
|
| 7da98d7ebaf4475812f2ce44062d50bee393faf7 |
|
09-Jan-2008 |
Eric Anholt <eric@anholt.net> |
[965] Allow more than one draw_prims per batchbuffer.
The comment about (vbo)_exec_api.c appeared to be stale, as the VBO code seems
to only use non-named VBOs (not actual VBOs) or freshly-allocated VBO data.
This brings a 2x speedup to openarena, because we can submit nearly-full
batchbuffers instead of many 450-byte ones.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw.c
|
| beddf653a914903156712aa472b5deaddb7bbaed |
|
09-Jan-2008 |
Eric Anholt <eric@anholt.net> |
[intel] Clean up cliprect handling in intel drivers.
In particular, batch buffers are no longer flushed when switching from
CLIPRECTS to NO_CLIPRECTS or vice versa, and 965 just uses DRM cliprect
handling for primitives instead of trying to sneak in its own to avoid the
DRM stuff. The disadvantage is that we will re-execute state updates per
cliprect, but the advantage is that we will be able to accumulate larger
batch buffers, which were proving to be a major overhead.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw.c
|
| 7ce12b0863f1cc03bdd7c65c0c0733b2ff903e40 |
|
09-Jan-2008 |
Eric Anholt <eric@anholt.net> |
[intel] Remove the dead intel->need_flush member.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw.c
|
| 3fe9d5cbb7c680c6fb88a2eba678b28a2a06949e |
|
15-Dec-2007 |
Eric Anholt <eric@anholt.net> |
[intel] Merge intel_buffer_objects to shared.
965 gains fixed TTM typing of the buffer object buffers and unused PBO
functions, and 915 gains buffer size == 0 fixes from 965.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw.c
|
| 7c71ef3a3d0cf2620525f468960cdc76a0fb0d33 |
|
12-Dec-2007 |
Eric Anholt <eric@anholt.net> |
[intel] Move bufmgr back to context instead of screen, fixing glthreads.
Putting the bufmgr in the screen is not thread-safe since the emit_reloc
changes. It also led to a significant performance hit from pthread usage
for the attempted thread-safety (up to 12% of a cpu spent on refcounting
protection in single-threaded 965). The motivation had been to allow
multi-context bufmgr sharing in classic mode, but it wasn't worth the cost.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw.c
|
| e3a6e60040b7f6ea7965e52f8f9881ed31e0347c |
|
08-Dec-2007 |
Eric Anholt <eric@anholt.net> |
[965] Convert the driver to dri_bufmgr interface and enable TTM.
This is currently believed to work but be a significant performance loss.
Performance recovery should be soon to follow.
The dri_bo_fake_disable_backing_store() call was added to allow backing store
disable like bufmgr_fake.c did, which is a significant performance win (though
it's missing the no-fence-subdata part).
This commit is a squash merge of the 965-ttm branch, which had some history
I wanted to avoid pulling due to noisiness and brokenness at many points
for git-bisecting.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw.c
|
| 27674c41352dc78ad79f67cebca16d7896cd2093 |
|
20-Nov-2007 |
Eric Anholt <eric@anholt.net> |
[965] Convert DBG macro to use FILE_DEBUG_FLAG like i915.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw.c
|
| 38c30a81844214b030c9c637f9cf97bd2bf19cde |
|
26-Sep-2007 |
Eric Anholt <eric@anholt.net> |
[965] Remove AUB file support.
This code existed to dump logs of hardware access to be replayed in simulation.
Since we have real hardware now, it's not really needed.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw.c
|
| c235cc71a296e63f65cafcc95839119cf3cf2a63 |
|
28-Aug-2007 |
Xiang, Haihao <haihao.xiang@intel.com> |
i965: flush batch buffer when getting the maximum. This makes
some 3D programs such as pymol work well.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw.c
|
| 3a2ffadb7c98c040f01340d20289cffe753d48c2 |
|
23-May-2007 |
Brian <brian.paul@tungstengraphics.com> |
include swrast_setup/swrast_setup.h to silence warning
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw.c
|
| 121533defb48abddbf796aed62c1282cfa5234f9 |
|
03-May-2007 |
Brian <brian@yutani.localnet.net> |
add some #includes to silence warnings
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw.c
|
| a783713432a1aed168688ace7d03bc11abf9b406 |
|
05-Mar-2007 |
Xiang, Haihao <haihao.xiang@intel.com> |
fix for bug#9971
call swsetup_Wakeup before falling back to software rendering
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw.c
|
| 605d428d20819ac3f46aaeb4a66707febec7ded2 |
|
01-Feb-2007 |
Keith Whitwell <keith@tungstengraphics.com> |
Cope with internally-generated null inputs.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw.c
|
| 893526b8a823fe1b88f2b46376155afb91c84016 |
|
30-Jan-2007 |
Keith Whitwell <keith@tungstengraphics.com> |
Use new rebase helper. Remove other rebase code.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw.c
|
| f2eb6434ab1cf72e938956c82d2f530368a6be4a |
|
31-Oct-2006 |
Keith Whitwell <keith@tungstengraphics.com> |
cleanup code, compiles with vbo changes
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw.c
|
| efef291dc71eb57f90785a26957f4b3e01733156 |
|
30-Oct-2006 |
Keith Whitwell <keith@tungstengraphics.com> |
checkpoint - remove dead files, otherwise untested
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw.c
|
| 759facb4d87843f6368fad9c5f20a5b1b3d95055 |
|
23-Oct-2006 |
Keith Whitwell <keith@tungstengraphics.com> |
Emit cliprects in the userspace driver as required, rather than
passing them to the kernel. This works because all drawing commands
in the 965 driver are emitted with the lock held and the batchbuffer
is always flushed prior to releasing the lock. This allows multiple
cliprects to be dealt with, without replaying entire batchbuffers and
redundantly re-emitting state.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw.c
|
| b35121d54df4bb8700c4135203162c1d79ca637d |
|
20-Sep-2006 |
Keith Whitwell <keith@tungstengraphics.com> |
1) Add a new flag in the sarea (coopting the unused texAge value) to
identify context switches between members of a share group -
ie. multiple contexts in a single application, possibly on different
threads. In this case the contexts share a bufmgr instance and there
is no need to evict textures - so don't.
2) Use a new flag 'need_flush' to ensure hardware rendering is flushed
prior to starting a software fallback.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw.c
|
| 285801a9eda72310aa34e39c82beb57ec5e752d3 |
|
20-Sep-2006 |
Keith Whitwell <keith@tungstengraphics.com> |
Use DEBUG_SYNC to switch between per-primitive and per-frame aubfile dumps.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw.c
|
| b1cb39d8bdb6707be2e44d38c52f44515bcbf16e |
|
12-Sep-2006 |
Keith Whitwell <keith@tungstengraphics.com> |
quieten debug
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw.c
|
| 02df36f394da4f699b4841c279a6b573fcb7c32b |
|
08-Sep-2006 |
Keith Whitwell <keith@tungstengraphics.com> |
Basic facility for playing back captured aubfiles. Requires a small
hack to the drm to disable command verification on the cmd_buffer
ioctl. Doesn't exactly replay as commands are normally delivered as
batchbuffers but are captured and replayed as commands on the ring.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw.c
|
| 493b2ddecb47fdacc4b73d9c9a3ba2e46489105f |
|
07-Sep-2006 |
Keith Whitwell <keith@tungstengraphics.com> |
Cope with memory pool fragmentation by allowing a second attempt at
rendering operations to take place after evicting all resident
buffers.
Cope better with memory allocation failures throughout the driver and
improve tracking of failures.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw.c
|
| 14ec34d64733478b773190cb62be37b7b2871a7f |
|
06-Sep-2006 |
Keith Whitwell <keith@tungstengraphics.com> |
Simplify the immediate and displaylist code. Treat VertexAttrib*ARB
as non-aliasing and cope with the >32 attributes that result, taking
materials into account.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw.c
|
| 9f344b3e7d6e23674dd4747faec253f103563b36 |
|
09-Aug-2006 |
Eric Anholt <anholt@FreeBSD.org> |
Add Intel i965G/Q DRI driver.
This driver comes from Tungsten Graphics, with a few further modifications by
Intel.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_draw.c
|