| 112711afefcfcd43680c7c4aa8d38ef180e8811e |
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10-Apr-2015 |
sewardj <sewardj@a5019735-40e9-0310-863c-91ae7b9d1cf9> |
Add a port to Linux/TileGx. Zhi-Gang Liu (zliu@tilera.com)
Valgrind aspects, to match vex r3124.
See bug 339778 - Linux/TileGx platform support to Valgrind
git-svn-id: svn://svn.valgrind.org/valgrind/trunk@15080 a5019735-40e9-0310-863c-91ae7b9d1cf9
/external/valgrind/coregrind/m_cache.c
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| cae0cc22b83ffb260ee8379e92099c5a701944cb |
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08-Aug-2014 |
carll <carll@a5019735-40e9-0310-863c-91ae7b9d1cf9> |
This commit is for Bugzilla 334384. The Bugzilla contains patch 1 of 3
to add PPC64 LE support. The other two patches can be found in Bugzillas
334834 and 334836. The commit does not have a VEX commit associated with it.
POWER PC, add initial Little Endian support
The IBM POWER processor now supports both Big Endian and Little Endian.
This patch renames the #defines with the name ppc64 to ppc64be for the BE
specific code. This patch adds the Little Endian #define ppc64le to the
Additionally, a few functions are renamed to remove BE from the name if the
function is used by BE and LE. Functions that are BE specific have BE put
in the name.
The goals of this patch is to make sure #defines, function names and
variables consistently use PPC64/ppc64 if it refers to BE and LE,
PPC64BE/ppc64be if it is specific to BE, PPC64LE/ppc64le if it is LE
specific. The patch does not break the code for PPC64 Big Endian.
The test files memcheck/tests/atomic_incs.c, tests/power_insn_available.c
and tests/power_insn_available.c are also updated to the new #define
definition for PPC64 BE.
Signed-off-by: Carl Love <carll@us.ibm.com>
git-svn-id: svn://svn.valgrind.org/valgrind/trunk@14238 a5019735-40e9-0310-863c-91ae7b9d1cf9
/external/valgrind/coregrind/m_cache.c
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| f0c1250e324f6684757c6a15545366447ef1d64f |
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12-Jan-2014 |
sewardj <sewardj@a5019735-40e9-0310-863c-91ae7b9d1cf9> |
Add support for ARMv8 AArch64 (the 64 bit ARM instruction set).
git-svn-id: svn://svn.valgrind.org/valgrind/trunk@13770 a5019735-40e9-0310-863c-91ae7b9d1cf9
/external/valgrind/coregrind/m_cache.c
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| 0f157ddb404bcde7815a1c5bf2d7e41c114f3d73 |
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18-Oct-2013 |
sewardj <sewardj@a5019735-40e9-0310-863c-91ae7b9d1cf9> |
Update copyright dates (20XY-2012 ==> 20XY-2013)
git-svn-id: svn://svn.valgrind.org/valgrind/trunk@13658 a5019735-40e9-0310-863c-91ae7b9d1cf9
/external/valgrind/coregrind/m_cache.c
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| 4df0bfc0614379192c780c944415dc420d9cfe8e |
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28-Feb-2013 |
petarj <petarj@a5019735-40e9-0310-863c-91ae7b9d1cf9> |
mips: adding MIPS64LE support to Valgrind
Necessary changes to Valgrind to support MIPS64LE on Linux.
Minor cleanup/style changes embedded in the patch as well.
The change corresponds to r2687 in VEX.
Patch written by Dejan Jevtic and Petar Jovanovic.
More information about this issue:
https://bugs.kde.org/show_bug.cgi?id=313267
git-svn-id: svn://svn.valgrind.org/valgrind/trunk@13292 a5019735-40e9-0310-863c-91ae7b9d1cf9
/external/valgrind/coregrind/m_cache.c
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| 33332a36b6eba9494a7e8ce7837883379bfb5e53 |
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17-Dec-2012 |
florian <florian@a5019735-40e9-0310-863c-91ae7b9d1cf9> |
Fix an operator precedence error found by BEAM.
git-svn-id: svn://svn.valgrind.org/valgrind/trunk@13184 a5019735-40e9-0310-863c-91ae7b9d1cf9
/external/valgrind/coregrind/m_cache.c
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| 19f91bbaedb4caef8a60ce94b0f507193cc0bc10 |
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10-Nov-2012 |
florian <florian@a5019735-40e9-0310-863c-91ae7b9d1cf9> |
Fix more Char/HChar mixups. Closing in...
git-svn-id: svn://svn.valgrind.org/valgrind/trunk@13119 a5019735-40e9-0310-863c-91ae7b9d1cf9
/external/valgrind/coregrind/m_cache.c
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| fb11d9736384835f3dfe0e627810048c22c5776d |
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02-Nov-2012 |
florian <florian@a5019735-40e9-0310-863c-91ae7b9d1cf9> |
s390: Autodetect cache info. These are the final bits to fix BZ 275800.
git-svn-id: svn://svn.valgrind.org/valgrind/trunk@13100 a5019735-40e9-0310-863c-91ae7b9d1cf9
/external/valgrind/coregrind/m_cache.c
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| b7058da8e033c572a5043c66660a98e0c6fec7bb |
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02-Nov-2012 |
florian <florian@a5019735-40e9-0310-863c-91ae7b9d1cf9> |
Tweak VG_(machine_get_cache_info).
Better messages. Always write cache info when in debug mode.
git-svn-id: svn://svn.valgrind.org/valgrind/trunk@13099 a5019735-40e9-0310-863c-91ae7b9d1cf9
/external/valgrind/coregrind/m_cache.c
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| 94830f470f13df0fcd92bc57bdf312b4716eca31 |
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18-Oct-2012 |
florian <florian@a5019735-40e9-0310-863c-91ae7b9d1cf9> |
Fix VG_(cpuid) invocations.
Also call cache_info_is_sensible. I forgot to do that in r13053.
git-svn-id: svn://svn.valgrind.org/valgrind/trunk@13055 a5019735-40e9-0310-863c-91ae7b9d1cf9
/external/valgrind/coregrind/m_cache.c
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| 38aeb9ff6ef22dbfd2fe3040c80de932c9a31b90 |
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18-Oct-2012 |
florian <florian@a5019735-40e9-0310-863c-91ae7b9d1cf9> |
Change cache detection for x86/amd64 to fill in VexCacheInfo directly.
New function write_cache_info to dump what was detected for debugging
purposes.
New function cache_info_is_sensible to ensure that autodetected
cache info lives up to the promises made in libvex.h.
Moved the trace-cache related kludgery to cachegrind where it belongs.
git-svn-id: svn://svn.valgrind.org/valgrind/trunk@13053 a5019735-40e9-0310-863c-91ae7b9d1cf9
/external/valgrind/coregrind/m_cache.c
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| 7862701c0e3f556e4a0c7ec4074a40526c73a4ef |
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07-Oct-2012 |
florian <florian@a5019735-40e9-0310-863c-91ae7b9d1cf9> |
This patch is the first installment of the cache info reorganisation.
It's reorg only. No new cache autodetection stuff has been added.
coregrind
pub_tool_cpuid.h is removed as it is no longer exposed to tools.
Its contents has moved to pub_core_cpuid.h.
New file: coregrind/m_cache.c to contain the autodetect code for
cache configurations and define other cache characteristics that
cannot be autodetected (i.e. icaches_maintain_coherence). Most of
cg-arch/x86-amd64.c was moved here. The cache detection code for
x86-64 needs to be fixed to properly initialise VexCacheInfo. It
currently has cachegrind bias.
m_cache.c exports a single function (to coregrind):
VG_(machine_get_cache_info)(VexArchInfo *vai)
This function is called from VG_(machine_get_hwcaps) after hwcaps have
been detected.
cachegrind
Remove cachegrind/cg-{ppc32,ppc43,arm,mips32,s390x,x86-amd64}.c
With the exception of x86/mamd64 those were only establishing a
default cache configuration and that is so small a code snippet that
a separate file is no longer warranted. So, the code was moved to
cg-arch.c. Code was added to extract the relevant info from
x86-amd64.
New function maybe_tweak_LLc which captures the code to massage the
LLc cache configuration into something the simulator can handle. This
was originally in cg-x86-amd64.c but should be used to all architectures.
Changed warning message about missing cache auto-detect feature
to be more useful. Adapted filter-stderr scripts accordingly.
git-svn-id: svn://svn.valgrind.org/valgrind/trunk@13028 a5019735-40e9-0310-863c-91ae7b9d1cf9
/external/valgrind/coregrind/m_cache.c
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