| a89b04673925f2b40bbc8e060c8aa9f5d451b680 |
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18-Apr-2015 |
carll <carll@a5019735-40e9-0310-863c-91ae7b9d1cf9> |
Add support for the lbarx, lharx, stbcx and sthcs instructions.
The instructions are part of the ISA 2.06 but were not implemented
in all versions of hardware. The four instructions are all supported
in ISA 2.07. The instructions were put under the ISA 2.07 category
of supported instructions in this patch.
The VEX commit for this fix is r3137.
The bugzilla for this issue is 346324.
git-svn-id: svn://svn.valgrind.org/valgrind/trunk@15106 a5019735-40e9-0310-863c-91ae7b9d1cf9
/external/valgrind/none/tests/ppc64/test_isa_2_07_part1.c
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| dd690bf8d81c9119a7228446be12e3366e202176 |
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08-Aug-2014 |
carll <carll@a5019735-40e9-0310-863c-91ae7b9d1cf9> |
This commit is for Bugzilla 334836. The Bugzilla contains patch 3 of 3
to add PPC64 LE support. The other two patches can be found in Bugzillas
334384 and 334834. Note, there are no VEX changes in this patch.
PP64 Little Endian test case fixes.
This patch adds new LE and BE expect files where needed. In other
cases, the test was fixed to run correctly on LE and BE using based on
testing to see which platform is being used.
Where practical, the test cases have been changed so that the output
produced for BE and LE will be identical. The test cases that require
a major rewrite to make the output identical for BE and LE simply
had an additional expect file added.
Signed-off-by: Carl Love <carll@us.ibm.com>
git-svn-id: svn://svn.valgrind.org/valgrind/trunk@14240 a5019735-40e9-0310-863c-91ae7b9d1cf9
/external/valgrind/none/tests/ppc64/test_isa_2_07_part1.c
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| e6bd3e49c6f37b871974c3b5212476f1eed3fb77 |
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18-Oct-2013 |
carll <carll@a5019735-40e9-0310-863c-91ae7b9d1cf9> |
This commit adds testing support for the following instructions:
vaddcuq, vadduqm, vaddecuq, vaddeuqm,
vsubcuq, vsubuqm, vsubecuq, vsubeuqm,
vbpermq and vgbbd.
The completes adding the Power ISA 2.07 support.
Bugzilla 325816
VEX commit id 2790
git-svn-id: svn://svn.valgrind.org/valgrind/trunk@13653 a5019735-40e9-0310-863c-91ae7b9d1cf9
/external/valgrind/none/tests/ppc64/test_isa_2_07_part1.c
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| 24e40de8f2127d70117ed9af3bc4474cbc29cb8a |
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15-Oct-2013 |
carll <carll@a5019735-40e9-0310-863c-91ae7b9d1cf9> |
Power 8 support, phase 5
This commit adds the testcases for the following instructions:
vpmsumb, vpmsumh, vpmsumw, vpmsumd, vpermxor, vcipher, vcipherlast,
vncipher, vncipherlast, vsbox,
vclzb, vclzw, vclzh, vclzd,
vpopcntb, vpopcnth, vpopcntw, vpopcntd,
vnand, vorc, veqv,
vshasigmaw, vshasigmad,
bcdadd, bcdsub
The VEX commit that added the support for the above instructions was
commit 2789.
The patch is for Bugzilla 325628
git-svn-id: svn://svn.valgrind.org/valgrind/trunk@13646 a5019735-40e9-0310-863c-91ae7b9d1cf9
/external/valgrind/none/tests/ppc64/test_isa_2_07_part1.c
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| 6277067119ad816282b8e57727295b3adee14075 |
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01-Oct-2013 |
carll <carll@a5019735-40e9-0310-863c-91ae7b9d1cf9> |
Add tests for the phase 3 ISA 2.07 code patch
This patch adds testcases to an existing testcase
source file to test the new instructions which were
added to VEX support in the phase 3 ISA 2.07 code patch.
The patch also makes a small change to memcheck's
vbit tester code to allow successful execution.
Signed-off-by: Maynard Johnson <maynardj@us.ibm.com>
Bugzilla 324894. Corresponding VEX commit 2779
git-svn-id: svn://svn.valgrind.org/valgrind/trunk@13594 a5019735-40e9-0310-863c-91ae7b9d1cf9
/external/valgrind/none/tests/ppc64/test_isa_2_07_part1.c
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| 8efe4e40e702e4a1eafac37076e1df2ccd9b047b |
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12-Sep-2013 |
carll <carll@a5019735-40e9-0310-863c-91ae7b9d1cf9> |
The Power ISA 2.07 document includes a correction to the description for the
behavior of the xscvspdp instruction, indicating that if the source argument
is a SNaN, it is first changed to a QNaN before being converted from
single-precision to double-precision. This updated information about the
xscvspdp instruction exposed a bug in the VEX implementation for that
instruction and also a bug in the testing for all instructions having
special behavior for single-precision SNaN arguments.
The VEX code fix for this issue is r2760.
This patch fixes the test cases for the ISA 2.07.
Testing bug: In several ppc[64] test cases, an array of special
double-precision floating point values is set up, and then all elements of
that array are copied via assignment to a single-precision array ('float'
type). Assignment from a double to a float works fine for all cases, except for
SNaN values. In the case of a SNaN, the source is changed to a QNaN and then
converted to single-precision. So the end result was that our array of floats
did not have an actual SNaN value, and, therefore, any instructions that had
special behavior for a single-precision SNaN input argument was never being
properly tested. This patch makes some functional changes in the following
testcases:
none/tests/ppc[32|64]/test_isa_2_06_part2.c
none/tests/ppc[32|64]/test_isa_2_06_part3.c
none/tests/ppc[32|64]/test_isa_2_07_part2.c
These changes impacted the associated *.stdout.exp files, so the patch also
updates those files. Additionally, there were several errors in testcase
source comments that misidentified QNaN and SNaN bit patterns which this patch
corrects.
See bugzilla 324816.
git-svn-id: svn://svn.valgrind.org/valgrind/trunk@13544 a5019735-40e9-0310-863c-91ae7b9d1cf9
/external/valgrind/none/tests/ppc64/test_isa_2_07_part1.c
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| a81925998c22a5af981c6933f56f24437e790447 |
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10-Sep-2013 |
carll <carll@a5019735-40e9-0310-863c-91ae7b9d1cf9> |
Bugzilla 323437, this is phase 2 in a series of patches adding support for IBM
Power ISA 2.07. The first bugzilla in the series was: 322294: Add initial
support for IBM Power ISA 2.07
Phase 2 VEX commit 2756 added support for the following new instructions to
VEX/priv/guest_ppc_toIR.c:
- lq, stq, lqarx, stqcx.
- mfvsrwz, mtvsrwz
- fmrgew, fmrgow
This commit adds the corresponding test cases for these instructions.
git-svn-id: svn://svn.valgrind.org/valgrind/trunk@13539 a5019735-40e9-0310-863c-91ae7b9d1cf9
/external/valgrind/none/tests/ppc64/test_isa_2_07_part1.c
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| dfbf294f08ac004a60cb3b528d544cb7d0404eb0 |
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12-Aug-2013 |
carll <carll@a5019735-40e9-0310-863c-91ae7b9d1cf9> |
Initial ISA 2.07 support for POWER8-tuned libc
The IBM Power ISA 2.07 has been published on power.org, and IBM's new POWER8
processor is under development to implement that ISA. This patch provides
initial runtime and testsuite support for running Valgrind on POWER8 systems
running a soon-to-be released Linux distribution. This Linux distro will
include a POWER8-tuned libc that uses a subset of the new instructions from
ISA 2.07. Since virtually all applications link with libc, it would be
impossible to run an application under Valgrind on this distro without adding
support for these new instructions to Valgrind, so that's the intent of this
patch. Note that applications built on this distro will *not* employ new POWER8
instructions by default. There are roughly 150 new instructions in the Power
ISA 2.07, including hardware transaction management (HTM). Support for these
new instructions (modulo the subset included in this bug) will be added to
Valgrind in a phased approach, similar to what we did for Power ISA 2.06.
Bugzilla 322294, VEX commit 2740
git-svn-id: svn://svn.valgrind.org/valgrind/trunk@13494 a5019735-40e9-0310-863c-91ae7b9d1cf9
/external/valgrind/none/tests/ppc64/test_isa_2_07_part1.c
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