Searched defs:ExtType (Results 1 - 15 of 15) sorted by relevance

/external/llvm/include/llvm/Target/
H A DTargetLowering.h575 LegalizeAction getLoadExtAction(unsigned ExtType, EVT ValVT, EVT MemVT) const { argument
579 assert(ExtType < ISD::LAST_LOADEXT_TYPE && ValI < MVT::LAST_VALUETYPE &&
581 return (LegalizeAction)LoadExtActions[ValI][MemI][ExtType];
585 bool isLoadExtLegal(unsigned ExtType, EVT ValVT, EVT MemVT) const {
587 getLoadExtAction(ExtType, ValVT, MemVT) == Legal;
592 bool isLoadExtLegalOrCustom(unsigned ExtType, EVT ValVT, EVT MemVT) const {
594 (getLoadExtAction(ExtType, ValVT, MemVT) == Legal ||
595 getLoadExtAction(ExtType, ValVT, MemVT) == Custom);
1292 void setLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT,
1294 assert(ExtType < IS
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/external/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorOps.cpp201 ISD::LoadExtType ExtType = LD->getExtensionType(); local
202 if (LD->getMemoryVT().isVector() && ExtType != ISD::NON_EXTLOAD)
483 ISD::LoadExtType ExtType = LD->getExtensionType(); local
577 switch (ExtType) {
599 SDValue ScalarLoad = DAG.getExtLoad(ExtType, dl,
H A DLegalizeIntegerTypes.cpp456 ISD::LoadExtType ExtType = local
459 SDValue Res = DAG.getExtLoad(ExtType, dl, NVT, N->getChain(), N->getBasePtr(),
1899 ISD::LoadExtType ExtType = N->getExtensionType(); local
1912 Lo = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr, N->getPointerInfo(),
1919 if (ExtType == ISD::SEXTLOAD) {
1925 } else if (ExtType == ISD::ZEXTLOAD) {
1929 assert(ExtType == ISD::EXTLOAD && "Unknown extload!");
1947 Hi = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr,
1965 Hi = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr, N->getPointerInfo(),
1993 Hi = DAG.getNode(ExtType
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H A DLegalizeVectorTypes.cpp950 ISD::LoadExtType ExtType = LD->getExtensionType(); local
964 Lo = DAG.getLoad(ISD::UNINDEXED, ExtType, LoVT, dl, Ch, Ptr, Offset,
971 Hi = DAG.getLoad(ISD::UNINDEXED, ExtType, HiVT, dl, Ch, Ptr, Offset,
996 ISD::LoadExtType ExtType = MLD->getExtensionType(); local
1021 ExtType);
1033 ExtType);
2410 ISD::LoadExtType ExtType = LD->getExtensionType(); local
2414 if (ExtType != ISD::NON_EXTLOAD)
2415 Result = GenWidenVectorExtLoads(LdChain, LD, ExtType);
2441 ISD::LoadExtType ExtType local
3139 GenWidenVectorExtLoads(SmallVectorImpl<SDValue> &LdChain, LoadSDNode *LD, ISD::LoadExtType ExtType) argument
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H A DSelectionDAG.cpp253 ISD::NodeType ISD::getExtForLoadExtType(bool IsFP, ISD::LoadExtType ExtType) { argument
254 switch (ExtType) {
2606 unsigned ExtType = LD->getExtensionType(); local
2607 switch (ExtType) {
4748 SelectionDAG::getLoad(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType, argument
4777 return getLoad(AM, ExtType, VT, dl, Chain, Ptr, Offset, MemVT, MMO);
4781 SelectionDAG::getLoad(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType, argument
4786 ExtType = ISD::NON_EXTLOAD;
4787 } else if (ExtType == ISD::NON_EXTLOAD) {
4812 ID.AddInteger(encodeMemSDNodeFlags(ExtType, A
4850 getExtLoad(ISD::LoadExtType ExtType, SDLoc dl, EVT VT, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, EVT MemVT, bool isVolatile, bool isNonTemporal, bool isInvariant, unsigned Alignment, const AAMDNodes &AAInfo) argument
4863 getExtLoad(ISD::LoadExtType ExtType, SDLoc dl, EVT VT, SDValue Chain, SDValue Ptr, EVT MemVT, MachineMemOperand *MMO) argument
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H A DDAGCombiner.cpp213 ISD::NodeType ExtType);
910 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(LD) local
915 return DAG.getExtLoad(ExtType, dl, PVT,
1132 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(LD) local
1136 SDValue NewLD = DAG.getExtLoad(ExtType, dl, PVT,
5416 ISD::NodeType ExtType) {
5427 Ops.push_back(DAG.getNode(ExtType, DL, ExtLoad->getValueType(0), SOp));
5476 ISD::LoadExtType ExtType =
5482 while (!TLI.isLoadExtLegalOrCustom(ExtType, SplitDstVT, SplitSrcVT) &&
5488 if (!TLI.isLoadExtLegalOrCustom(ExtType, SplitDstV
5414 ExtendSetCCUses(const SmallVectorImpl<SDNode *> &SetCCs, SDValue Trunc, SDValue ExtLoad, SDLoc DL, ISD::NodeType ExtType) argument
6160 ISD::LoadExtType ExtType = LN0->getExtensionType(); local
6268 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD; local
10948 ISD::LoadExtType ExtType = TLI.isLoadExtLegal(ISD::ZEXTLOAD, ResultVT, local
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/external/llvm/lib/Target/AArch64/
H A DAArch64InstrInfo.cpp1284 AArch64_AM::ShiftExtendType ExtType = AArch64_AM::getMemExtendType(Val); local
1285 return (ExtType != AArch64_AM::UXTX) || AArch64_AM::getMemDoShift(Val);
H A DAArch64ISelDAGToDAG.cpp979 ISD::LoadExtType ExtType = LD->getExtensionType(); local
984 if (ExtType == ISD::NON_EXTLOAD)
986 else if (ExtType == ISD::SEXTLOAD)
996 if (ExtType == ISD::SEXTLOAD) {
1009 if (ExtType == ISD::SEXTLOAD) {
H A DAArch64FastISel.cpp54 AArch64_AM::ShiftExtendType ExtType; member in class:__anon10636::final::Address
65 Address() : Kind(RegBase), ExtType(AArch64_AM::InvalidShiftExtend),
69 void setExtendType(AArch64_AM::ShiftExtendType E) { ExtType = E; }
70 AArch64_AM::ShiftExtendType getExtendType() const { return ExtType; }
174 AArch64_AM::ShiftExtendType ExtType,
1350 AArch64_AM::ShiftExtendType ExtType,
1383 .addImm(getArithExtendImm(ExtType, ShiftImm));
1347 emitAddSub_rx(bool UseAdd, MVT RetVT, unsigned LHSReg, bool LHSIsKill, unsigned RHSReg, bool RHSIsKill, AArch64_AM::ShiftExtendType ExtType, uint64_t ShiftImm, bool SetFlags, bool WantResult) argument
H A DAArch64ISelLowering.cpp2180 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD; local
2190 ExtType = ISD::SEXTLOAD;
2193 ExtType = ISD::ZEXTLOAD;
2196 ExtType = ISD::EXTLOAD;
2200 ArgValue = DAG.getExtLoad(ExtType, DL, VA.getLocVT(), Chain, FIN,
7653 unsigned ExtType = LHS.getOpcode(); local
7662 RHS = DAG.getNode(ExtType, SDLoc(N), VT, RHS);
7668 LHS = DAG.getNode(ExtType, SDLoc(N), VT, LHS);
8293 bool checkValueWidth(SDValue V, unsigned width, ISD::LoadExtType &ExtType) { argument
8294 ExtType
8399 isEquivalentMaskless(unsigned CC, unsigned width, ISD::LoadExtType ExtType, signed AddConstant, signed CompConstant) argument
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/external/llvm/lib/Target/AArch64/InstPrinter/
H A DAArch64InstPrinter.cpp1008 AArch64_AM::ShiftExtendType ExtType = AArch64_AM::getArithExtendType(Val); local
1014 if (ExtType == AArch64_AM::UXTW || ExtType == AArch64_AM::UXTX) {
1018 ExtType == AArch64_AM::UXTX) ||
1020 ExtType == AArch64_AM::UXTW) ) {
1026 O << ", " << AArch64_AM::getShiftExtendName(ExtType);
/external/llvm/lib/Target/Hexagon/
H A DHexagonISelDAGToDAG.cpp374 ISD::LoadExtType ExtType = LD->getExtensionType(); local
375 bool IsZeroExt = (ExtType == ISD::ZEXTLOAD || ExtType == ISD::EXTLOAD);
406 if (LD->getValueType(0) == MVT::i64 && ExtType == ISD::SEXTLOAD)
/external/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp4001 unsigned ExtType = local
4004 if (ExtType == ISD::SEXTLOAD) {
/external/llvm/lib/Target/Mips/
H A DMipsISelLowering.cpp2151 ISD::LoadExtType ExtType = LD->getExtensionType(); local
2161 if ((VT == MVT::i64) && (ExtType == ISD::NON_EXTLOAD)) {
2180 if ((VT == MVT::i32) || (ExtType == ISD::SEXTLOAD) ||
2181 (ExtType == ISD::EXTLOAD))
2184 assert((VT == MVT::i64) && (ExtType == ISD::ZEXTLOAD));
/external/llvm/lib/Target/R600/
H A DAMDGPUISelLowering.cpp1418 ISD::LoadExtType ExtType = Load->getExtensionType(); local
1422 if (ExtType == ISD::NON_EXTLOAD && VT.getSizeInBits() < 32) {
1444 ExtType == ISD::NON_EXTLOAD || Load->getMemoryVT().bitsGE(MVT::i32))
1463 if (ExtType == ISD::SEXTLOAD) {

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