Searched defs:NewMIs (Results 1 - 5 of 5) sorted by relevance

/external/llvm/include/llvm/Target/
H A DTargetInstrInfo.h606 /// @param NewMIs Set that record all MIs in the basic block up to \p
611 SmallPtrSetImpl<MachineInstr *> &NewMIs,
796 SmallVectorImpl<MachineInstr*> &NewMIs) const{
610 optimizeSelect(MachineInstr *MI, SmallPtrSetImpl<MachineInstr *> &NewMIs, bool PreferFalse = false) const argument
/external/llvm/lib/CodeGen/
H A DMachineLICM.cpp1260 SmallVector<MachineInstr *, 2> NewMIs; local
1264 NewMIs);
1269 assert(NewMIs.size() == 2 &&
1273 MBB->insert(Pos, NewMIs[0]);
1274 MBB->insert(Pos, NewMIs[1]);
1277 if (!IsLoopInvariantInst(*NewMIs[0]) || !IsProfitableToHoist(*NewMIs[0])) {
1278 NewMIs[0]->eraseFromParent();
1279 NewMIs[1]->eraseFromParent();
1284 UpdateRegPressure(NewMIs[
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H A DTwoAddressInstructionPass.cpp1272 SmallVector<MachineInstr *, 2> NewMIs; local
1275 NewMIs)) {
1279 assert(NewMIs.size() == 2 &&
1282 NewMIs[1]->addRegisterKilled(Reg, TRI);
1286 MBB->insert(mi, NewMIs[0]);
1287 MBB->insert(mi, NewMIs[1]);
1289 DEBUG(dbgs() << "2addr: NEW LOAD: " << *NewMIs[0]
1290 << "2addr: NEW INST: " << *NewMIs[1]); local
1293 unsigned NewDstIdx = NewMIs[1]->findRegisterDefOperandIdx(regA);
1294 unsigned NewSrcIdx = NewMIs[
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/external/llvm/lib/Target/PowerPC/
H A DPPCInstrInfo.cpp845 SmallVectorImpl<MachineInstr*> &NewMIs,
853 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STW))
859 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STD))
864 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STFD))
869 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STFS))
874 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::SPILL_CR))
880 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::SPILL_CRBIT))
886 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STVX))
892 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STXVD2X))
898 NewMIs
841 StoreRegToStackSlot(MachineFunction &MF, unsigned SrcReg, bool isKill, int FrameIdx, const TargetRegisterClass *RC, SmallVectorImpl<MachineInstr*> &NewMIs, bool &NonRI, bool &SpillsVRS) const argument
943 SmallVector<MachineInstr*, 4> NewMIs; local
972 LoadRegFromStackSlot(MachineFunction &MF, DebugLoc DL, unsigned DestReg, int FrameIdx, const TargetRegisterClass *RC, SmallVectorImpl<MachineInstr*> &NewMIs, bool &NonRI, bool &SpillsVRS) const argument
1050 SmallVector<MachineInstr*, 4> NewMIs; local
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/external/llvm/lib/Target/ARM/
H A DARMBaseInstrInfo.cpp214 std::vector<MachineInstr*> NewMIs; local
224 NewMIs.push_back(MemMI);
225 NewMIs.push_back(UpdateMI);
237 NewMIs.push_back(UpdateMI);
238 NewMIs.push_back(MemMI);
257 MachineInstr *NewMI = NewMIs[j];
270 MFI->insert(MBBI, NewMIs[1]);
271 MFI->insert(MBBI, NewMIs[0]);
272 return NewMIs[0];

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