Searched defs:Reg (Results 1 - 25 of 254) sorted by relevance

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/external/llvm/lib/MC/
H A DMCRegisterInfo.cpp18 unsigned MCRegisterInfo::getMatchingSuperReg(unsigned Reg, unsigned SubIdx, argument
20 for (MCSuperRegIterator Supers(Reg, this); Supers.isValid(); ++Supers)
21 if (RC->contains(*Supers) && Reg == getSubReg(*Supers, SubIdx))
26 unsigned MCRegisterInfo::getSubReg(unsigned Reg, unsigned Idx) const { argument
31 const uint16_t *SRI = SubRegIndices + get(Reg).SubRegIndices;
32 for (MCSubRegIterator Subs(Reg, this); Subs.isValid(); ++Subs, ++SRI)
38 unsigned MCRegisterInfo::getSubRegIndex(unsigned Reg, unsigned SubReg) const {
42 const uint16_t *SRI = SubRegIndices + get(Reg).SubRegIndices;
43 for (MCSubRegIterator Subs(Reg, this); Subs.isValid(); ++Subs, ++SRI)
/external/llvm/lib/Target/Mips/MCTargetDesc/
H A DMipsOptionRecord.cpp67 void MipsRegInfoRecord::SetPhysRegUsed(unsigned Reg, argument
71 for (MCSubRegIterator SubRegIt(Reg, MCRegInfo, true); SubRegIt.isValid();
H A DMipsELFStreamer.cpp31 unsigned Reg = Op.getReg(); local
32 RegInfoRecord->SetPhysRegUsed(Reg, MCRegInfo);
/external/llvm/lib/Target/PowerPC/
H A DPPCRegisterInfo.h27 unsigned Reg = 0; local
30 Reg = PPC::CR0;
33 Reg = PPC::CR1;
36 Reg = PPC::CR2;
39 Reg = PPC::CR3;
42 Reg = PPC::CR4;
45 Reg = PPC::CR5;
48 Reg = PPC::CR6;
51 Reg = PPC::CR7;
53 assert(Reg !
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H A DPPCVSXCopy.cpp57 bool IsRegInClass(unsigned Reg, const TargetRegisterClass *RC, argument
59 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
60 return RC->hasSubClassEq(MRI.getRegClass(Reg));
61 } else if (RC->contains(Reg)) {
68 bool IsVSReg(unsigned Reg, MachineRegisterInfo &MRI) { argument
69 return IsRegInClass(Reg, &PPC::VSRCRegClass, MRI);
72 bool IsVRReg(unsigned Reg, MachineRegisterInfo &MRI) { argument
73 return IsRegInClass(Reg, &PPC::VRRCRegClass, MRI);
76 bool IsF8Reg(unsigned Reg, MachineRegisterInfo &MRI) { argument
77 return IsRegInClass(Reg,
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/external/llvm/include/llvm/MC/
H A DMCInstBuilder.h32 MCInstBuilder &addReg(unsigned Reg) { argument
33 Inst.addOperand(MCOperand::CreateReg(Reg));
H A DMCWin64EH.h28 static WinEH::Instruction PushNonVol(MCSymbol *L, unsigned Reg) { argument
29 return WinEH::Instruction(Win64EH::UOP_PushNonVol, L, Reg, -1);
38 static WinEH::Instruction SaveNonVol(MCSymbol *L, unsigned Reg, argument
42 L, Reg, Offset);
44 static WinEH::Instruction SaveXMM(MCSymbol *L, unsigned Reg, argument
48 L, Reg, Offset);
50 static WinEH::Instruction SetFPReg(MCSymbol *L, unsigned Reg, unsigned Off) { argument
51 return WinEH::Instruction(UOP_SetFPReg, L, Reg, Off);
H A DMCWinEH.h29 Instruction(unsigned Op, MCSymbol *L, unsigned Reg, unsigned Off) argument
30 : Label(L), Offset(Off), Register(Reg), Operation(Op) {}
/external/llvm/lib/CodeGen/
H A DAllocationOrder.h54 unsigned Reg = Order[Pos++]; local
55 if (!isHint(Reg))
56 return Reg;
H A DLivePhysRegs.cpp43 unsigned Reg = O->getReg(); local
44 if (Reg == 0)
46 removeReg(Reg);
55 unsigned Reg = O->getReg(); local
56 if (Reg == 0)
58 addReg(Reg);
71 unsigned Reg = O->getReg(); local
72 if (Reg == 0)
76 Defs.push_back(Reg);
81 removeReg(Reg);
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H A DDeadMachineInstructionElim.cpp75 unsigned Reg = MO.getReg(); local
76 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
78 if (LivePhysRegs.test(Reg) || MRI->isReserved(Reg))
81 if (!MRI->use_nodbg_empty(Reg))
145 unsigned Reg = MO.getReg(); local
146 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
150 for (MCSubRegIterator SR(Reg, TRI,/*IncludeSelf=*/true);
164 unsigned Reg = MO.getReg(); local
165 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
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H A DRegAllocBase.cpp75 unsigned Reg = TargetRegisterInfo::index2VirtReg(i); local
76 if (MRI->reg_nodbg_empty(Reg))
78 enqueue(&LIS->getInterval(Reg));
H A DProcessImplicitDefs.cpp79 unsigned Reg = MI->getOperand(0).getReg(); local
81 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
84 for (MachineOperand &MO : MRI->use_nodbg_operands(Reg)) {
108 !TRI->regsOverlap(Reg, UserReg))
110 // UserMI uses or redefines Reg. Set <undef> flags on all uses.
/external/llvm/lib/Target/SystemZ/MCTargetDesc/
H A DSystemZMCTargetDesc.h55 unsigned getFirstReg(unsigned Reg);
58 inline unsigned getRegAsGR64(unsigned Reg) { argument
59 return GR64Regs[getFirstReg(Reg)];
63 inline unsigned getRegAsGR32(unsigned Reg) { argument
64 return GR32Regs[getFirstReg(Reg)];
68 inline unsigned getRegAsGRH32(unsigned Reg) { argument
69 return GRH32Regs[getFirstReg(Reg)];
/external/llvm/lib/Target/XCore/
H A DXCoreFrameToArgsOffsetElim.cpp56 unsigned Reg = OldInst->getOperand(0).getReg(); local
57 MBBI = TII.loadImmediate(MBB, MBBI, Reg, StackSize);
/external/llvm/lib/Target/AArch64/
H A DAArch64DeadRegisterDefinitionsPass.cpp33 bool implicitlyDefinesOverlappingReg(unsigned Reg, const MachineInstr &MI);
53 unsigned Reg, const MachineInstr &MI) {
56 if (TRI->regsOverlap(Reg, MO.getReg()))
52 implicitlyDefinesOverlappingReg( unsigned Reg, const MachineInstr &MI) argument
/external/llvm/lib/Target/ARM/
H A DARMBaseRegisterInfo.h34 static inline bool isARMArea1Register(unsigned Reg, bool isIOS) { argument
36 switch (Reg) {
49 static inline bool isARMArea2Register(unsigned Reg, bool isIOS) { argument
51 switch (Reg) {
60 static inline bool isARMArea3Register(unsigned Reg, bool isIOS) { argument
62 switch (Reg) {
71 static inline bool isCalleeSavedRegister(unsigned Reg, argument
74 if (Reg == CSRegs[i])
131 void updateRegAllocHint(unsigned Reg, unsigned NewReg,
155 bool isLowRegister(unsigned Reg) cons
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/external/llvm/lib/Target/Sparc/
H A DSparcMachineFunctionInfo.h43 void setGlobalBaseReg(unsigned Reg) { GlobalBaseReg = Reg; } argument
49 void setSRetReturnReg(unsigned Reg) { SRetReturnReg = Reg; } argument
/external/llvm/lib/Target/SystemZ/
H A DSystemZShortenInst.cpp78 unsigned Reg = MI.getOperand(0).getReg(); local
79 assert(Reg < SystemZ::NUM_TARGET_REGS && "Invalid register number");
80 unsigned GPRs = GPRMap[Reg];
88 MI.getOperand(0).setReg(SystemZMC::getRegAsGR64(Reg));
93 MI.getOperand(0).setReg(SystemZMC::getRegAsGR64(Reg));
110 unsigned Reg = *LI;
111 assert(Reg < SystemZ::NUM_TARGET_REGS && "Invalid register number");
112 LiveLow |= LowGPRs[Reg];
113 LiveHigh |= HighGPRs[Reg];
133 if (unsigned Reg
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/external/llvm/include/llvm/CodeGen/
H A DLivePhysRegs.h74 void addReg(unsigned Reg) { argument
76 assert(Reg <= TRI->getNumRegs() && "Expected a physical register.");
77 for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true);
84 void removeReg(unsigned Reg) { argument
86 assert(Reg <= TRI->getNumRegs() && "Expected a physical register.");
87 for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true);
90 for (MCSuperRegIterator SuperRegs(Reg, TRI, /*IncludeSelf=*/false);
98 /// \brief Returns true if register @p Reg is contained in the set. This also
99 /// works if only the super register of @p Reg has been defined, because we
101 bool contains(unsigned Reg) cons
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H A DLiveVariables.h106 /// isLiveIn - Is Reg live in to MBB? This means that Reg is live through
107 /// MBB, or it is killed in MBB. If Reg is only used by PHI instructions in
110 unsigned Reg,
150 /// HandlePhysRegKill - Add kills of Reg and its sub-registers to the
153 bool HandlePhysRegKill(unsigned Reg, MachineInstr *MI);
158 void HandlePhysRegUse(unsigned Reg, MachineInstr *MI);
159 void HandlePhysRegDef(unsigned Reg, MachineInstr *MI,
165 MachineInstr *FindLastRefOrPartRef(unsigned Reg);
170 MachineInstr *FindLastPartialDef(unsigned Reg,
285 isLiveIn(unsigned Reg, const MachineBasicBlock &MBB) argument
303 isPHIJoin(unsigned Reg) argument
306 setPHIJoin(unsigned Reg) argument
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/external/llvm/lib/DebugInfo/PDB/
H A DPDBExtras.cpp94 raw_ostream &llvm::operator<<(raw_ostream &OS, const PDB_RegisterId &Reg) { argument
95 switch (Reg) {
144 OS << static_cast<int>(Reg);
/external/llvm/lib/Target/R600/
H A DSIFixSGPRLiveRanges.cpp161 unsigned Reg = RegLR.first; local
186 .addReg(Reg, RegState::Implicit);
H A DSILowerI1Copies.cpp89 unsigned Reg = MI.getOperand(0).getReg(); local
90 const TargetRegisterClass *RC = MRI.getRegClass(Reg);
92 MRI.setRegClass(Reg, &AMDGPU::SReg_64RegClass);
147 for (unsigned Reg : I1Defs)
148 MRI.setRegClass(Reg, &AMDGPU::VGPR_32RegClass);
H A DSIMachineFunctionInfo.h56 void setTIDReg(unsigned Reg) { TIDReg = Reg; } argument

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