/external/llvm/lib/Target/Hexagon/ |
H A D | HexagonPeephole.cpp | 159 MachineOperand &Src2 = MI->getOperand(2); local 163 unsigned SrcReg = Src2.getReg(); 176 MachineOperand &Src2 = MI->getOperand(2); local 177 if (Src2.getImm() != 32)
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/external/llvm/lib/Target/R600/ |
H A D | SIShrinkInstructions.cpp | 90 const MachineOperand *Src2 = TII->getNamedOperand(MI, AMDGPU::OpName::src2); local 97 if (Src2)
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H A D | SIInstrInfo.cpp | 920 MachineOperand *Src2 = getNamedOperand(*UseMI, AMDGPU::OpName::src2); local 929 if (!Src2->isReg() || 930 (Src2->isReg() && RI.isSGPRClass(MRI->getRegClass(Src2->getReg())))) 955 unsigned Src2Reg = Src2->getReg(); 956 unsigned Src2SubReg = Src2->getSubReg(); 962 Src2->ChangeToImmediate(Imm); 975 if (Src2->isReg() && Src2->getReg() == Reg) { 997 Src2 [all...] |
/external/llvm/lib/ExecutionEngine/Interpreter/ |
H A D | Execution.cpp | 52 Dest.TY##Val = Src1.TY##Val OP Src2.TY##Val; \ 56 GenericValue Src2, Type *Ty) { 67 GenericValue Src2, Type *Ty) { 78 GenericValue Src2, Type *Ty) { 89 GenericValue Src2, Type *Ty) { 100 GenericValue Src2, Type *Ty) { 103 Dest.FloatVal = fmod(Src1.FloatVal, Src2.FloatVal); 106 Dest.DoubleVal = fmod(Src1.DoubleVal, Src2.DoubleVal); 116 Dest.IntVal = APInt(1,Src1.IntVal.OP(Src2.IntVal)); \ 121 assert(Src1.AggregateVal.size() == Src2 55 executeFAddInst(GenericValue &Dest, GenericValue Src1, GenericValue Src2, Type *Ty) argument 66 executeFSubInst(GenericValue &Dest, GenericValue Src1, GenericValue Src2, Type *Ty) argument 77 executeFMulInst(GenericValue &Dest, GenericValue Src1, GenericValue Src2, Type *Ty) argument 88 executeFDivInst(GenericValue &Dest, GenericValue Src1, GenericValue Src2, Type *Ty) argument 99 executeFRemInst(GenericValue &Dest, GenericValue Src1, GenericValue Src2, Type *Ty) argument 138 executeICMP_EQ(GenericValue Src1, GenericValue Src2, Type *Ty) argument 152 executeICMP_NE(GenericValue Src1, GenericValue Src2, Type *Ty) argument 166 executeICMP_ULT(GenericValue Src1, GenericValue Src2, Type *Ty) argument [all...] |
/external/llvm/lib/Target/SystemZ/ |
H A D | SystemZSelectionDAGInfo.cpp | 156 // Use CLC to compare [Src1, Src1 + Size) with [Src2, Src2 + Size), 159 SDValue Src1, SDValue Src2, uint64_t Size) { 171 return DAG.getNode(SystemZISD::CLC_LOOP, DL, VTs, Chain, Src1, Src2, 174 return DAG.getNode(SystemZISD::CLC, DL, VTs, Chain, Src1, Src2, 193 SDValue Src1, SDValue Src2, SDValue Size, 199 Chain = emitCLC(DAG, DL, Chain, Src1, Src2, Bytes); 246 SDValue Src1, SDValue Src2, 250 SDValue Unused = DAG.getNode(SystemZISD::STRCMP, DL, VTs, Chain, Src1, Src2, 158 emitCLC(SelectionDAG &DAG, SDLoc DL, SDValue Chain, SDValue Src1, SDValue Src2, uint64_t Size) argument 192 EmitTargetCodeForMemcmp(SelectionDAG &DAG, SDLoc DL, SDValue Chain, SDValue Src1, SDValue Src2, SDValue Size, MachinePointerInfo Op1PtrInfo, MachinePointerInfo Op2PtrInfo) const argument 245 EmitTargetCodeForStrcmp(SelectionDAG &DAG, SDLoc DL, SDValue Chain, SDValue Src1, SDValue Src2, MachinePointerInfo Op1PtrInfo, MachinePointerInfo Op2PtrInfo) const argument
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H A D | SystemZISelLowering.cpp | 2495 SDValue Src2 = Node->getVal(); local 2502 if (auto *Const = dyn_cast<ConstantSDNode>(Src2)) { 2504 Src2 = DAG.getConstant(-Const->getSExtValue(), Src2.getValueType()); 2528 Src2 = DAG.getNode(ISD::SHL, DL, WideVT, Src2, 2532 Src2 = DAG.getNode(ISD::OR, DL, WideVT, Src2, 2537 SDValue Ops[] = { ChainIn, AlignedAddr, Src2, BitShift, NegBitShift, 2562 SDValue Src2 local 3044 MachineOperand Src2 = earlyUseOperand(MI->getOperand(3)); local 3163 unsigned Src2 = MI->getOperand(3).getReg(); local [all...] |
/external/llvm/lib/Target/X86/ |
H A D | X86FixupLEAs.cpp | 305 const MachineOperand &Src2 = MI->getOperand(SrcR1 == DstR ? 3 : 1); local 309 .addOperand(Src2);
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H A D | X86InstrInfo.cpp | 2612 unsigned Src2 = MI->getOperand(2).getReg(); local 2616 if (Src == Src2) { 2631 .addReg(Src2, getKillRegState(isKill2)); 2635 LV->replaceKillInstruction(Src2, MI, InsMI2); 2828 const MachineOperand &Src2 = MI->getOperand(2); local 2832 if (!classifyLEAReg(MI, Src2, Opc, /*AllowSP=*/ false, 2849 if (LV && Src2.isKill()) 2859 unsigned Src2 = MI->getOperand(2).getReg(); local 2863 Src.getReg(), Src.isKill(), Src2, isKill2); 2872 LV->replaceKillInstruction(Src2, M [all...] |
H A D | X86ISelLowering.cpp | 14735 SDValue Src2 = Op.getOperand(2); local 14743 return getScalarMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src1, Src2, 14750 return getScalarMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Src1, Src2, 14756 SDValue Src2 = Op.getOperand(2); local 14769 Src1, Src2, Rnd), 14774 Src1,Src2), 14779 SDValue Src2 = Op.getOperand(2); local 14792 Src1, Src2, Src3, Rnd), 14797 Src1, Src2, Src3),
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/external/llvm/lib/Target/Sparc/ |
H A D | SparcAsmPrinter.cpp | 132 MCOperand &RS1, MCOperand &Src2, MCOperand &RD, 139 Inst.addOperand(Src2); 131 EmitBinary(MCStreamer &OutStreamer, unsigned Opcode, MCOperand &RS1, MCOperand &Src2, MCOperand &RD, const MCSubtargetInfo &STI) argument
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H A D | SparcISelLowering.cpp | 2684 SDValue Src2 = Op.getOperand(1); local 2685 SDValue Src2Lo = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Src2); 2686 SDValue Src2Hi = DAG.getNode(ISD::SRL, dl, MVT::i64, Src2,
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/external/clang/lib/CodeGen/ |
H A D | CGBuiltin.cpp | 6395 llvm::Value *Src2 = CGF.EmitScalarExpr(E->getArg(2)); local 6398 return CGF.Builder.CreateCall3(F, Src0, Src1, Src2); 6447 llvm::Value *Src2 = EmitScalarExpr(E->getArg(2)); local 6453 return Builder.CreateCall4(F, Src0, Src1, Src2, Src3ToBool);
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/external/llvm/lib/Target/PowerPC/ |
H A D | PPCISelLowering.cpp | 8794 unsigned Src2 = MI->getOperand(2).getReg(); local 8808 BuildMI(*BB, MI, dl, TII->get(PPC::FADD), Dest).addReg(Src1).addReg(Src2);
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