1//===-- SIShrinkInstructions.cpp - Shrink Instructions --------------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8/// The pass tries to use the 32-bit encoding for instructions when possible.
9//===----------------------------------------------------------------------===//
10//
11
12#include "AMDGPU.h"
13#include "AMDGPUMCInstLower.h"
14#include "AMDGPUSubtarget.h"
15#include "SIInstrInfo.h"
16#include "llvm/ADT/Statistic.h"
17#include "llvm/CodeGen/MachineFunctionPass.h"
18#include "llvm/CodeGen/MachineInstrBuilder.h"
19#include "llvm/CodeGen/MachineRegisterInfo.h"
20#include "llvm/IR/Constants.h"
21#include "llvm/IR/Function.h"
22#include "llvm/IR/LLVMContext.h"
23#include "llvm/Support/Debug.h"
24#include "llvm/Support/raw_ostream.h"
25#include "llvm/Target/TargetMachine.h"
26
27#define DEBUG_TYPE "si-shrink-instructions"
28
29STATISTIC(NumInstructionsShrunk,
30          "Number of 64-bit instruction reduced to 32-bit.");
31STATISTIC(NumLiteralConstantsFolded,
32          "Number of literal constants folded into 32-bit instructions.");
33
34namespace llvm {
35  void initializeSIShrinkInstructionsPass(PassRegistry&);
36}
37
38using namespace llvm;
39
40namespace {
41
42class SIShrinkInstructions : public MachineFunctionPass {
43public:
44  static char ID;
45
46public:
47  SIShrinkInstructions() : MachineFunctionPass(ID) {
48  }
49
50  bool runOnMachineFunction(MachineFunction &MF) override;
51
52  const char *getPassName() const override {
53    return "SI Shrink Instructions";
54  }
55
56  void getAnalysisUsage(AnalysisUsage &AU) const override {
57    AU.setPreservesCFG();
58    MachineFunctionPass::getAnalysisUsage(AU);
59  }
60};
61
62} // End anonymous namespace.
63
64INITIALIZE_PASS_BEGIN(SIShrinkInstructions, DEBUG_TYPE,
65                      "SI Lower il Copies", false, false)
66INITIALIZE_PASS_END(SIShrinkInstructions, DEBUG_TYPE,
67                    "SI Lower il Copies", false, false)
68
69char SIShrinkInstructions::ID = 0;
70
71FunctionPass *llvm::createSIShrinkInstructionsPass() {
72  return new SIShrinkInstructions();
73}
74
75static bool isVGPR(const MachineOperand *MO, const SIRegisterInfo &TRI,
76                   const MachineRegisterInfo &MRI) {
77  if (!MO->isReg())
78    return false;
79
80  if (TargetRegisterInfo::isVirtualRegister(MO->getReg()))
81    return TRI.hasVGPRs(MRI.getRegClass(MO->getReg()));
82
83  return TRI.hasVGPRs(TRI.getPhysRegClass(MO->getReg()));
84}
85
86static bool canShrink(MachineInstr &MI, const SIInstrInfo *TII,
87                      const SIRegisterInfo &TRI,
88                      const MachineRegisterInfo &MRI) {
89
90  const MachineOperand *Src2 = TII->getNamedOperand(MI, AMDGPU::OpName::src2);
91  // Can't shrink instruction with three operands.
92  // FIXME: v_cndmask_b32 has 3 operands and is shrinkable, but we need to add
93  // a special case for it.  It can only be shrunk if the third operand
94  // is vcc.  We should handle this the same way we handle vopc, by addding
95  // a register allocation hint pre-regalloc and then do the shrining
96  // post-regalloc.
97  if (Src2)
98    return false;
99
100  const MachineOperand *Src1 = TII->getNamedOperand(MI, AMDGPU::OpName::src1);
101  const MachineOperand *Src1Mod =
102      TII->getNamedOperand(MI, AMDGPU::OpName::src1_modifiers);
103
104  if (Src1 && (!isVGPR(Src1, TRI, MRI) || (Src1Mod && Src1Mod->getImm() != 0)))
105    return false;
106
107  // We don't need to check src0, all input types are legal, so just make sure
108  // src0 isn't using any modifiers.
109  if (TII->hasModifiersSet(MI, AMDGPU::OpName::src0_modifiers))
110    return false;
111
112  // Check output modifiers
113  if (TII->hasModifiersSet(MI, AMDGPU::OpName::omod))
114    return false;
115
116  if (TII->hasModifiersSet(MI, AMDGPU::OpName::clamp))
117    return false;
118
119  return true;
120}
121
122/// \brief This function checks \p MI for operands defined by a move immediate
123/// instruction and then folds the literal constant into the instruction if it
124/// can.  This function assumes that \p MI is a VOP1, VOP2, or VOPC instruction
125/// and will only fold literal constants if we are still in SSA.
126static void foldImmediates(MachineInstr &MI, const SIInstrInfo *TII,
127                           MachineRegisterInfo &MRI, bool TryToCommute = true) {
128
129  if (!MRI.isSSA())
130    return;
131
132  assert(TII->isVOP1(MI.getOpcode()) || TII->isVOP2(MI.getOpcode()) ||
133         TII->isVOPC(MI.getOpcode()));
134
135  const SIRegisterInfo &TRI = TII->getRegisterInfo();
136  int Src0Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::src0);
137  MachineOperand &Src0 = MI.getOperand(Src0Idx);
138
139  // Only one literal constant is allowed per instruction, so if src0 is a
140  // literal constant then we can't do any folding.
141  if (Src0.isImm() &&
142      TII->isLiteralConstant(Src0, TII->getOpSize(MI, Src0Idx)))
143    return;
144
145  // Literal constants and SGPRs can only be used in Src0, so if Src0 is an
146  // SGPR, we cannot commute the instruction, so we can't fold any literal
147  // constants.
148  if (Src0.isReg() && !isVGPR(&Src0, TRI, MRI))
149    return;
150
151  // Try to fold Src0
152  if (Src0.isReg()) {
153    unsigned Reg = Src0.getReg();
154    MachineInstr *Def = MRI.getUniqueVRegDef(Reg);
155    if (Def && Def->isMoveImmediate()) {
156      MachineOperand &MovSrc = Def->getOperand(1);
157      bool ConstantFolded = false;
158
159      if (MovSrc.isImm() && isUInt<32>(MovSrc.getImm())) {
160        Src0.ChangeToImmediate(MovSrc.getImm());
161        ConstantFolded = true;
162      }
163      if (ConstantFolded) {
164        if (MRI.use_empty(Reg))
165          Def->eraseFromParent();
166        ++NumLiteralConstantsFolded;
167        return;
168      }
169    }
170  }
171
172  // We have failed to fold src0, so commute the instruction and try again.
173  if (TryToCommute && MI.isCommutable() && TII->commuteInstruction(&MI))
174    foldImmediates(MI, TII, MRI, false);
175
176}
177
178bool SIShrinkInstructions::runOnMachineFunction(MachineFunction &MF) {
179  MachineRegisterInfo &MRI = MF.getRegInfo();
180  const SIInstrInfo *TII =
181      static_cast<const SIInstrInfo *>(MF.getSubtarget().getInstrInfo());
182  const SIRegisterInfo &TRI = TII->getRegisterInfo();
183  std::vector<unsigned> I1Defs;
184
185  for (MachineFunction::iterator BI = MF.begin(), BE = MF.end();
186                                                  BI != BE; ++BI) {
187
188    MachineBasicBlock &MBB = *BI;
189    MachineBasicBlock::iterator I, Next;
190    for (I = MBB.begin(); I != MBB.end(); I = Next) {
191      Next = std::next(I);
192      MachineInstr &MI = *I;
193
194      // Try to use S_MOVK_I32, which will save 4 bytes for small immediates.
195      if (MI.getOpcode() == AMDGPU::S_MOV_B32) {
196        const MachineOperand &Src = MI.getOperand(1);
197
198        if (Src.isImm()) {
199          if (isInt<16>(Src.getImm()) && !TII->isInlineConstant(Src, 4))
200            MI.setDesc(TII->get(AMDGPU::S_MOVK_I32));
201        }
202
203        continue;
204      }
205
206      if (!TII->hasVALU32BitEncoding(MI.getOpcode()))
207        continue;
208
209      if (!canShrink(MI, TII, TRI, MRI)) {
210        // Try commuting the instruction and see if that enables us to shrink
211        // it.
212        if (!MI.isCommutable() || !TII->commuteInstruction(&MI) ||
213            !canShrink(MI, TII, TRI, MRI))
214          continue;
215      }
216
217      // getVOPe32 could be -1 here if we started with an instruction that had
218      // a 32-bit encoding and then commuted it to an instruction that did not.
219      if (!TII->hasVALU32BitEncoding(MI.getOpcode()))
220        continue;
221
222      int Op32 = AMDGPU::getVOPe32(MI.getOpcode());
223
224      if (TII->isVOPC(Op32)) {
225        unsigned DstReg = MI.getOperand(0).getReg();
226        if (TargetRegisterInfo::isVirtualRegister(DstReg)) {
227          // VOPC instructions can only write to the VCC register.  We can't
228          // force them to use VCC here, because the register allocator has
229          // trouble with sequences like this, which cause the allocator to run
230          // out of registers if vreg0 and vreg1 belong to the VCCReg register
231          // class:
232          // vreg0 = VOPC;
233          // vreg1 = VOPC;
234          // S_AND_B64 vreg0, vreg1
235          //
236          // So, instead of forcing the instruction to write to VCC, we provide
237          // a hint to the register allocator to use VCC and then we we will run
238          // this pass again after RA and shrink it if it outputs to VCC.
239          MRI.setRegAllocationHint(MI.getOperand(0).getReg(), 0, AMDGPU::VCC);
240          continue;
241        }
242        if (DstReg != AMDGPU::VCC)
243          continue;
244      }
245
246      // We can shrink this instruction
247      DEBUG(dbgs() << "Shrinking "; MI.dump(); dbgs() << '\n';);
248
249      MachineInstrBuilder Inst32 =
250          BuildMI(MBB, I, MI.getDebugLoc(), TII->get(Op32));
251
252      // dst
253      Inst32.addOperand(MI.getOperand(0));
254
255      Inst32.addOperand(*TII->getNamedOperand(MI, AMDGPU::OpName::src0));
256
257      const MachineOperand *Src1 =
258          TII->getNamedOperand(MI, AMDGPU::OpName::src1);
259      if (Src1)
260        Inst32.addOperand(*Src1);
261
262      ++NumInstructionsShrunk;
263      MI.eraseFromParent();
264
265      foldImmediates(*Inst32, TII, MRI);
266      DEBUG(dbgs() << "e32 MI = " << *Inst32 << '\n');
267
268
269    }
270  }
271  return false;
272}
273