H A D | assembler_mips64.cc | 71 void Mips64Assembler::EmitFR(int opcode, int fmt, FpuRegister ft, FpuRegister fs, FpuRegister fd, argument 74 CHECK_NE(fs, kNoFpuRegister); 79 static_cast<uint32_t>(fs) << kFsShift | 514 void Mips64Assembler::AddS(FpuRegister fd, FpuRegister fs, FpuRegister ft) { argument 515 EmitFR(0x11, 0x10, ft, fs, fd, 0x0); 518 void Mips64Assembler::SubS(FpuRegister fd, FpuRegister fs, FpuRegister ft) { argument 519 EmitFR(0x11, 0x10, ft, fs, fd, 0x1); 522 void Mips64Assembler::MulS(FpuRegister fd, FpuRegister fs, FpuRegister ft) { argument 523 EmitFR(0x11, 0x10, ft, fs, fd, 0x2); 526 void Mips64Assembler::DivS(FpuRegister fd, FpuRegister fs, FpuRegiste argument 530 AddD(FpuRegister fd, FpuRegister fs, FpuRegister ft) argument 534 SubD(FpuRegister fd, FpuRegister fs, FpuRegister ft) argument 538 MulD(FpuRegister fd, FpuRegister fs, FpuRegister ft) argument 542 DivD(FpuRegister fd, FpuRegister fs, FpuRegister ft) argument 546 MovS(FpuRegister fd, FpuRegister fs) argument 550 MovD(FpuRegister fd, FpuRegister fs) argument 554 NegS(FpuRegister fd, FpuRegister fs) argument 558 NegD(FpuRegister fd, FpuRegister fs) argument 562 Cvtsw(FpuRegister fd, FpuRegister fs) argument 566 Cvtdw(FpuRegister fd, FpuRegister fs) argument 570 Cvtsd(FpuRegister fd, FpuRegister fs) argument 574 Cvtds(FpuRegister fd, FpuRegister fs) argument 578 Mfc1(GpuRegister rt, FpuRegister fs) argument 582 Mtc1(GpuRegister rt, FpuRegister fs) argument 586 Dmfc1(GpuRegister rt, FpuRegister fs) argument 590 Dmtc1(GpuRegister rt, FpuRegister fs) argument [all...] |