| /external/llvm/lib/Target/ARM/ |
| H A D | ThumbRegisterInfo.cpp | 135 bool isSub = false; local
141 isSub = true;
163 int Opc = (isSub) ? ARM::tSUBrr : ((isHigh || !CanChangeCC) ? ARM::tADDhirr
169 if (DestReg == ARM::SP || isSub)
187 bool isSub = NumBytes < 0; local
189 if (isSub) Bytes = -NumBytes;
222 ExtraOpc = isSub ? ARM::tSUBspi : ARM::tADDspi;
228 assert(!isSub && "Thumb1 does not have tSUBrSPi");
237 CopyOpc = isSub ? ARM::tSUBi3 : ARM::tADDi3;
245 ExtraOpc = isSub
[all...] |
| H A D | ARMBaseInstrInfo.cpp | 171 bool isSub = ARM_AM::getAM2Op(OffImm) == ARM_AM::sub; local
179 get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
186 get(isSub ? ARM::SUBrsi : ARM::ADDrsi), WBReg)
191 get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg)
197 bool isSub = ARM_AM::getAM3Op(OffImm) == ARM_AM::sub; local
202 get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
207 get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg)
1958 bool isSub = NumBytes < 0; local
1959 if (isSub) NumBytes = -NumBytes;
1972 unsigned Opc = isSub
2106 bool isSub = false; local
2737 bool isSub = ARM_AM::getAM2Op(ShOpVal) == ARM_AM::sub; local
2753 bool isSub = ARM_AM::getAM2Op(ShOpVal) == ARM_AM::sub; local
2781 bool isSub = ARM_AM::getAM2Op(ShOpVal) == ARM_AM::sub; local
2794 bool isSub = ARM_AM::getAM2Op(ShOpVal) == ARM_AM::sub; local
2846 bool isSub = ARM_AM::getAM2Op(ShOpVal) == ARM_AM::sub; local
3469 bool isSub = ARM_AM::getAM2Op(ShOpVal) == ARM_AM::sub; local
[all...] |
| H A D | ARMISelLowering.cpp | 7325 bool isSub = ARM_AM::getAM2Op(Offset) == ARM_AM::sub; local
7327 if (isSub)
|
| /external/llvm/lib/Target/X86/ |
| H A D | X86FrameLowering.cpp | 213 bool isSub = NumBytes < 0; local
214 uint64_t Offset = isSub ? -NumBytes : NumBytes;
219 Opc = isSub
232 if (isSub && !isEAXLiveIn(*MBB.getParent()))
241 Opc = isSub
256 unsigned Reg = isSub
260 Opc = isSub
264 .addReg(Reg, getDefRegState(!isSub) | getUndefRegState(isSub));
265 if (isSub)
[all...] |
| /external/llvm/lib/Transforms/InstCombine/ |
| H A D | InstCombineAndOrXor.cpp | 360 /// where isSub determines whether the operator is a sub. If we can fold one of
370 ConstantInt *Mask, bool isSub,
410 if (isSub)
369 FoldLogicalPlusAnd(Value *LHS, Value *RHS, ConstantInt *Mask, bool isSub, Instruction &I) argument
|
| /external/clang/lib/CodeGen/ |
| H A D | CGExprScalar.cpp | 2545 bool isSub=false) {
2565 return buildFMulAdd(LHSBinOp, op.RHS, CGF, Builder, false, isSub);
2572 return buildFMulAdd(RHSBinOp, op.LHS, CGF, Builder, isSub, false);
2543 tryEmitFMulAdd(const BinOpInfo &op, const CodeGenFunction &CGF, CGBuilderTy &Builder, bool isSub=false) argument
|
| /external/valgrind/VEX/priv/ |
| H A D | guest_arm_toIR.c | 18597 UInt isSub = INSN0(9,9); local
18602 putIRegT(rD, binop(isSub ? Iop_Sub32 : Iop_Add32,
18605 setFlags_D1_D2( isSub ? ARMG_CC_OP_SUB : ARMG_CC_OP_ADD,
18607 DIP("%s r%u, r%u, #%u\n", isSub ? "subs" : "adds", rD, rN, uimm3);
18618 UInt isSub = INSN0(9,9); local
18623 putIRegT( rD, binop(isSub ? Iop_Sub32 : Iop_Add32,
18626 setFlags_D1_D2( isSub ? ARMG_CC_OP_SUB : ARMG_CC_OP_ADD,
18628 DIP("%s r%u, r%u, r%u\n", isSub ? "subs" : "adds", rD, rN, rM);
18757 UInt isSub = INSN0(11,11); local
18764 putIRegT( rN, binop(isSub
[all...] |
| H A D | guest_arm64_toIR.c | 2406 Bool isSub = INSN(30,30) == 1; local
2412 const HChar* nm = isSub ? "sub" : "add";
2424 assign(res, binop(isSub ? Iop_Sub64 : Iop_Add64,
2428 setFlags_ADD_SUB(True/*is64*/, isSub, argL, argR);
2442 assign(res, binop(isSub ? Iop_Sub32 : Iop_Add32,
2446 setFlags_ADD_SUB(False/*!is64*/, isSub, argL, argR);
3097 Bool isSub = INSN(30,30) == 1; local
3150 assign(res, binop(isSub ? Iop_Sub64 : Iop_Add64,
3155 setFlags_ADD_SUB(True/*is64*/, isSub, argL, argR);
3166 setFlags_ADD_SUB(False/*!is64*/, isSub, argL3
[all...] |