/art/compiler/utils/x86/ |
H A D | assembler_x86.h | 54 Register rm() const { function in class:art::x86::Operand 622 inline void EmitRegisterOperand(int rm, int reg); 623 inline void EmitXmmRegisterOperand(int rm, XmmRegister reg); 627 void EmitOperand(int rm, const Operand& operand); 629 void EmitComplex(int rm, const Operand& operand, const Immediate& immediate); 634 void EmitGenericShift(int rm, const Operand& operand, const Immediate& imm); 635 void EmitGenericShift(int rm, const Operand& operand, Register shifter); 648 inline void X86Assembler::EmitRegisterOperand(int rm, int reg) { argument 649 CHECK_GE(rm, 0); 650 CHECK_LT(rm, 654 EmitXmmRegisterOperand(int rm, XmmRegister reg) argument [all...] |
/art/compiler/utils/x86_64/ |
H A D | assembler_x86_64.h | 63 Register rm() const { function in class:art::x86_64::Operand 774 void EmitRegisterOperand(uint8_t rm, uint8_t reg); 775 void EmitXmmRegisterOperand(uint8_t rm, XmmRegister reg); 779 void EmitOperand(uint8_t rm, const Operand& operand); 781 void EmitComplex(uint8_t rm, const Operand& operand, const Immediate& immediate); 786 void EmitGenericShift(bool wide, int rm, CpuRegister reg, const Immediate& imm); 787 void EmitGenericShift(bool wide, int rm, CpuRegister operand, CpuRegister shifter); 837 inline void X86_64Assembler::EmitRegisterOperand(uint8_t rm, uint8_t reg) { argument 838 CHECK_GE(rm, 0); 839 CHECK_LT(rm, 843 EmitXmmRegisterOperand(uint8_t rm, XmmRegister reg) argument [all...] |
/art/disassembler/ |
H A D | disassembler_x86.cc | 160 std::string DisassemblerX86::DumpAddress(uint8_t mod, uint8_t rm, uint8_t rex64, uint8_t rex_w, argument 166 if (mod == 0 && rm == 5) { 174 } else if (rm == 4 && mod != 3) { // SIB 227 DumpRmReg(address, rex_w, rm, byte_operand || byte_second_operand, 232 DumpBaseReg(address, rex64, rm); 296 const char* opcode3 = ""; // Mod-rm part. 298 bool store = false; // stores to memory (ie rm is on the left) 299 bool load = false; // loads from memory (ie rm is on the right) 1279 uint8_t rm = modrm & 7; local 1280 std::string address = DumpAddress(mod, rm, rex6 [all...] |
H A D | disassembler_arm.cc | 153 explicit RmLslImm2(uint32_t instr) : imm2((instr >> 4) & 0x3), rm(instr & 0xf) {} 155 ArmRegister rm; member in struct:art::arm::RmLslImm2 158 os << r.rm; 1408 unpred = unpred || (Rm.rm.r == SP) || (Rm.rm.r == PC); 1574 ThumbRegister rm(instr, 3); 1583 args << Rd << ", " << rm << ", #" << imm5; 1637 ThumbRegister rm(instr, 3); 1640 args << rdn << ", " << rm; local 1649 ArmRegister rm(inst 1653 args << DN_Rdn << ", " << rm; local 1664 args << DN_Rdn << ", " << rm; local 1674 args << N_Rn << ", " << rm; local 1682 args << rm; local [all...] |
/art/compiler/utils/arm/ |
H A D | assembler_arm.h | 45 explicit ShifterOperand(Register rm) : type_(kRegister), rm_(rm), rs_(kNoRegister), argument 54 ShifterOperand(Register rm, Shift shift, uint32_t shift_imm = 0) : type_(kRegister), rm_(rm), argument 60 ShifterOperand(Register rm, Shift shift, Register rs) : type_(kRegister), rm_(rm), argument 190 Address(Register rn, Register rm, Mode am = Offset) : rn_(rn), rm_(rm), offset_(0), argument 192 CHECK_NE(rm, PC); 195 Address(Register rn, Register rm, Shif argument [all...] |
H A D | assembler_arm32.cc | 183 void Arm32Assembler::mul(Register rd, Register rn, Register rm, Condition cond) { argument 184 // Assembler registers rd, rn, rm are encoded as rn, rm, rs. 185 EmitMulOp(cond, 0, R0, rd, rn, rm); 189 void Arm32Assembler::mla(Register rd, Register rn, Register rm, Register ra, argument 191 // Assembler registers rd, rn, rm, ra are encoded as rn, rm, rs, rd. 192 EmitMulOp(cond, B21, ra, rd, rn, rm); 196 void Arm32Assembler::mls(Register rd, Register rn, Register rm, Register ra, argument 198 // Assembler registers rd, rn, rm, r 203 umull(Register rd_lo, Register rd_hi, Register rn, Register rm, Condition cond) argument 210 sdiv(Register rd, Register rn, Register rm, Condition cond) argument 226 udiv(Register rd, Register rn, Register rm, Condition cond) argument 684 EmitShiftImmediate(Condition cond, Shift opcode, Register rd, Register rm, const ShifterOperand& so) argument 701 EmitShiftRegister(Condition cond, Shift opcode, Register rd, Register rm, const ShifterOperand& so) argument 731 clz(Register rd, Register rm, Condition cond) argument 763 EmitMulOp(Condition cond, int32_t opcode, Register rd, Register rn, Register rm, Register rs) argument 1153 Lsl(Register rd, Register rm, uint32_t shift_imm, bool setcc, Condition cond) argument 1164 Lsr(Register rd, Register rm, uint32_t shift_imm, bool setcc, Condition cond) argument 1176 Asr(Register rd, Register rm, uint32_t shift_imm, bool setcc, Condition cond) argument 1188 Ror(Register rd, Register rm, uint32_t shift_imm, bool setcc, Condition cond) argument 1198 Rrx(Register rd, Register rm, bool setcc, Condition cond) argument 1207 Lsl(Register rd, Register rm, Register rn, bool setcc, Condition cond) argument 1217 Lsr(Register rd, Register rm, Register rn, bool setcc, Condition cond) argument 1227 Asr(Register rd, Register rm, Register rn, bool setcc, Condition cond) argument 1237 Ror(Register rd, Register rm, Register rn, bool setcc, Condition cond) argument 1270 blx(Register rm, Condition cond) argument 1280 bx(Register rm, Condition cond) argument 1310 Mov(Register rd, Register rm, Condition cond) argument [all...] |
H A D | assembler_thumb2.cc | 180 void Thumb2Assembler::mul(Register rd, Register rn, Register rm, Condition cond) { argument 183 if (rd == rm && !IsHighRegister(rd) && !IsHighRegister(rn) && !force_32bit_) { 198 static_cast<uint32_t>(rm); 205 void Thumb2Assembler::mla(Register rd, Register rn, Register rm, Register ra, argument 217 static_cast<uint32_t>(rm); 223 void Thumb2Assembler::mls(Register rd, Register rn, Register rm, Register ra, argument 235 static_cast<uint32_t>(rm); 242 Register rm, Condition cond) { 253 static_cast<uint32_t>(rm); 259 void Thumb2Assembler::sdiv(Register rd, Register rn, Register rm, Conditio argument 241 umull(Register rd_lo, Register rd_hi, Register rn, Register rm, Condition cond) argument 276 udiv(Register rd, Register rn, Register rm, Condition cond) argument 1072 Register rm = so.GetRegister(); local 1202 EmitShift(Register rd, Register rm, Shift shift, uint8_t amount, bool setcc) argument 1241 EmitShift(Register rd, Register rn, Shift shift, Register rm, bool setcc) argument 1636 clz(Register rd, Register rm, Condition cond) argument 2198 blx(Register rm, Condition cond) argument 2206 bx(Register rm, Condition cond) argument 2234 Mov(Register rd, Register rm, Condition cond) argument 2320 Lsl(Register rd, Register rm, uint32_t shift_imm, bool setcc, Condition cond) argument 2328 Lsr(Register rd, Register rm, uint32_t shift_imm, bool setcc, Condition cond) argument 2337 Asr(Register rd, Register rm, uint32_t shift_imm, bool setcc, Condition cond) argument 2346 Ror(Register rd, Register rm, uint32_t shift_imm, bool setcc, Condition cond) argument 2354 Rrx(Register rd, Register rm, bool setcc, Condition cond) argument 2360 Lsl(Register rd, Register rm, Register rn, bool setcc, Condition cond) argument 2367 Lsr(Register rd, Register rm, Register rn, bool setcc, Condition cond) argument 2374 Asr(Register rd, Register rm, Register rn, bool setcc, Condition cond) argument 2381 Ror(Register rd, Register rm, Register rn, bool setcc, Condition cond) argument [all...] |