Searched refs:registers (Results 1 - 23 of 23) sorted by relevance

/art/test/425-invoke-super/smali/
H A Dsubclass.smali20 .registers 1
26 .registers 2
H A Dsuperclass.smali20 .registers 1
26 .registers 2
H A Dinvokesuper.smali21 .registers 1
28 .registers 2
37 .registers 2
/art/test/471-uninitialized-locals/smali/
H A DTest.smali21 .registers 1
/art/test/435-new-instance/smali/
H A Dinstance.smali20 .registers 1
26 .registers 5
34 .registers 5
42 .registers 5
50 .registers 5
/art/test/434-invoke-direct/smali/
H A Dinvoke.smali20 .registers 2
26 .registers 3
/art/test/501-regression-packed-switch/smali/
H A DTest.smali21 .registers 1
/art/test/504-regression-baseline-entry/smali/
H A DTest.smali21 .registers 1
/art/test/472-unreachable-if-regression/smali/
H A DTest.smali21 .registers 1
30 .registers 1
/art/runtime/
H A Dcheck_reference_map_visitor.h27 // Helper class for tests checking that the compiler keeps track of dex registers
54 void CheckReferences(int* registers, int number_of_references, uint32_t native_pc_offset)
57 CheckOptimizedMethod(registers, number_of_references, native_pc_offset);
59 CheckQuickMethod(registers, number_of_references, native_pc_offset);
64 void CheckOptimizedMethod(int* registers, int number_of_references, uint32_t native_pc_offset)
75 int reg = registers[i];
105 void CheckQuickMethod(int* registers, int number_of_references, uint32_t native_pc_offset)
112 int reg = registers[i];
/art/test/134-reg-promotion/smali/
H A DTest.smali21 .registers 3
41 .registers 4
/art/runtime/arch/mips/
H A Djni_entrypoints_mips.S41 lw $a0, 0($sp) # restore registers from stack
H A Dquick_entrypoints_mips.S375 move $v0, $zero # clear result registers r0 and r1
381 * Called by managed code, saves most registers (forms basis of long jump context) and passes
1152 # Load parameters from stack into registers
/art/compiler/utils/arm64/
H A Dassembler_arm64.cc552 // For now we only hold stale handle scope entries in x registers.
652 void Arm64Assembler::SpillRegisters(vixl::CPURegList registers, int offset) { argument
653 int size = registers.RegisterSizeInBytes();
655 while (registers.Count() >= 2) {
656 const CPURegister& dst0 = registers.PopLowestIndex();
657 const CPURegister& dst1 = registers.PopLowestIndex();
663 if (!registers.IsEmpty()) {
664 const CPURegister& dst0 = registers.PopLowestIndex();
668 DCHECK(registers.IsEmpty());
671 void Arm64Assembler::UnspillRegisters(vixl::CPURegList registers, in argument
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H A Dassembler_arm64.h85 void SpillRegisters(vixl::CPURegList registers, int offset);
86 void UnspillRegisters(vixl::CPURegList registers, int offset);
/art/runtime/arch/mips64/
H A Djni_entrypoints_mips64.S52 ld $a0, 0($sp) # restore registers from stack
H A Dquick_entrypoints_mips64.S436 move $v0, $zero # clear result registers v0 and v1
442 * Called by managed code, saves most registers (forms basis of long jump
1417 # Load parameters from stack into registers
/art/compiler/optimizing/
H A Dcode_generator.h116 // The current index for core registers.
118 // The current index for floating-point registers.
185 static uint32_t ComputeRegisterMask(const int* registers, size_t length) { argument
188 mask |= (1 << registers[i]);
379 // Returns the location of the first spilled entry for floating point registers,
394 // We check the core registers against 1 because it always comprises the return PC.
422 // registers we can allocate. `SetupBlockedRegisters` updates the
471 CallingConvention(const C* registers, argument
476 : registers_(registers),
496 // We still reserve the space for parameters passed by registers
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/art/compiler/utils/x86_64/
H A Dassembler_x86_64_test.cc364 std::vector<x86_64::CpuRegister*> registers = assembler_test->GetRegisters(); local
367 for (auto reg : registers) {
387 std::vector<x86_64::CpuRegister*> registers = assembler_test->GetRegisters(); local
390 for (auto reg : registers) {
410 std::vector<x86_64::CpuRegister*> registers = assembler_test->GetRegisters(); local
413 for (auto reg : registers) {
433 std::vector<x86_64::CpuRegister*> registers = assembler_test->GetRegisters(); local
436 for (auto reg : registers) {
456 std::vector<x86_64::CpuRegister*> registers = assembler_test->GetRegisters(); local
459 for (auto reg : registers) {
479 std::vector<x86_64::CpuRegister*> registers = assembler_test->GetRegisters(); local
1073 std::vector<x86_64::CpuRegister*> registers = assembler_test->GetRegisters(); local
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/art/compiler/utils/
H A Dassembler_test.h216 UNIMPLEMENTED(FATAL) << "Architecture does not support floating-point registers";
220 // Secondary register names are the secondary view on registers, e.g., 32b on 64b systems.
222 UNIMPLEMENTED(FATAL) << "Architecture does not support secondary registers";
226 // Tertiary register names are the tertiary view on registers, e.g., 16b on 64b systems.
228 UNIMPLEMENTED(FATAL) << "Architecture does not support tertiary registers";
232 // Quaternary register names are the quaternary view on registers, e.g., 8b on 64b systems.
234 UNIMPLEMENTED(FATAL) << "Architecture does not support quaternary registers";
347 const std::vector<RegType*> registers,
351 for (auto reg : registers) {
509 const std::vector<Reg*> registers local
346 RepeatTemplatedRegister(void (Ass::*f)(RegType), const std::vector<RegType*> registers, std::string (AssemblerTest::*GetName)(const RegType&), std::string fmt) argument
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/art/compiler/utils/arm/
H A Dassembler_arm32_test.cc299 std::vector<arm::Register*> registers = without_pc ? GetRegistersWithoutPC() : GetRegisters(); local
300 for (auto reg : registers) {
347 std::vector<arm::Register*> registers = without_pc ? GetRegistersWithoutPC() : GetRegisters(); local
348 for (auto reg : registers) {
H A Dassembler_arm_test.h390 const std::vector<RegT*>& registers,
395 WarnOnCombinations(cond.size() * registers.size() * shifts.size());
416 for (auto reg : registers) {
389 RepeatTemplatedRSC(void (Ass::*f)(RegT, SOp, Cond), const std::vector<RegT*>& registers, const std::vector<SOp>& shifts, const std::vector<Cond>& cond, std::string (AssemblerArmTest::*GetName)(const RegT&), std::string fmt) argument
/art/runtime/arch/arm/
H A Dquick_entrypoints_arm.S195 SETUP_SAVE_ALL_CALLEE_SAVE_FRAME r0, r1 // save all registers as basis for long jump context
204 SETUP_SAVE_ALL_CALLEE_SAVE_FRAME r1, r2 // save all registers as basis for long jump context
213 SETUP_SAVE_ALL_CALLEE_SAVE_FRAME r2, r3 // save all registers as basis for long jump context
451 mov r0, #0 @ clear result registers r0 and r1
592 SETUP_SAVE_ALL_CALLEE_SAVE_FRAME r2, r3 // save all registers as basis for long jump context
881 // Tear down the callee-save frame. Skip arg registers.
957 // Load parameters from frame into registers.
990 // Tear down the callee-save frame. Skip arg registers.
1016 // Tear down the callee-save frame. Skip arg registers.

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