/external/valgrind/none/tests/ppc32/ |
H A D | opcodes.h | 28 #define X20_ASM(OPCODE, TH, RA, RB, XO, RES) \ 32 "(" #RA "<<" X20_RA_OFFSET ")" "+" \ 37 #define X20(OPCODE, TH, RA, RB, XO, RES) X20_ASM(OPCODE, TH, RA, RB, XO, RES) 46 #define DCBT_S(RA, RB, TH) X20(DCBT_OPCODE, TH, RA, RB, DCBT_XO, DCBT_RES) 47 #define ASM_DCBT(RA, RB, TH) __asm__ __volatile__ (DCBT_S(RA, RB, TH)) 53 #define DCBTST_S(RA, RB, TH) X20(DCBTST_OPCODE, TH, RA, R [all...] |
H A D | data-cache-instructions.c | 50 asm volatile ("dcbzl %[RA], %[RB]" : : [RA] "r" (0), [RB] "r" (addr));
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/external/valgrind/none/tests/ppc64/ |
H A D | opcodes.h | 28 #define X20_ASM(OPCODE, TH, RA, RB, XO, RES) \ 32 "(" #RA "<<" X20_RA_OFFSET ")" "+" \ 37 #define X20(OPCODE, TH, RA, RB, XO, RES) X20_ASM(OPCODE, TH, RA, RB, XO, RES) 46 #define DCBT_S(RA, RB, TH) X20(DCBT_OPCODE, TH, RA, RB, DCBT_XO, DCBT_RES) 47 #define ASM_DCBT(RA, RB, TH) __asm__ __volatile__ (DCBT_S(RA, RB, TH)) 53 #define DCBTST_S(RA, RB, TH) X20(DCBTST_OPCODE, TH, RA, R [all...] |
H A D | data-cache-instructions.c | 50 asm volatile ("dcbzl %[RA], %[RB]" : : [RA] "r" (0), [RB] "r" (addr));
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/external/clang/test/Layout/ |
H A D | ms-x86-alias-avoidance-padding.cpp | 301 struct RA {}; struct 306 struct RX0 : RB, RA {}; 307 struct RX1 : RA, RB {}; 308 struct RX2 : RA { char a; }; 309 struct RX3 : RA { RB a; }; 310 struct RX4 { RA a; char b; }; 311 struct RX5 { RA a; RB b; }; 313 struct RX7 : virtual RW { RA a; }; 314 struct RX8 : RA, virtual RW {}; 326 // CHECK-NEXT: 1 | struct RA (bas [all...] |
H A D | ms-x86-pack-and-align.cpp | 430 struct RA {}; struct 441 struct __declspec(align(8)) RB2 : virtual RA { 445 struct __declspec(align(8)) RB3 : virtual RA { 476 // CHECK-NEXT: 1028 | struct RA (virtual base) (empty) 484 // CHECK-NEXT: 2052 | struct RA (virtual base) (empty) 519 // CHECK-X64-NEXT: 1028 | struct RA (virtual base) (empty) 527 // CHECK-X64-NEXT: 2052 | struct RA (virtual base) (empty)
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/external/clang/test/CodeGenCXX/ |
H A D | devirtualize-virtual-function-calls-final.cpp | 179 struct RA { struct in namespace:Test9 187 struct RC final : public RA { 212 return static_cast<RA*>(x)->f(); 225 return -static_cast<RA&>(*x);
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/external/llvm/lib/MC/ |
H A D | MCSubtargetInfo.cpp | 44 const MCReadAdvanceEntry *RA, 55 ReadAdvanceTable = RA; 38 InitMCSubtargetInfo(StringRef TT, StringRef C, StringRef FS, ArrayRef<SubtargetFeatureKV> PF, ArrayRef<SubtargetFeatureKV> PD, const SubtargetInfoKV *ProcSched, const MCWriteProcResEntry *WPR, const MCWriteLatencyEntry *WL, const MCReadAdvanceEntry *RA, const InstrStage *IS, const unsigned *OC, const unsigned *FP) argument
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/external/llvm/lib/Transforms/IPO/ |
H A D | DeadArgumentElimination.cpp | 153 void MarkValue(const RetOrArg &RA, Liveness L, 155 void MarkLive(const RetOrArg &RA); 157 void PropagateLiveness(const RetOrArg &RA); 663 /// MarkValue - This function marks the liveness of RA depending on L. If L is 665 /// such that RA will be marked live if any use in MaybeLiveUses gets marked 667 void DAE::MarkValue(const RetOrArg &RA, Liveness L, argument 670 case Live: MarkLive(RA); break; 677 Uses.insert(std::make_pair(*UI, RA)); 702 void DAE::MarkLive(const RetOrArg &RA) { argument 703 if (LiveFunctions.count(RA 715 PropagateLiveness(const RetOrArg &RA) argument [all...] |
H A D | MergeFunctions.cpp | 445 Attribute RA = *RI; local 446 if (LA < RA) 448 if (RA < LA) 548 const ConstantArray *RA = cast<ConstantArray>(R); local 555 cast<Constant>(RA->getOperand(i))))
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/external/llvm/utils/TableGen/ |
H A D | FixedLenDecoderEmitter.cpp | 461 void reportRegion(bitAttr_t RA, unsigned StartBit, unsigned BitIndex, 1360 void FilterChooser::reportRegion(bitAttr_t RA, unsigned StartBit, 1362 if (RA == ATTR_MIXED && AllowMixed) 1364 else if (RA == ATTR_ALL_SET && !AllowMixed) 1482 bitAttr_t RA = ATTR_NONE; 1490 switch (RA) { 1497 RA = ATTR_ALL_SET; 1503 RA = ATTR_MIXED; 1512 reportRegion(RA, StartBit, BitIndex, AllowMixed); 1513 RA [all...] |
/external/libpcap/ |
H A D | tokdefs.h | 90 RA = 308, enumerator in enum:yytokentype 211 #define RA 308 macro
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H A D | grammar.y | 280 %token TYPE SUBTYPE DIR ADDR1 ADDR2 ADDR3 ADDR4 RA TA 446 | RA { $$ = Q_RA; }
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/external/llvm/lib/Target/X86/MCTargetDesc/ |
H A D | X86MCTargetDesc.cpp | 105 unsigned RA = (TheTriple.getArch() == Triple::x86_64) local 110 InitX86MCRegisterInfo(X, RA, 113 RA);
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/external/llvm/include/llvm/MC/ |
H A D | MCSubtargetInfo.h | 54 const MCReadAdvanceEntry *RA,
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H A D | MCRegisterInfo.h | 244 void InitMCRegisterInfo(const MCRegisterDesc *D, unsigned NR, unsigned RA, argument 259 RAReg = RA;
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/external/llvm/lib/Target/Mips/ |
H A D | MipsRegisterInfo.cpp | 46 MipsRegisterInfo::MipsRegisterInfo() : MipsGenRegisterInfo(Mips::RA) {} 204 // Reserve RA if in mips16 mode. 207 Reserved.set(Mips::RA);
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H A D | Mips16FrameLowering.cpp | 112 // Registers RA, S0,S1 are the callee saved registers and they 118 // RA and return address is taken, because it has already been added in 120 // It's killed at the spill, unless the register is RA and return address 123 bool IsRAAndRetAddrIsTaken = (Reg == Mips::RA) 137 // Registers RA,S0,S1 are the callee saved registers and they will be restored
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H A D | MipsLongBranch.cpp | 298 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::SW)).addReg(Mips::RA) 329 .addReg(Mips::RA).addReg(Mips::AT); 330 BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::LW), Mips::RA)
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H A D | MipsSEInstrInfo.cpp | 438 BuildMI(MBB, I, I->getDebugLoc(), get(Mips::PseudoReturn)).addReg(Mips::RA); 615 unsigned RA = Subtarget.isGP64bit() ? Mips::RA_64 : Mips::RA; local 629 BuildMI(MBB, I, I->getDebugLoc(), get(ADDU), RA)
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/external/llvm/lib/Target/PowerPC/MCTargetDesc/ |
H A D | PPCMCTargetDesc.cpp | 59 unsigned RA = isPPC64 ? PPC::LR8 : PPC::LR; local 62 InitPPCMCRegisterInfo(X, RA, Flavour, Flavour);
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/external/llvm/lib/Target/Mips/MCTargetDesc/ |
H A D | MipsMCTargetDesc.cpp | 66 InitMipsMCRegisterInfo(X, Mips::RA);
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/external/llvm/lib/Analysis/ |
H A D | ScalarEvolution.cpp | 511 const Argument *RA = cast<Argument>(RV); local 512 unsigned LArgNo = LA->getArgNo(), RArgNo = RA->getArgNo(); 546 const APInt &RA = RC->getValue()->getValue(); local 547 unsigned LBitWidth = LA.getBitWidth(), RBitWidth = RA.getBitWidth(); 550 return LA.ult(RA) ? -1 : 1; 555 const SCEVAddRecExpr *RA = cast<SCEVAddRecExpr>(RHS); local 558 const Loop *LLoop = LA->getLoop(), *RLoop = RA->getLoop(); 567 unsigned LNumOps = LA->getNumOperands(), RNumOps = RA->getNumOperands(); 573 long X = compare(LA->getOperand(i), RA->getOperand(i)); 4356 const SCEV *RA [all...] |
/external/llvm/lib/Target/Mips/InstPrinter/ |
H A D | MipsInstPrinter.cpp | 319 return isReg<Mips::RA>(MI, 0) && printAlias("jalr", MI, 1, OS);
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/external/llvm/lib/Transforms/InstCombine/ |
H A D | InstCombineSimplifyDemanded.cpp | 764 APInt RA = Rem->getValue().abs(); local 765 if (RA.isPowerOf2()) { 766 if (DemandedMask.ult(RA)) // srem won't affect demanded bits 769 APInt LowBits = RA - 1;
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