| /external/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 358 /// SHL_PARTS/SRA_PARTS/SRL_PARTS - These operators are used for expanded
362 SHL_PARTS, SRA_PARTS, SRL_PARTS, enumerator in enum:llvm::ISD::NodeType
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGDumper.cpp | 221 case ISD::SRA_PARTS: return "sra_parts";
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| H A D | LegalizeIntegerTypes.cpp | 2131 PartsOpc = ISD::SRA_PARTS;
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| H A D | LegalizeDAG.cpp | 1322 case ISD::SRA_PARTS:
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| H A D | SelectionDAG.cpp | 5182 case ISD::SRA_PARTS:
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| /external/llvm/lib/Target/MSP430/ |
| H A D | MSP430ISelLowering.cpp | 137 setOperationAction(ISD::SRA_PARTS, MVT::i8, Expand);
138 setOperationAction(ISD::SRA_PARTS, MVT::i16, Expand);
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| /external/llvm/lib/Target/BPF/ |
| H A D | BPFISelLowering.cpp | 138 setOperationAction(ISD::SRA_PARTS, MVT::i64, Expand);
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| /external/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXISelLowering.cpp | 164 setOperationAction(ISD::SRA_PARTS, MVT::i32 , Custom);
167 setOperationAction(ISD::SRA_PARTS, MVT::i64 , Custom);
1651 /// LowerShiftRightParts - Lower SRL_PARTS, SRA_PARTS, which
1659 assert(Op.getOpcode() == ISD::SRA_PARTS || Op.getOpcode() == ISD::SRL_PARTS);
1667 unsigned Opc = (Op.getOpcode() == ISD::SRA_PARTS) ? ISD::SRA : ISD::SRL;
1794 case ISD::SRA_PARTS:
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| /external/llvm/lib/Target/R600/ |
| H A D | R600ISelLowering.cpp | 179 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
586 case ISD::SRA_PARTS:
1051 const bool SRA = Op.getOpcode() == ISD::SRA_PARTS;
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| /external/llvm/lib/Target/Mips/ |
| H A D | MipsISelLowering.cpp | 279 setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom);
285 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
854 case ISD::SRA_PARTS: return lowerShiftRightParts(Op, DAG, true);
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| /external/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLowering.cpp | 1745 setOperationAction(ISD::SRA_PARTS, MVT::i64, Expand);
1755 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
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| /external/llvm/lib/Target/XCore/ |
| H A D | XCoreISelLowering.cpp | 108 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
|
| /external/llvm/lib/Target/Sparc/ |
| H A D | SparcISelLowering.cpp | 1544 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
1561 setOperationAction(ISD::SRA_PARTS, MVT::i64, Expand);
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| /external/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 148 setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom);
1995 case ISD::SRA_PARTS:
4106 /// LowerShiftRightParts - Lower SRA_PARTS, which returns two
4118 unsigned Opc = (Op.getOpcode() == ISD::SRA_PARTS) ? ISD::SRA : ISD::SRL;
4120 assert(Op.getOpcode() == ISD::SRA_PARTS || Op.getOpcode() == ISD::SRL_PARTS);
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| /external/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 677 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
4065 /// LowerShiftRightParts - Lower SRA_PARTS, which returns two
4077 unsigned Opc = (Op.getOpcode() == ISD::SRA_PARTS) ? ISD::SRA : ISD::SRL;
4079 assert(Op.getOpcode() == ISD::SRA_PARTS || Op.getOpcode() == ISD::SRL_PARTS);
6302 case ISD::SRA_PARTS: return LowerShiftRightParts(Op, DAG);
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| /external/llvm/lib/Target/SystemZ/ |
| H A D | SystemZISelLowering.cpp | 224 setOperationAction(ISD::SRA_PARTS, MVT::i64, Expand);
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| /external/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 391 setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom);
396 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
7697 case ISD::SRA_PARTS: return LowerSRA_PARTS(Op, DAG);
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| /external/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 451 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom);
455 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom);
11338 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values
11345 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS;
17204 case ISD::SRA_PARTS:
|