| /external/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 214 ADDE, SUBE, enumerator in enum:llvm::ISD::NodeType
|
| /external/llvm/lib/Target/Mips/ |
| H A D | Mips16ISelDAGToDAG.cpp | 258 case ISD::SUBE:
263 (Opc == ISD::SUBC || Opc == ISD::SUBE)) &&
|
| H A D | MipsSEISelDAGToDAG.cpp | 236 (Opc == ISD::SUBC || Opc == ISD::SUBE)) &&
708 case ISD::SUBE: {
|
| H A D | MipsSEISelLowering.cpp | 143 setTargetDAGCombine(ISD::SUBE);
1079 case ISD::SUBE:
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGDumper.cpp | 219 case ISD::SUBE: return "sube";
|
| H A D | LegalizeIntegerTypes.cpp | 1313 case ISD::SUBE: ExpandIntRes_ADDSUBE(N, Lo, Hi); break;
1618 // Do not generate ADDC/ADDE or SUBC/SUBE if the target does not support
1620 // ADDC/ADDE/SUBC/SUBE. The problem is that these operations generate
1637 Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps);
1686 Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps);
|
| H A D | DAGCombiner.cpp | 1310 case ISD::SUBE: return visitSUBE(N);
|
| /external/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.h | 75 SUBE, // Sub using carry enumerator in enum:llvm::ARMISD::NodeType
|
| H A D | ARMISelLowering.cpp | 687 setOperationAction(ISD::SUBE, MVT::i32, Custom);
1042 case ARMISD::SUBE: return "ARMISD::SUBE";
6140 case ISD::SUBE: Opc = ARMISD::SUBE; ExtraOp = true; break;
6319 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
10401 case ARMISD::SUBE:
|
| /external/llvm/lib/Target/BPF/ |
| H A D | BPFISelLowering.cpp | 129 setOperationAction(ISD::SUBE, MVT::i64, Expand);
|
| /external/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLowering.cpp | 1707 setOperationAction(ISD::SUBE, MVT::i8, Expand);
1708 setOperationAction(ISD::SUBE, MVT::i16, Expand);
1709 setOperationAction(ISD::SUBE, MVT::i32, Expand);
1710 setOperationAction(ISD::SUBE, MVT::i64, Expand);
|
| /external/mesa3d/src/gallium/drivers/radeon/ |
| H A D | AMDILISelLowering.cpp | 111 setOperationAction(ISD::SUBE, VT, Expand);
|
| /external/llvm/lib/Target/Sparc/ |
| H A D | SparcISelLowering.cpp | 1464 setOperationAction(ISD::SUBE, MVT::i64, Custom);
2697 case ISD::SUBC: hiOpc = ISD::SUBE; break;
2698 case ISD::SUBE: hasChain = true; break;
2832 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
|
| /external/llvm/lib/Target/R600/ |
| H A D | SIISelLowering.cpp | 74 setOperationAction(ISD::SUBE, MVT::i32, Legal);
|
| H A D | AMDGPUISelLowering.cpp | 341 setOperationAction(ISD::SUBE, VT, Expand);
|
| H A D | R600ISelLowering.cpp | 188 setOperationAction(ISD::SUBE, VT, Expand);
|
| /external/llvm/lib/Target/XCore/ |
| H A D | XCoreISelLowering.cpp | 98 setOperationAction(ISD::SUBE, MVT::i32, Expand);
|
| /external/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 227 setOperationAction(ISD::SUBE, MVT::i32, Custom);
231 setOperationAction(ISD::SUBE, MVT::i64, Custom);
1467 case ISD::SUBE:
1953 case ISD::SUBE:
|
| /external/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 296 setOperationAction(ISD::SUBE, VT, Custom);
17116 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break;
17261 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG);
17298 case ISD::SUBE:
|