/external/clang/test/CodeGen/ |
H A D | ppc64-vector.c | 5 typedef short v4i16 __attribute__((vector_size (8))); typedef 25 v4i16 test_v4i16(v4i16 x)
|
H A D | systemz-abi-vector.c | 16 typedef __attribute__((vector_size(8))) short v4i16; typedef 57 v4i16 pass_v4i16(v4i16 arg) { return arg; }
|
/external/llvm/lib/Target/ARM/ |
H A D | ARMTargetTransformInfo.cpp | 81 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i16, 0 }, 82 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i16, 0 }, 86 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i32, 1 }, 89 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 3 }, 90 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 3 }, 118 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i16, 2 }, 119 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i16, 2 }, 133 { ISD::FP_TO_SINT, MVT::v4i16, MVT::v4f32, 2 }, 134 { ISD::FP_TO_UINT, MVT::v4i16, MVT::v4f32, 2 }, 376 {ISD::VECTOR_SHUFFLE, MVT::v4i16, [all...] |
H A D | ARMISelLowering.cpp | 432 addDRTypeForNEON(MVT::v4i16); 522 setOperationAction(ISD::SDIV, MVT::v4i16, Custom); 524 setOperationAction(ISD::UDIV, MVT::v4i16, Custom); 532 setOperationAction(ISD::SINT_TO_FP, MVT::v4i16, Custom); 533 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom); 534 setOperationAction(ISD::FP_TO_UINT, MVT::v4i16, Custom); 535 setOperationAction(ISD::FP_TO_SINT, MVT::v4i16, Custom); 545 setOperationAction(ISD::CTPOP, MVT::v4i16, Custom); 573 // It is legal to extload from v4i8 to v4i16 or v4i32. 574 for (MVT Ty : {MVT::v8i8, MVT::v4i8, MVT::v2i8, MVT::v4i16, MV [all...] |
H A D | ARMISelDAGToDAG.cpp | 1794 case MVT::v4i16: OpcodeIndex = 1; break; 1931 case MVT::v4i16: OpcodeIndex = 1; break; 2094 case MVT::v4i16: OpcodeIndex = 1; break; 2206 case MVT::v4i16: OpcodeIndex = 1; break; 2745 case MVT::v4i16: Opc = ARM::VZIPd16; break; 2765 case MVT::v4i16: Opc = ARM::VUZPd16; break; 2785 case MVT::v4i16: Opc = ARM::VTRNd16; break;
|
/external/llvm/include/llvm/CodeGen/ |
H A D | MachineValueType.h | 75 v4i16 = 28, // 4 x i16 enumerator in enum:llvm::MVT::SimpleValueType 217 return (SimpleTy == MVT::v8i8 || SimpleTy == MVT::v4i16 || 299 case v4i16: 353 case v4i16: 416 case v4i16: 546 if (NumElements == 4) return MVT::v4i16;
|
/external/llvm/lib/Target/AArch64/ |
H A D | AArch64ISelDAGToDAG.cpp | 463 case MVT::v4i16: 2262 else if (VT == MVT::v4i16 || VT == MVT::v4f16) 2280 else if (VT == MVT::v4i16 || VT == MVT::v4f16) 2298 else if (VT == MVT::v4i16 || VT == MVT::v4f16) 2316 else if (VT == MVT::v4i16 || VT == MVT::v4f16) 2334 else if (VT == MVT::v4i16 || VT == MVT::v4f16) 2352 else if (VT == MVT::v4i16 || VT == MVT::v4f16) 2370 else if (VT == MVT::v4i16 || VT == MVT::v4f16) 2388 else if (VT == MVT::v4i16 || VT == MVT::v4f16) 2406 else if (VT == MVT::v4i16 || V [all...] |
H A D | AArch64TargetTransformInfo.cpp | 209 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i16, 2 }, 211 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i16, 2 }, 238 // Complex, from v4f32: legal type is v4i16, 1 narrowing => ~2 239 { ISD::FP_TO_SINT, MVT::v4i16, MVT::v4f32, 2 }, 241 { ISD::FP_TO_UINT, MVT::v4i16, MVT::v4f32, 2 },
|
H A D | AArch64ISelLowering.cpp | 106 addDRTypeForNEON(MVT::v4i16); 558 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Promote); 559 setOperationAction(ISD::SINT_TO_FP, MVT::v4i16, Promote); 757 } else if (VT == MVT::v4i16 || VT == MVT::v8i16) { 1739 return MVT::v4i16; 5417 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16; 5426 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16; 5617 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16; 5626 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16; 5750 MVT MovTy = (VT.getSizeInBits() == 128) ? MVT::v8i16 : MVT::v4i16; [all...] |
/external/llvm/lib/Target/X86/ |
H A D | X86TargetTransformInfo.cpp | 555 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 3 }, 556 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 3 }, 561 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i64, 2 }, 587 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 6 }, 588 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 3 }, 593 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i64, 4 }, 606 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i16, 3 }, 610 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i16, 3 }, 619 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i16, 2 }, 623 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i16, [all...] |
H A D | X86ISelLowering.cpp | 766 for (MVT MMXTy : {MVT::v8i8, MVT::v4i16, MVT::v2i32, MVT::v1i64}) { 869 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v4i16, Custom); 875 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i16, Custom); 923 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom); 936 setOperationAction(ISD::BITCAST, MVT::v4i16, Custom); 968 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i32, MVT::v4i16, Legal); 975 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i32, MVT::v4i16, Legal); 1156 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i64, MVT::v4i16, Legal); 1163 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i64, MVT::v4i16, Legal); 11722 case MVT::v4i16 [all...] |
/external/llvm/lib/IR/ |
H A D | ValueTypes.cpp | 146 case MVT::v4i16: return "v4i16"; 214 case MVT::v4i16: return VectorType::get(Type::getInt16Ty(Context), 4);
|
/external/mesa3d/src/gallium/drivers/radeon/ |
H A D | AMDILISelLowering.cpp | 60 (int)MVT::v4i16, 88 (int)MVT::v4i16, 210 setOperationAction(ISD::UDIV, MVT::v4i16, Expand); 668 } else if (OVT == MVT::v4i16) {
|
/external/llvm/lib/Target/Hexagon/ |
H A D | HexagonISelLowering.cpp | 170 } else if (LocVT == MVT::v8i8 || LocVT == MVT::v4i16 || LocVT == MVT::v2i32) { 251 } else if (LocVT == MVT::v8i8 || LocVT == MVT::v4i16 || LocVT == MVT::v2i32) { 965 if (VT.getSimpleVT() == MVT::v4i16) 1077 if (VT == MVT::v4i16) { 1276 addRegisterClass(MVT::v4i16, &Hexagon::DoubleRegsRegClass); 1280 // Custom lower v4i16 load only. Let v4i16 store to be 1282 setOperationAction(ISD::LOAD, MVT::v4i16, Custom); 1283 AddPromotedToType(ISD::LOAD, MVT::v4i16, MVT::i64); 1284 setOperationAction(ISD::STORE, MVT::v4i16, Promot [all...] |
/external/llvm/utils/TableGen/ |
H A D | CodeGenTarget.cpp | 88 case MVT::v4i16: return "MVT::v4i16";
|
/external/llvm/lib/Target/R600/ |
H A D | AMDGPUISelLowering.cpp | 178 setTruncStoreAction(MVT::v4i32, MVT::v4i16, Expand); 237 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i16, Expand); 238 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v4i16, Expand); 239 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::v4i16, Expand);
|
H A D | SIISelLowering.cpp | 117 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i16, Custom);
|
H A D | R600ISelLowering.cpp | 109 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i16, Expand);
|
/external/llvm/lib/Target/NVPTX/ |
H A D | NVPTXISelLowering.cpp | 66 case MVT::v4i16: 1883 case MVT::v4i16: 4241 case MVT::v4i16:
|