1/*
2 *
3 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
16 * of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 *
26 */
27
28#ifndef _INTEL_CHIPSET_H
29#define _INTEL_CHIPSET_H
30
31#define PCI_CHIP_I810			0x7121
32#define PCI_CHIP_I810_DC100		0x7123
33#define PCI_CHIP_I810_E			0x7125
34#define PCI_CHIP_I815			0x1132
35
36#define PCI_CHIP_I830_M			0x3577
37#define PCI_CHIP_845_G			0x2562
38#define PCI_CHIP_I855_GM		0x3582
39#define PCI_CHIP_I865_G			0x2572
40
41#define PCI_CHIP_I915_G			0x2582
42#define PCI_CHIP_E7221_G		0x258A
43#define PCI_CHIP_I915_GM		0x2592
44#define PCI_CHIP_I945_G			0x2772
45#define PCI_CHIP_I945_GM		0x27A2
46#define PCI_CHIP_I945_GME		0x27AE
47
48#define PCI_CHIP_Q35_G			0x29B2
49#define PCI_CHIP_G33_G			0x29C2
50#define PCI_CHIP_Q33_G			0x29D2
51
52#define PCI_CHIP_IGD_GM			0xA011
53#define PCI_CHIP_IGD_G			0xA001
54
55#define IS_IGDGM(devid)		((devid) == PCI_CHIP_IGD_GM)
56#define IS_IGDG(devid)		((devid) == PCI_CHIP_IGD_G)
57#define IS_IGD(devid)		(IS_IGDG(devid) || IS_IGDGM(devid))
58
59#define PCI_CHIP_I965_G			0x29A2
60#define PCI_CHIP_I965_Q			0x2992
61#define PCI_CHIP_I965_G_1		0x2982
62#define PCI_CHIP_I946_GZ		0x2972
63#define PCI_CHIP_I965_GM		0x2A02
64#define PCI_CHIP_I965_GME		0x2A12
65
66#define PCI_CHIP_GM45_GM		0x2A42
67
68#define PCI_CHIP_IGD_E_G		0x2E02
69#define PCI_CHIP_Q45_G			0x2E12
70#define PCI_CHIP_G45_G			0x2E22
71#define PCI_CHIP_G41_G			0x2E32
72
73#define PCI_CHIP_ILD_G			0x0042
74#define PCI_CHIP_ILM_G			0x0046
75
76#define PCI_CHIP_SANDYBRIDGE_GT1	0x0102 /* desktop */
77#define PCI_CHIP_SANDYBRIDGE_GT2	0x0112
78#define PCI_CHIP_SANDYBRIDGE_GT2_PLUS	0x0122
79#define PCI_CHIP_SANDYBRIDGE_M_GT1	0x0106 /* mobile */
80#define PCI_CHIP_SANDYBRIDGE_M_GT2	0x0116
81#define PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS	0x0126
82#define PCI_CHIP_SANDYBRIDGE_S		0x010A /* server */
83
84#define PCI_CHIP_IVYBRIDGE_GT1		0x0152 /* desktop */
85#define PCI_CHIP_IVYBRIDGE_GT2		0x0162
86#define PCI_CHIP_IVYBRIDGE_M_GT1	0x0156 /* mobile */
87#define PCI_CHIP_IVYBRIDGE_M_GT2	0x0166
88#define PCI_CHIP_IVYBRIDGE_S		0x015a /* server */
89#define PCI_CHIP_IVYBRIDGE_S_GT2	0x016a /* server */
90
91#define PCI_CHIP_HASWELL_GT1		0x0402 /* Desktop */
92#define PCI_CHIP_HASWELL_GT2		0x0412
93#define PCI_CHIP_HASWELL_GT3		0x0422
94#define PCI_CHIP_HASWELL_M_GT1		0x0406 /* Mobile */
95#define PCI_CHIP_HASWELL_M_GT2		0x0416
96#define PCI_CHIP_HASWELL_M_GT3		0x0426
97#define PCI_CHIP_HASWELL_S_GT1		0x040A /* Server */
98#define PCI_CHIP_HASWELL_S_GT2		0x041A
99#define PCI_CHIP_HASWELL_S_GT3		0x042A
100#define PCI_CHIP_HASWELL_B_GT1		0x040B /* Reserved */
101#define PCI_CHIP_HASWELL_B_GT2		0x041B
102#define PCI_CHIP_HASWELL_B_GT3		0x042B
103#define PCI_CHIP_HASWELL_E_GT1		0x040E /* Reserved */
104#define PCI_CHIP_HASWELL_E_GT2		0x041E
105#define PCI_CHIP_HASWELL_E_GT3		0x042E
106#define PCI_CHIP_HASWELL_SDV_GT1	0x0C02 /* Desktop */
107#define PCI_CHIP_HASWELL_SDV_GT2	0x0C12
108#define PCI_CHIP_HASWELL_SDV_GT3	0x0C22
109#define PCI_CHIP_HASWELL_SDV_M_GT1	0x0C06 /* Mobile */
110#define PCI_CHIP_HASWELL_SDV_M_GT2	0x0C16
111#define PCI_CHIP_HASWELL_SDV_M_GT3	0x0C26
112#define PCI_CHIP_HASWELL_SDV_S_GT1	0x0C0A /* Server */
113#define PCI_CHIP_HASWELL_SDV_S_GT2	0x0C1A
114#define PCI_CHIP_HASWELL_SDV_S_GT3	0x0C2A
115#define PCI_CHIP_HASWELL_SDV_B_GT1	0x0C0B /* Reserved */
116#define PCI_CHIP_HASWELL_SDV_B_GT2	0x0C1B
117#define PCI_CHIP_HASWELL_SDV_B_GT3	0x0C2B
118#define PCI_CHIP_HASWELL_SDV_E_GT1	0x0C0E /* Reserved */
119#define PCI_CHIP_HASWELL_SDV_E_GT2	0x0C1E
120#define PCI_CHIP_HASWELL_SDV_E_GT3	0x0C2E
121#define PCI_CHIP_HASWELL_ULT_GT1	0x0A02 /* Desktop */
122#define PCI_CHIP_HASWELL_ULT_GT2	0x0A12
123#define PCI_CHIP_HASWELL_ULT_GT3	0x0A22
124#define PCI_CHIP_HASWELL_ULT_M_GT1	0x0A06 /* Mobile */
125#define PCI_CHIP_HASWELL_ULT_M_GT2	0x0A16
126#define PCI_CHIP_HASWELL_ULT_M_GT3	0x0A26
127#define PCI_CHIP_HASWELL_ULT_S_GT1	0x0A0A /* Server */
128#define PCI_CHIP_HASWELL_ULT_S_GT2	0x0A1A
129#define PCI_CHIP_HASWELL_ULT_S_GT3	0x0A2A
130#define PCI_CHIP_HASWELL_ULT_B_GT1	0x0A0B /* Reserved */
131#define PCI_CHIP_HASWELL_ULT_B_GT2	0x0A1B
132#define PCI_CHIP_HASWELL_ULT_B_GT3	0x0A2B
133#define PCI_CHIP_HASWELL_ULT_E_GT1	0x0A0E /* Reserved */
134#define PCI_CHIP_HASWELL_ULT_E_GT2	0x0A1E
135#define PCI_CHIP_HASWELL_ULT_E_GT3	0x0A2E
136#define PCI_CHIP_HASWELL_CRW_GT1	0x0D02 /* Desktop */
137#define PCI_CHIP_HASWELL_CRW_GT2	0x0D12
138#define PCI_CHIP_HASWELL_CRW_GT3	0x0D22
139#define PCI_CHIP_HASWELL_CRW_M_GT1	0x0D06 /* Mobile */
140#define PCI_CHIP_HASWELL_CRW_M_GT2	0x0D16
141#define PCI_CHIP_HASWELL_CRW_M_GT3	0x0D26
142#define PCI_CHIP_HASWELL_CRW_S_GT1	0x0D0A /* Server */
143#define PCI_CHIP_HASWELL_CRW_S_GT2	0x0D1A
144#define PCI_CHIP_HASWELL_CRW_S_GT3	0x0D2A
145#define PCI_CHIP_HASWELL_CRW_B_GT1	0x0D0B /* Reserved */
146#define PCI_CHIP_HASWELL_CRW_B_GT2	0x0D1B
147#define PCI_CHIP_HASWELL_CRW_B_GT3	0x0D2B
148#define PCI_CHIP_HASWELL_CRW_E_GT1	0x0D0E /* Reserved */
149#define PCI_CHIP_HASWELL_CRW_E_GT2	0x0D1E
150#define PCI_CHIP_HASWELL_CRW_E_GT3	0x0D2E
151#define BDW_SPARE			0x2
152#define BDW_ULT				0x6
153#define BDW_SERVER			0xa
154#define BDW_IRIS			0xb
155#define BDW_WORKSTATION			0xd
156#define BDW_ULX				0xe
157
158#define PCI_CHIP_VALLEYVIEW_PO		0x0f30 /* VLV PO board */
159#define PCI_CHIP_VALLEYVIEW_1		0x0f31
160#define PCI_CHIP_VALLEYVIEW_2		0x0f32
161#define PCI_CHIP_VALLEYVIEW_3		0x0f33
162
163#define PCI_CHIP_CHERRYVIEW_0		0x22b0
164#define PCI_CHIP_CHERRYVIEW_1		0x22b1
165#define PCI_CHIP_CHERRYVIEW_2		0x22b2
166#define PCI_CHIP_CHERRYVIEW_3		0x22b3
167
168#define PCI_CHIP_SKYLAKE_ULT_GT2	0x1916
169#define PCI_CHIP_SKYLAKE_ULT_GT1	0x1906
170#define PCI_CHIP_SKYLAKE_ULT_GT3	0x1926
171#define PCI_CHIP_SKYLAKE_ULT_GT2F	0x1921
172#define PCI_CHIP_SKYLAKE_ULX_GT1	0x190E
173#define PCI_CHIP_SKYLAKE_ULX_GT2	0x191E
174#define PCI_CHIP_SKYLAKE_DT_GT2		0x1912
175#define PCI_CHIP_SKYLAKE_DT_GT1		0x1902
176#define PCI_CHIP_SKYLAKE_HALO_GT2	0x191B
177#define PCI_CHIP_SKYLAKE_HALO_GT3	0x192B
178#define PCI_CHIP_SKYLAKE_HALO_GT1 	0x190B
179#define PCI_CHIP_SKYLAKE_SRV_GT2	0x191A
180#define PCI_CHIP_SKYLAKE_SRV_GT3	0x192A
181#define PCI_CHIP_SKYLAKE_SRV_GT1	0x190A
182#define PCI_CHIP_SKYLAKE_WKS_GT2 	0x191D
183
184#define IS_MOBILE(devid)	((devid) == PCI_CHIP_I855_GM || \
185				 (devid) == PCI_CHIP_I915_GM || \
186				 (devid) == PCI_CHIP_I945_GM || \
187				 (devid) == PCI_CHIP_I945_GME || \
188				 (devid) == PCI_CHIP_I965_GM || \
189				 (devid) == PCI_CHIP_I965_GME || \
190				 (devid) == PCI_CHIP_GM45_GM || IS_IGD(devid) || \
191				 (devid) == PCI_CHIP_IVYBRIDGE_M_GT1 || \
192				 (devid) == PCI_CHIP_IVYBRIDGE_M_GT2)
193
194#define IS_G45(devid)		((devid) == PCI_CHIP_IGD_E_G || \
195				 (devid) == PCI_CHIP_Q45_G || \
196				 (devid) == PCI_CHIP_G45_G || \
197				 (devid) == PCI_CHIP_G41_G)
198#define IS_GM45(devid)		((devid) == PCI_CHIP_GM45_GM)
199#define IS_G4X(devid)		(IS_G45(devid) || IS_GM45(devid))
200
201#define IS_ILD(devid)		((devid) == PCI_CHIP_ILD_G)
202#define IS_ILM(devid)		((devid) == PCI_CHIP_ILM_G)
203
204#define IS_915(devid)		((devid) == PCI_CHIP_I915_G || \
205				 (devid) == PCI_CHIP_E7221_G || \
206				 (devid) == PCI_CHIP_I915_GM)
207
208#define IS_945GM(devid)		((devid) == PCI_CHIP_I945_GM || \
209				 (devid) == PCI_CHIP_I945_GME)
210
211#define IS_945(devid)		((devid) == PCI_CHIP_I945_G || \
212				 (devid) == PCI_CHIP_I945_GM || \
213				 (devid) == PCI_CHIP_I945_GME || \
214				 IS_G33(devid))
215
216#define IS_G33(devid)		((devid) == PCI_CHIP_G33_G || \
217				 (devid) == PCI_CHIP_Q33_G || \
218				 (devid) == PCI_CHIP_Q35_G || IS_IGD(devid))
219
220#define IS_GEN2(devid)		((devid) == PCI_CHIP_I830_M || \
221				 (devid) == PCI_CHIP_845_G || \
222				 (devid) == PCI_CHIP_I855_GM || \
223				 (devid) == PCI_CHIP_I865_G)
224
225#define IS_GEN3(devid)		(IS_945(devid) || IS_915(devid))
226
227#define IS_GEN4(devid)		((devid) == PCI_CHIP_I965_G || \
228				 (devid) == PCI_CHIP_I965_Q || \
229				 (devid) == PCI_CHIP_I965_G_1 || \
230				 (devid) == PCI_CHIP_I965_GM || \
231				 (devid) == PCI_CHIP_I965_GME || \
232				 (devid) == PCI_CHIP_I946_GZ || \
233				 IS_G4X(devid))
234
235#define IS_GEN5(devid)		(IS_ILD(devid) || IS_ILM(devid))
236
237#define IS_GEN6(devid)		((devid) == PCI_CHIP_SANDYBRIDGE_GT1 || \
238				 (devid) == PCI_CHIP_SANDYBRIDGE_GT2 || \
239				 (devid) == PCI_CHIP_SANDYBRIDGE_GT2_PLUS || \
240				 (devid) == PCI_CHIP_SANDYBRIDGE_M_GT1 || \
241				 (devid) == PCI_CHIP_SANDYBRIDGE_M_GT2 || \
242				 (devid) == PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS || \
243				 (devid) == PCI_CHIP_SANDYBRIDGE_S)
244
245#define IS_GEN7(devid)		(IS_IVYBRIDGE(devid) || \
246				 IS_HASWELL(devid) || \
247				 IS_VALLEYVIEW(devid))
248
249#define IS_IVYBRIDGE(devid)	((devid) == PCI_CHIP_IVYBRIDGE_GT1 || \
250				 (devid) == PCI_CHIP_IVYBRIDGE_GT2 || \
251				 (devid) == PCI_CHIP_IVYBRIDGE_M_GT1 || \
252				 (devid) == PCI_CHIP_IVYBRIDGE_M_GT2 || \
253				 (devid) == PCI_CHIP_IVYBRIDGE_S || \
254				 (devid) == PCI_CHIP_IVYBRIDGE_S_GT2)
255
256#define IS_VALLEYVIEW(devid)	((devid) == PCI_CHIP_VALLEYVIEW_PO || \
257				 (devid) == PCI_CHIP_VALLEYVIEW_1 || \
258				 (devid) == PCI_CHIP_VALLEYVIEW_2 || \
259				 (devid) == PCI_CHIP_VALLEYVIEW_3)
260
261#define IS_HSW_GT1(devid)	((devid) == PCI_CHIP_HASWELL_GT1 || \
262				 (devid) == PCI_CHIP_HASWELL_M_GT1 || \
263				 (devid) == PCI_CHIP_HASWELL_S_GT1 || \
264				 (devid) == PCI_CHIP_HASWELL_B_GT1 || \
265				 (devid) == PCI_CHIP_HASWELL_E_GT1 || \
266				 (devid) == PCI_CHIP_HASWELL_SDV_GT1 || \
267				 (devid) == PCI_CHIP_HASWELL_SDV_M_GT1 || \
268				 (devid) == PCI_CHIP_HASWELL_SDV_S_GT1 || \
269				 (devid) == PCI_CHIP_HASWELL_SDV_B_GT1 || \
270				 (devid) == PCI_CHIP_HASWELL_SDV_E_GT1 || \
271				 (devid) == PCI_CHIP_HASWELL_ULT_GT1 || \
272				 (devid) == PCI_CHIP_HASWELL_ULT_M_GT1 || \
273				 (devid) == PCI_CHIP_HASWELL_ULT_S_GT1 || \
274				 (devid) == PCI_CHIP_HASWELL_ULT_B_GT1 || \
275				 (devid) == PCI_CHIP_HASWELL_ULT_E_GT1 || \
276				 (devid) == PCI_CHIP_HASWELL_CRW_GT1 || \
277				 (devid) == PCI_CHIP_HASWELL_CRW_M_GT1 || \
278				 (devid) == PCI_CHIP_HASWELL_CRW_S_GT1 || \
279				 (devid) == PCI_CHIP_HASWELL_CRW_B_GT1 || \
280				 (devid) == PCI_CHIP_HASWELL_CRW_E_GT1)
281#define IS_HSW_GT2(devid)	((devid) == PCI_CHIP_HASWELL_GT2 || \
282				 (devid) == PCI_CHIP_HASWELL_M_GT2 || \
283				 (devid) == PCI_CHIP_HASWELL_S_GT2 || \
284				 (devid) == PCI_CHIP_HASWELL_B_GT2 || \
285				 (devid) == PCI_CHIP_HASWELL_E_GT2 || \
286				 (devid) == PCI_CHIP_HASWELL_SDV_GT2 || \
287				 (devid) == PCI_CHIP_HASWELL_SDV_M_GT2 || \
288				 (devid) == PCI_CHIP_HASWELL_SDV_S_GT2 || \
289				 (devid) == PCI_CHIP_HASWELL_SDV_B_GT2 || \
290				 (devid) == PCI_CHIP_HASWELL_SDV_E_GT2 || \
291				 (devid) == PCI_CHIP_HASWELL_ULT_GT2 || \
292				 (devid) == PCI_CHIP_HASWELL_ULT_M_GT2 || \
293				 (devid) == PCI_CHIP_HASWELL_ULT_S_GT2 || \
294				 (devid) == PCI_CHIP_HASWELL_ULT_B_GT2 || \
295				 (devid) == PCI_CHIP_HASWELL_ULT_E_GT2 || \
296				 (devid) == PCI_CHIP_HASWELL_CRW_GT2 || \
297				 (devid) == PCI_CHIP_HASWELL_CRW_M_GT2 || \
298				 (devid) == PCI_CHIP_HASWELL_CRW_S_GT2 || \
299				 (devid) == PCI_CHIP_HASWELL_CRW_B_GT2 || \
300				 (devid) == PCI_CHIP_HASWELL_CRW_E_GT2)
301#define IS_HSW_GT3(devid)	((devid) == PCI_CHIP_HASWELL_GT3 || \
302				 (devid) == PCI_CHIP_HASWELL_M_GT3 || \
303				 (devid) == PCI_CHIP_HASWELL_S_GT3 || \
304				 (devid) == PCI_CHIP_HASWELL_B_GT3 || \
305				 (devid) == PCI_CHIP_HASWELL_E_GT3 || \
306				 (devid) == PCI_CHIP_HASWELL_SDV_GT3 || \
307				 (devid) == PCI_CHIP_HASWELL_SDV_M_GT3 || \
308				 (devid) == PCI_CHIP_HASWELL_SDV_S_GT3 || \
309				 (devid) == PCI_CHIP_HASWELL_SDV_B_GT3 || \
310				 (devid) == PCI_CHIP_HASWELL_SDV_E_GT3 || \
311				 (devid) == PCI_CHIP_HASWELL_ULT_GT3 || \
312				 (devid) == PCI_CHIP_HASWELL_ULT_M_GT3 || \
313				 (devid) == PCI_CHIP_HASWELL_ULT_S_GT3 || \
314				 (devid) == PCI_CHIP_HASWELL_ULT_B_GT3 || \
315				 (devid) == PCI_CHIP_HASWELL_ULT_E_GT3 || \
316				 (devid) == PCI_CHIP_HASWELL_CRW_GT3 || \
317				 (devid) == PCI_CHIP_HASWELL_CRW_M_GT3 || \
318				 (devid) == PCI_CHIP_HASWELL_CRW_S_GT3 || \
319				 (devid) == PCI_CHIP_HASWELL_CRW_B_GT3 || \
320				 (devid) == PCI_CHIP_HASWELL_CRW_E_GT3)
321
322#define IS_HASWELL(devid)	(IS_HSW_GT1(devid) || \
323				 IS_HSW_GT2(devid) || \
324				 IS_HSW_GT3(devid))
325
326#define IS_BROADWELL(devid)     (((devid & 0xff00) != 0x1600) ? 0 : \
327				(((devid & 0x00f0) >> 4) > 3) ? 0 : \
328				((devid & 0x000f) == BDW_SPARE) ? 1 : \
329				((devid & 0x000f) == BDW_ULT) ? 1 : \
330				((devid & 0x000f) == BDW_IRIS) ? 1 : \
331				((devid & 0x000f) == BDW_SERVER) ? 1 : \
332				((devid & 0x000f) == BDW_WORKSTATION) ? 1 : \
333				((devid & 0x000f) == BDW_ULX) ? 1 : 0)
334
335#define IS_CHERRYVIEW(devid)	((devid) == PCI_CHIP_CHERRYVIEW_0 || \
336				 (devid) == PCI_CHIP_CHERRYVIEW_1 || \
337				 (devid) == PCI_CHIP_CHERRYVIEW_2 || \
338				 (devid) == PCI_CHIP_CHERRYVIEW_3)
339
340#define IS_GEN8(devid)		(IS_BROADWELL(devid) || \
341				 IS_CHERRYVIEW(devid))
342
343#define IS_SKL_GT1(devid)	((devid) == PCI_CHIP_SKYLAKE_ULT_GT1	|| \
344				 (devid) == PCI_CHIP_SKYLAKE_ULX_GT1	|| \
345				 (devid) == PCI_CHIP_SKYLAKE_DT_GT1	|| \
346				 (devid) == PCI_CHIP_SKYLAKE_HALO_GT1	|| \
347				 (devid) == PCI_CHIP_SKYLAKE_SRV_GT1)
348
349#define IS_SKL_GT2(devid)	((devid) == PCI_CHIP_SKYLAKE_ULT_GT2	|| \
350				 (devid) == PCI_CHIP_SKYLAKE_ULT_GT2F	|| \
351				 (devid) == PCI_CHIP_SKYLAKE_ULX_GT2	|| \
352				 (devid) == PCI_CHIP_SKYLAKE_DT_GT2	|| \
353				 (devid) == PCI_CHIP_SKYLAKE_HALO_GT2	|| \
354				 (devid) == PCI_CHIP_SKYLAKE_SRV_GT2	|| \
355				 (devid) == PCI_CHIP_SKYLAKE_WKS_GT2)
356
357#define IS_SKL_GT3(devid)	((devid) == PCI_CHIP_SKYLAKE_ULT_GT3	|| \
358				 (devid) == PCI_CHIP_SKYLAKE_HALO_GT3	|| \
359				 (devid) == PCI_CHIP_SKYLAKE_SRV_GT3)
360
361#define IS_SKYLAKE(devid)	(IS_SKL_GT1(devid) || \
362				 IS_SKL_GT2(devid) || \
363				 IS_SKL_GT3(devid))
364
365#define IS_GEN9(devid)		IS_SKYLAKE(devid)
366
367#define IS_9XX(dev)		(IS_GEN3(dev) || \
368				 IS_GEN4(dev) || \
369				 IS_GEN5(dev) || \
370				 IS_GEN6(dev) || \
371				 IS_GEN7(dev) || \
372				 IS_GEN8(dev) || \
373				 IS_GEN9(dev))
374
375
376#endif /* _INTEL_CHIPSET_H */
377